SU1425669A1 - Appangement for priority access to common storage - Google Patents

Abstract

The invention relates to computing technology and can be used in organizing the main data exchange between processors and shared memory modules in multiprocessor computing systems. The aim of the invention is to simplify the device. The device contains a priority block 2, an address switch 3, a decoder 4, a group of elements AND 1, three triggers 5.8.9, two elements OR 6.11, two elements AND 7.10 and a counter 12. The device serves the requests of processors to access common multi modular memory by trunk. The call to the required memory module occurs as a result of the priority connection of one of the processors that submitted the request for access to the trunk. The device with the help of the counter 12 controls the duration of time between adjacent ready signals, and in the case of whether this duration exceeds the permissible time, it generates a fault signal. 1 il. ГГ - ф (Л 4 :: Ю Р О5 о: со

Description

The invention relates to computer technology and can be used in multiprocessor compression systems with a common multi-module memory,

; The aim of the invention is a simpler device.

; The drawing shows a functional diagram of the device. The device contains a group of ifoB and 1 elements, priority block 2, iJop 3 switching addresses, descrambler 4, first trigger 5, first element OR 6, first element 11 and 7, third trigger 8, second trigger 9, second element 10 , the second element OR 11, the counter 12, the alarm input 13, the inputs 14 and 14, the address inputs 15, the inputs 16 and 17 of the initial setup and memory ready signals, the output 18 of the common access signal, the outputs 19 of the request confirmation signals, the exit 20 , outputs 21 signal fail.

At input 13, the device is supplied with synchronization signals for operation of counter 12 and trigger 8. At inputs 14, to the first inputs of a group of elements And | request signals are received for accessing shared memory from processors. On the information inputs 15 to the switch 3 addresses, the codes of the memory module numbers from the processors come along with the request signals. At input 16, the device receives a signal of the initial installation from the processors. Upon entry of the D 17, the device receives a ready signal from the working memory module. On exit 18 of trigger 8, a reversal signal is stored in the memory. To the outputs 19 of block 2, request confirmation signals are issued for informational connection to the mainlines of the processors and for removing their own request. The outputs 20 s de1 | 1 of the amplifier A are outputting signals to the memory modules for their commissioning. The output 21 from the output of the counter 12 is given a fault signal in case the waiting time of the ready signal exceeds the allowable one. The ready signal is a generalized memory signal and is formed by logically adding individual ready signals from each memory module. Trigger 5 sets the mode of operation of the device ™, trigger 8 serves to generate a common reference signal, and trigger 9 sets the mode of operation of the counter 12

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The device works in the same way.

After the arrival of the initial installation signal at input 16, trigger 5 is set to the zero state and opens a group of elements AND 1 and element 7. As a result, the device is ready to receive and process the request signals. If it is necessary to access the shared memory, the processor issues a request signal and the address of the required memory module to the inputs 14 and 15, respectively. In the case of occurrence of the indicated signals (in the form of logical units) at the inputs 14 in any combination, they pass through a group of elements And 1 and arrive at the inputs of block 2 and the element OR 6. According to the highest priority request, block 2 at the corresponding output issues a request confirmation signal, which is fed to the highest priority processor that submitted the request. In addition, according to this signal, the switch 3 passes to the input of the decoder 4 the corresponding address of the memory module, which is decoded into the signal of addressing the address m module.

In addition, as indicated earlier, the presence of at least one request signal using the OR elements. 6, and 7. provides a signal in the form of a logical unit at the D input of trigger 8 and S input of trigger 9. As a result, the trigger 8 is set to 1 according to the nearest clock pulse, thus forming a generalized address signal at output-18 and simultaneously setting 1 trigger 5. After that the requests are blocked, and the trigger 8 is prepared for a reset on the following clock pulse, which arrives at input 13.

The servicing processor, having received a response confirmation of the request, connects to the information trunk and then removes its request. In addition, the trigger 9, installed in 1, through the element And 10 includes in the operation of the counter 12,

0 to the countable input of which through the AND 10 element passes the clock pulses from the input 13, the Counter is calculated for a certain time interval, usually exceeding the real time interval between adjacent readiness signals. If there is no next ready signal or a significant delay, the counter starts a new cycle with its output signal.

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bots of the device and output to output 21 is a memory fault signal, which can be wired to the interrupt system of one of the processors.

If the next ready signal arrives on time, then it gives rise to the next cycle of the device, simultaneously dropping trigger 9 and counter 12 using the OR 11 element.

Formula of the invention The device for priority treatment

A shared memory containing a priority block, the outputs of which are connected to the outputs of the device request confirmation and the control inputs of the address switch, the outputs of which are connected to the inputs of the decoder, the outputs of which are device access outputs, the inputs of the device requests are connected to the first inputs of the corresponding elements AND groups, whose codes are connected to the inputs of the priority block, the information inputs of the address switch are address inputs of the device, characterized in that, in order to simplify stroystva, it contains two elements or two elements

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And, three triggers and a counter, the second input of the elements of the AND group is connected to the inverse output of the first trigger and the first input of the first element AND, and the outputs of the AND elements of the group are connected to the inputs of the first OR element, the output of which is connected to the second input of the first element And the output which is connected to the S-input of the second trigger and the P-input of the third trigger, the output of which is connected to the output of the common signal of the device and to the S-input of the first trigger, the C-input of the third trigger is connected to the clock input of the device and the first input Ohm of the second element And, the second input of which is connected to the unit output of the second trigger, and the output is connected to the counting input of the counter, the output of which is connected to the code of the device’s signal and to the first input of the second element OR, the second input of which is connected to the input of the initial installation of the device, the third input of the second element OR is connected to the readiness signal of the device memory, and the output is connected to the counter reset input, the second trigger reset input and the C-input of the first trigger, whose D input is connected to potential 3 ml devices.

Claims (1)

Claim A device for communicating with priority memory, containing a priority block, the outputs of which are connected to the outputs of the confirmation device requests and to the control inputs of the address switch, the outputs of which are connected to the inputs of the decoder, the outputs of which are the output addresses of the device, the input requests of the device are connected to the first inputs of the corresponding elements And the groups whose outputs are connected to the inputs of the priority block, the information inputs of the address switch are the address inputs of the device, distinguishing Esja in that, to simplify the apparatus, it comprises two OR gates, two elements And, three triggers and a counter, and the second inputs of the AND elements of the group are connected to the inverse output of the first trigger and the first input of the first AND element, and the outputs of the elements of the AND group are connected to the inputs of the first OR element, the output of which is connected to the second input of the first AND element, the output of which is connected to the S-input of the second trigger and the D-input of the third trigger, the output of which is connected to the output of the common signal of the device and the S-input of the first trigger, the C-input of the third trigger is connected to the synchronization input of the device and the first input the second AND element, the second input of which is connected to the single output of the second trigger, and the output is connected to the counting input of the counter, the output of which is connected to the output of the device failure signal and to the first input of the second OR element, the second input of which is connected to the input of the initial installation of the device, the third the input of the second OR element is connected to the input of the readiness signal of the device’s memory, and the output is connected to the counter reset input, the reset input of the second trigger, and the C-input of the first trigger, whose D-input is connected to ground potential troystva.