SU1531097A1 - Priority device - Google Patents

Abstract

The invention relates to computing. The purpose of the invention is to expand the field of application of the device due to the possibility of operating in both relative priority mode and absolute priority and cyclical service of requests. The device contains two registers 1.9, a group of 5 And elements, a pulse generator 14, an And 15 element, an OR 17 element, a memory block 13. The device can work in different priority systems, it allows to dynamically move from one system to another during the mode setting, randomly changing the order of service requests without changing the structure of the device. 1 il.

Description

The invention relates to computing technology, in particular, to devices for controlling information exchange by a priority service device, and can be used in the development of computing devices.

: The aim of the invention is to expand the field of application of the device due to the possibility of operating in both relative and absolute priority mode and cyclical servicing of requests,

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The drawing shows a block diagram of the device priority.

The device contains a register 1, triggers 2-4 register 1, a group of elements And 5, elements And 6-8 groups 5, register 9, triggers 10-12 register 9, memory block 13, pulse generator 14, element 15, trigger 16 , element OR 17, element AND 18, interrogation inputs 19-21 of the device, input 22 of the initial installation of the device, input 23 of the end of service of the device, outputs 24-26 of the device, inputs 27 and 28 of the device mode.

The device can operate in the service platform with relative priorities, absolute priorities, as well as in the cyclic request processing mode.

Consider the operation of the device in the service mode requests with absolute priority.

After the initial pulse device arrives at input 22, it enters registers 1 and 9, and also through element OR 17 on trigger 16, after which registers 1 and 9 and trigger 16 are zeroed and the device is ready for pq, bot.

Assume that trigger input 2 has the highest priority, trigger input 4 has the lowest priority. When requests are received for inputs 19-21, they are stored in register 1, i.e. the triggers 2-4 of this register go to one state. With an alternate clock pulse from the generator 14, the requests received into register 1 are rewritten through a group of 5 elements into register 9. From this code, which is in register 9, and the code defined absolute priority mode at inputs 27-28, from memory block 13 is selected a cell containing one at that time

0

five

five

five

the number that corresponds to the request with the highest priority of this combination of requests, after which a high level potential appears at the corresponding output of the device. For example, if a request is received on INPUT 20, then in memory block 13 a cell containing a unit in the second bit is selected, and at the output 25 of the device, the potential of a unit level is reached. The trigger 16 is always in the zero state, since its information input from the first control output of the memory block 13 receives a single level signal, and each clock pulse from the generator 14 arriving at the clock input of the trigger 16 confirms its zero state, V.-which is translated after the initial installation. Thus, each pulse from the generator 14 passes through the element AND 15 to the group of 5 elements AND, since the third input of the element AND 15 receives the signal of a single level from the second control output of the memory block 13. Meanwhile, the US-1YM every clock pulse from generator 14 rewrites newly received requests from register 1 to register 9. Suppose 1 that after starting the processing of a request received at input 20, a request comes in at input 19, then with the arrival of a clock pulse from the generator 14, it is rewritten to register 9. In memory block 13, a cell containing the unit only in the first bit is selected, so a potential of zero level is set at the device output 25, and a single level at output 24. This will interrupt the request service on the second channel and start the service on the first channel. After the arrival of the end-of-service pulse, only the trigger of register 9 (trigger 10) that corresponds to the request channel through which the service has been completed and completed, is zeroed. After zeroing one of the (-10-12-12 register 9 triggers, the corresponding trigger of register 1 is triggered (trigger 2). In memory 13, the cell with the unit in the second bit is again selected. The output 24 becomes zero, and the output 25 - single, thereby the device returns to the interrupted request service.

In the case of operation of the device in the relative priority discipline, the limit is only that after the arrival of the first polling pulse from the generator 14, the trigger 16 is set to one state. To do this, its information input is connected to the first control output of the memory unit, the zero is received. Thus, the AND element 15 is closed until the service end impulse arrives at the device input 23, and the trigger 16 does not return to the zero state. Consequently, the request that is currently being processed is not interrupted, and if a higher priority request arrives, its service will start only after the end of the service of the first request. Moreover, for a time equal to the polling pulse duration from generator 14, memory block 13 is transferred through element 18 to the address range where zero level signals are generated on the memory output group, regardless of the group of address inputs, which makes it possible to avoid transients at the outputs of the priority device during the census of requests from register 1 to register 9.

In the case of working in the cyclical mode of servicing requests, any unit at the output of register 9 transfers the memory block to the state when the second control output contains a zero that closes AND 15, i.e. recording pulses do not fall on register 9 until all applications recorded in register 9 earlier are served on a group of memory inputs, zero signals are not received, so that the corresponding memory is selected in the memory block. the cell and the second control output of the memory unit will be set to a single signal.

After this, the maintenance cycle may be repeated.

Claims (1)

Invention Formula A priority device containing two registers, a group of elements AND, the first element AND, a pulse generator, an element OR, and the device's request inputs are connected to the input 6 1 1 It ten 15 20 25 Set in 1 nepBOJ o register, outputs of elements AND groups are connected to inputs of installation in 1 second register, the output of each bit of the second register is connected to the clock input of the same name of the first register, input of the beginning setting and input of the end of service of the device are connected to inputs of the OR element, the initial setup input of the device is connected to the reset inputs of the first and second registers, the service end input of the device is connected to the clock input of the second register, so that, in order to expand the area of name due to the ability to work both in relative mode and absolute priority and cyclic service of requests, the device; about contains the second element AND, the trigger and memory block 1 AND, whose group is connected with the group of outputs of the device and is connected to the first a group of information: x input of the second register, the second group of information inputs of which are connected to the potential of the logic zero of the device, the first and second inputs of the device mode are connected respectively to the first and second ad1) memories of the memory unit, mp This address input and the address input group of the node are connected to the output of the first element I and to the outputs B and oporo of the register, the first group of information inputs of the first register is connected to the input of the logical zero of the device, the reset input of the trigger is connected to OR, the first and second information inputs of the trigger are connected respectively to the inverse input of the first element I and to the first output of the memory unit, the second output of which dp is connected to the first input of the second element And, the second .and the third inputs of which are connected respectively to the inverse output of the trigger and to the output of the pulse generator and to the clock house of the trigger, the output of the second element And is connected to the direct input of the first element And and to the first inputs elements And groups, the second input of each of which is connected to the output of the same-named bit of the first register and to the second information input of this bit. thirty 35 40 55