SU1406794A1 - Pulse recurrence rate to d.c. current or voltage converter - Google Patents

Abstract

The invention relates to information and measurement technology. The purpose of the invention is to expand and expand the range of transformations. The converter includes an input driver 1, counters 3 and 7, memory blocks 10 and 11, a control block 5 and a reference generator 9. Introduction of counters 14 and 15, a synchronization block 2, a setting signal generator 17 The trigger 18, the pulse amplitude stabilization unit 19 and the low-pass filter 20 eliminate the need for using two digital-to-analogue converters, which increases the conversion accuracy. Due to the fact that the conversion cycle is one period of the input frequency instead of two, the speed of the device is increased. The description provides an example of the execution of the control block 5. 1 hp ff, 2 ill. i (L

Description

vj

with

The invention relates to information technology and can be used to convert the pulse frequency to direct current.

The aim of the invention is to improve the accuracy, speed and rasigi rheniyu conversion range.

Pa figs. Figure 1 shows a functional diagram of a pulse frequency converter in direct current or voltage; in fig. 2 - timing charts of the device.

The converter (Fig. 1) contains an input driver 1, a synchronization unit 2, the input of which is connected to the output of the imaging device 1, and an output with a countable summation in :: the counter 3 and with the first input 4 of the control unit 5. The second input 6 of block 5 is connected to the high-output output of counter 7. The counting summing input of counter 7 and the synchronization input of block 2 are connected to the first output 8 of the reference generator 9. The outputs of counters 3 and 7 are connected to the code inputs of blocks 10 and 11, respectively. ti. The write inputs of blocks 10 and 11 are connected to the first output 12 of block 5, the second output 13 of which is connected to the installation inputs in O counters 3 and 7. The outputs of blocks 10 and 11 are connected respectively to the code inputs of the third 14 and fourth 15 counters, counting subtractors ( The inputs are connected to the second output 16 of the reference generator 9. The transfer output of the counter 15 is connected to the input of the installation signal generator 17, the output of which is connected to the installation inputs of the counters 14 and 15 and the first input of the trigger 18, the second input of which is connected to the transfer output 14 and the output to the input of the pulse amplitude stabilization unit 19. The output of the unit 19 is connected to the input of the low-pass filter 20, the output of which reduces the output signal.The unit 5 contains an element 21, the first one: and the second inputs are connected respectively to the first 4 and the second 6 inputs of block 5, the delay element 22, the shaper of the recording signal 23 and the shaper of the reset signal 24. The input of the element 22 is connected to the output of the AND element 21, and the output to the input of the shaper 23, the output of which is connected to the first output 12 of the block 5 and c

0

five

0

five

0

five

0

five

0

five

the input of the imaging unit 24, the output of which is connected to the second output 13 of the unit 5. The unit 19 may contain, for example, a stabilized voltage source and a switch controlled by the input signal of the unit 19 and alternately connecting its output to the common bus and to the stabilized voltage source. Each of the blocks 17, 22, 23 and 24 can be performed, for example, on a D-flip-flop.

FIG. 2 timing diagrams are indicated by the following positions: 25 — signal at altitude 8 of generator 9; 26 is a signal at the output of the imager 1; 27 - signal at the output of block 2; 28 - signal at the input 6 of block 5; 29 is a signal at the output of the element 21; 30 is the signal at the output of the element 22; 31 - the signal at the output 12 of block 5; 32 - signal at output 13 of block 5.

The device works as follows.

The arbitrary input signal of the converted frequency FK is converted by the former 1 into a series of rectangular pulses with a steep front. Unit 2 synchronizes the input signal on the leading edge of one of the pulses in code 8 of the reference oscillator 9. The device operates cyclically, and at the beginning of each cycle, the counters 3 and 7 are set in an O signal at the output 13 of the unit 5 in end of the previous cycle. During the cycle, counter 3 counts the impulses of the input frequency FX, and counter 7 represents the frequency pulses F, from output 8 of the reference oscillator 9. When the frequency pulses F are filled, half the capacitance of the counter 7, its highest bit assumes state 1 and at input 6 Unit 5 appears as a single potential. Next, the next pulse at the output of block 2, entering the input 4 of block 5, causes the appearance of a pulse at the output of the element 21, which, having passed through the element 22 of the delay, starts the driver 23, a pulse. at the output of which is fed to the recording inputs of blocks 10 and 11, as a result, the output codes of counters 3 and 7 are recorded in blocks 10 and 11, respectively. The delay time of element 22 is chosen so that the state of all bits of the first 1 time can be set. In this case, in block 10 will be

zapigpno number of M, yugitsto chig.p nepucidov NOKHNP1CH) signal time cycle T | from the beginning of the cycle dp of the moment of recording, and in block 11 - a number equal to peris1DO1 part

N,

behind

NT,

and up to

(one)

where t

J

p x

where t, 1 / f; T 1 / F - respectively, the following periods of the input itMnynbCOB and the pulses of the reference generator 9 at its output 8.

In order to ensure a small error in the discreteness of the TC, MHoi o must be chosen greater than T, and the counter capacity

T.

7 is greater than the magnitude of F where T

I c max

- c.zhaks maximum cycle time Next, the back edge of the write pulse is started by the imaging unit 24 and at its output sets counters 3 and 7 to O. Duration

The pulses of the formers 23 and 24 are selected so that the setting O ends before the next pulse from the output 8 of the reference oscillator 9 begins. Then the whole cycle is repeated. The counting subtractive inputs of the counters 14 and 15 are pulses of frequency F from the output 16 of the reference generator 9, and F F,. At the moment when the counter 15 passes through the zero state, a signal appears at its transfer output that triggers a form (Vatel 17, at the output of which a short pulse appears, arriving at the installation inputs of counters 14 and 15 and to the first trigger input 18. The last one this is set to one state.At the same time, the codes stored in the memory of blocks 10 and 11 are transferred to the bits of counters 14 and 15. Next, in the process of counting frequency pulses F, the codes recorded in counters 14 and 15 decrease to zero. . Due to the fact that, counter 1 4 reaches a non-positive state earlier than counter 15. At the same time, the signal at its transfer output transfers the trigger 18 to the zero state, then the counter 15 reaches the zero state, the transfer signal from its output sets the counters M and N, and the whole the process repeats periodically. {in the trigger of the 18 forms of the FIRST LATERATELY (GMPU. H1HCHNY SIGNN, D.CHITSLIIiiTTi1gpulse which t '

behind

before

is number M: period ness

 N / F.

 and T H / 1; Duration I, - NUMBER 1M N: T

The pulses from the output of trigger 18 are stabilized in amplitude by means of 10 E1 block 19, and their average value is equal to: t ,.

wed

-g

(2)

where F is the amplitude of the 1g pulse,

Substituting in (2) the expression we get

F.

(one),

(3)

20 To obtain the desired pulse ratio (so that at the top of the range it is close to one), the connection of the counter 14 to the block 10 can be made

25 by shifting K bits right.

With

by this

t ,.

 R

M 2 K

; .Л

if the input frequency decreases to zero, the write pulse disappears, which can lead to distortion

output information. To prevent this from occurring, it is possible to turn on the driver from the trailing edge of the output pulse of the high bit of counter 7 to input the signal

installation About block 10 memory.

The delay time of the element 22 is chosen such that the state of all the bits of the counter 3 has been set. Forming 23 is required

to form a recording pulse on blocks 10 and 11 (diagram 31), and the pulse duration must be sufficient for recording. The reset pulse (diagram 32) on counters 3 and 7 must come after the end of the write pulse, therefore a driver 24 is required to start from the trailing edge of the driver 23. At the moment when the counter 15 passes through the zero state at its output

A formatting device 17, on whose entry a short pulse appears, arriving at the installation inputs of counter B lA and 15. At this moment the code from blocks 10 and 11 is recorded at counters 1 and 15. When counter 15 passes through the zero state, starting the block 17, and from the output of block 17 the corresponding code is set into the counter 15. This setting impulse arrives earlier than the next counting pulse with a frequency F comes, since, for example, the delay time in block 17 is not more than 50 F, but , 1000 kHz.

Block 2 synchronizes the input signal on the leading edge of one of the pulses at the output 8 of the reference generator 9 (diagram 25), i.e. at the synchronizer output, there are pulses of frequency F (diagram 27), coinciding on the leading edge of the pulses with the pulses at the output 8 of the reference generator 9. Block 19 may contain, for example, a source of stabilized voltage and a switch controlled by the input signal of block 19 and alternately switching it output to a common bus and to a source of stabilized voltage. The frequency of polling counters 15 and 14 is equal to

ras ShireNPO lapapa oip reorganized without y1 (1 11 11 pogreipyus.

Thus, an expansion of the conversion range and an increase in accuracy is achieved. Improving the accuracy of 1ccc also by eliminating the error of two digital-to-analog converters. The increase in speed at the minimum input frequency is achieved by the fact that the conversion cycle is one period of the input frequency instead of two.

Claims (2)

1. Pulse-to-current-frequency converter or voltage converter containing an input driver, the first counter, the output of which is connected to the input of the first memory block, the second counter whose output is connected to the input of the second memory block, control unit, the first output which is connected to the recording inputs of the first and second memory blocks, and the second output to the installation inputs in the first and second counts chikov, and the reference generator, about tl and F fj. The codes on the outputs of the blocks are due to the fact that, with 10 and 11 are set at a frequency of F 1 / TC. During the time Tz, the codes on the outputs of blocks 10 and 11 do not change. By this, codes and codes are written with frequency to blocks 14 and 15, respectively, and, for example, TC 0.5 s; FJ 1000 kHz; N 3000, then 330 Hz:. 2 Hz. The discreteness error of the proposed device is determined by the number of pulses N, which fill the interval in M periods of the input signal. In the case of reducing the input frequency in the whole range of input frequencies, the number M is reduced to one, but the number N cannot be less than half the capacity of the counter 7, i.e. P / 2 N.P, where P is the capacity of counter 7, therefore, the accuracy does not decrease as the input frequency decreases, and the discreteness error can be obtained sufficiently small over the entire conversion range by choosing the counter capacity. I Considering that the minimum input frequency corresponds to M 1, and the maximum - full filling of the counter 3, due to the choice of the capacitance of the latter, significant results can be obtained 35 1) Accuracy accuracy, fast speed and range expansion is converted, the third and th counters are entered into it, the synchronization unit 40 trigger, stabilization unit of pulses and filter of the lower clock than the input of the synchronization unit to the output of the input form and output - to the counting summation of the input of the first counter and the input of the control unit; the output of the second counter is printed to the second input of the control unit g outputs and the second block of mi are connected to the corresponding inputs of the third and fourth counters, the first output of the reference generator is connected to the synchronization input of the synchronization unit and the summing input of the second, and the second output is connected with the subtracting inputs of the third right counters, the output of the fourth counter is connected to the signal conditioner of the mouth, the output of which is connected to the input of the third and fourth chips and to the first input of the trigger 50 55 the purpose five 1) Penetration accuracy, speed and expansion of the conversion range, the third and fourth counters, a synchronization unit, a setup driver, 0 a trigger, a pulse amplitude stabilization unit and a low-pass filter, the synchronization unit input connected to the output of the input driver, and the output to the counting summing input of the first counter and the first input of the control unit, the higher discharge output of the second counter, g the outputs of the first and second memory blocks are connected respectively to the code inputs of the third and fourth counters, the first output of the reference generator is connected to the synchronization input of the synchronization unit and the counting cy The second output is provided with counting subtracting inputs of the third and fourth counters, the transfer output of the fourth counter is connected to the input of the setup signal generator, the output of which is connected to the installation inputs of the third and fourth counters and to the first trigger input. 0 five the second input of which is connected to the transfer output of the third counter, and the output - to the input of the pulse amplitude stabilization unit, whose code is connected to the input of the low-pass filter. 2. The converter according to claim 1, T is characterized in that the control unit comprises an element AND, a delay element, a recording signal shaper and a signal shaper reset, the output of which is connected to the second output of the control unit, and the input to the first output of the control unit and the output of the recording signal generator, the input of which is connected to the output of the delay element, the first and second inputs of the And element are connected respectively to the first and second inputs of the control unit, and output - with the input of the delay element. Phi. i