SU1394394A1 - Pulse sequence frequency converter - Google Patents

Abstract

The invention relates to electronics. The purpose of the invention is to expand the range of changes in the coefficient. frequency conversion and increased stability of the output pulse period. The device contains r-1 frequency reference, frequency divider with variable coefficient. division (DCF) 2, the unit 3 measuring the period of the pulse. ow, register 4 memory, counter 5, 1L control signal generator (FUS) 8. A puller expander 6, counter 7, and DCPC 9 are input. The input pulses are fed to the DCPC 9 signal input, M values are set at input 10. With DCFK 9, the pulses arrive at the FUS 8, where they are synchronized by the pulses of the reference frequency and the duration of the pulse. At the same time, at the output of the FUS 8, a pair of short pulses follows, others for other pulses. The 1st pulse records information from the counter of block 3 into the register 4j and puts in the counter 7 a coefficient code. dividing L from input 11 and starting the expander 6, which will generate the 1st output pulse from the next row. The 2nd pulse resets the counter of block 3 and enters the coefficient codes in the DCPC 2 and 9 registers. dividing L and M. After the end of the output pulses of the FUS 8, the next cycle of operation begins, 3 sludge. §

Description

and

70

Phi.1

11394394

The invention relates to electronics, automation, computing, digital and measurement technology, and can be used to process information received in the form of a periodic sequence of rectangular logic pulses.

The purpose of the invention is to expand the range of changes in the coefficients of the converter | g bots.

15

The second pulse from the output of the imaging unit 8 resets the counter 12 of the block 3 and enters the registers of the first and second dividers 2 and 9 of the codes of the division factor L from input 11 and M from input 10, respectively. After the termination of the output pulses of the driver 8, each next cycle begins.

the counter 12 of block 3 receives pulses from the generator 1 through the first divider 2 with a variable integer division factor. The number of pulses recorded in the counter 12 block 3 is equal to

s - tv m

AND

where t

Bh

25

frequency development and increased stability of the output pulse period.

FIG. 1 shows a block diagram of a pulse frequency converter; in fig. 2 - unit for measuring the pulse following period; in fig. 3 is a block diagram of the control signal generator.

The frequency converter of the next 20 pulses contains the oscillator 1 of the reference frequency, the first divider 2 frequencies with a variable division factor, the unit 3 measures the period of the pulse following, the register 4 of the memory, the first counter 5, the expander 6 pulses, the second counter 7, the driver 8 of the control signals the second divider 9 frequency with a variable division factor; the input 10 of the control signal of the second divider 9; the input 11 of the control signal of the first divider 2.

The pulse period measurement unit comprises a counter 12 and an inverter 13.

The driver of the control signals contains a trigger 14, a delay element 15 and an inverter 16.

The pulse frequency converter operates as follows, Q This will overwrite

35

- the period following the input

pulses; M - division ratio second

divider 9;

i, - the period of pulses from the output of the first divider 2 After the arrival of the next pulse from the second divider 9, the N code from the counter 12 of the block 3 is transferred to the register 4, the N code rewrites the signal from the second counter 7 to the first counter 5 and its operation is allowed. The next pulse from the imaging unit 8 resets the counter 12 of block 3 and writes the division factors L and M to the registers of the first and second dividers 2 and 9. The pulses from the generator 1 are fed to the first counter 5 for the period fg. The output signals are generated by zeroing signals of the first counter 5 by the expander impulses with a period.

The input pulses arrive at the signal input of the second divider 9 frequency with an n-time division factor, the value of which is set to input 10. From the output of the second divider 9, the divided input pulses come in shaper 8, where they are synchronized by the reference frequency pulses and are generated in duration. In this case, at the output of the imaging unit 8, a pair of short, successive pulses take place. The first of these pulses records information from the counter 12 of block 3 into register 4, the generator of the second counter 7, the code of the division factor L from input 11, and starts the expander b, which produces the first output pulse from the next one of the row.

45

50

55

yes register 4 to the first counter 5 through the second counter 7 output pulses. As soon as the second counter 7 checks the number of output pulses equal to L, it closes the operation of the first counter 5 at the control input. Following the output pulse will be generated only by the arrival of a pulse from the second divider 9 frequency of the input pulses. Further, the operation cycle is repeated until the code is changed in the counter 12 of block 3. At the same time, Tg, is the period of the pulses arriving at the first counter 5. As of equality

T „- in M

the ratio of the periods of input and output pulses transformed takes the form

g bots converter.

five

The second pulse from the output of the imaging unit 8 resets the counter 12 of block 3 and enters the registers of the first and second dividers 2 and 9 of the codes of the division factor L from input 11 and M from input 10, respectively. After the termination of the output pulses of the driver 8, each next cycle begins.

the counter 12 of block 3 receives a pulse; sy from generator 1 through the first divider 2 with a variable integer division factor. The number of pulses recorded in the counter 12 block 3 is equal to

s - tv m

AND

where t

Bh

This will overwrite the

- the period following the input

pulses; M - the division ratio of the second

divider 9;

i, is the pulse period from the output of the first divider 2. After the next pulse arrives from the second divider 9, the code N from the counter 12 of block 3 is transferred to register 4, the signal from the second counter 7 causes the code N to be copied to the first counter 5 and its operation is allowed. The next pulse from the driver 8 resets the counter 12 of block 3 and records the division factors L and M in the registers of the first and second dividers 2 and 9. The pulses from the generator 1 are sent to the first counter 5 for the period fg. The output pulses are generated by the zeroing signals of the first counter 5 by the expander with a period.

This will overwrite the

yes register 4 to the first counter 5 through the second counter 7 output pulses. As soon as the second counter 7 checks the number of output pulses equal to L, it closes the operation of the first counter 5 at the control input. Following the output pulse will be generated only by the arrival of a pulse from the second divider 9 frequency of the input pulses. Further, the operation cycle is repeated until the code is changed in the counter 12 of block 3. At the same time, Tg, is the period of the pulses arriving at the first counter 5. As of equality

T „- in M

the ratio of the periods of input and output pulses transformed takes the form

.

Tv

Nb, L

 Mflr M

L is the first division coefficient.

divider 2 (integer

number). way

T

klX

T L

With M values, the L-converter works as a frequency divider of the input pulses. With values of M, the L converter works as a frequency multiplier. With values of M "L, the converter operates as a frequency follower.

Claims (1)

Invention Formula A pulse frequency converter containing a series-connected reference frequency generator, a first frequency divider with a variable division factor, a pulse-period measurement unit, a memory register, and a first counter. as well as a driver of control signals, the first output of which is connected to the control input of the memory register, while the second output of the controller of the control signals is connected to the installation inputs of the first frequency divider with a variable division factor and the unit for measuring the pulse period, the output of the reference frequency generator is connected with 0 five 0 five 0 five with the counting input of the first counter and the first input of the control signal generator, characterized in that, in order to expand the range of changes in the frequency conversion coefficients and increase the stability of the period of the output pulses, a second frequency divider with a variable division factor is introduced, the output of which is connected to the second input of the control generator signals and serially connected pulse expander and a second counter, the output of which is connected to the control input of the first counter, the first in the control signal generator path is connected to the control inputs of the pulse expander and the second counter, the second output of the control signal generator is connected to the installation input of the second frequency divider with a variable division factor, the output of the first counter is connected to the signal input of the pulse extender, and the control signal input the second counter is connected to the input of the control signal of the division factor of the first frequency divider with a variable division factor; the signal input of the second divides L variable frequency. the division factor and the pulse expander output are respectively the signal input and the output of the pulse frequency converter. Fi.2 Fa.H