SU1176360A1 - Device for transmission and reception of information - Google Patents

Abstract

A DEVICE FOR TRANSFER AND RECEIVING INFORMAVDI, which contains an element NOT to the transmitting side, the output of which is connected to the first input of the AND element, the amplifier whose output is connected to the information bus, the OR element, on the receiving side an amplifier whose output is connected to the information bus, the And element, characterized in that, in order to increase the information content of the device, the shift register, the synchronizer, the counter, the first inputs of the shift register are entered on the transmitting side, the information inputs of the device, the output of the register The shift side is connected to the first input of the synchronizer, the first output of which is connected to the second input of the AND element, the output of which is connected to the amplifier input, the output of the amplifier is connected to the first input of the OR element, the second input of which is connected to the second output of the synchronizer, the output of the OR element is connected to the second input synchronizer, the second input of the shift register and the first input of the counter, the output of the counter is connected to the input of the element NOT, the output of which is the first control signal of the device, the combined third input of the reg The shift source and the second input of the counter are the first control input of the device, the encoder, counter, shift register, pulse generator, whose output is connected to the first input (I of the I element, whose output is connected to the first input of the counter, which outputs connected to the first entrances of the encoder, the first output of the encoder is connected to the input of the amplifier and the first input of the shift register, the second output of the encoder is connected to the second input of the AND element, combined into a second input of the encoder and the second input of the recorder The offset shifts are connected to the ISCO O bus, the counter input is the second control input of the device, the third output of the encoder and the outputs of the shift register are the second control and information respectively; device outputs.

Description

The invention relates to automation and computing, can be used to exchange discrete information between asynchronous devices, 5

The aim of the invention is to increase the information content of the device.

Figure 1 is a block diagram of a device for transmitting data; Fig. 2 is a schematic diagram of a synchronizer, option; FIG. 3 is a schematic diagram of an encoder for an information word of size N 2m, where mn is a positive integer, option; FIG. A is a schematic of the registrar 15, option

The device for transmitting and receiving information contains the transmitting side 1, bus 2 information, receiving side 3, shift register 4, syn-20 chroniser 5, counter 6, element OR 7, element 8, element 8, element 9, amplifier 10, control inputs 11 and 12, information inputs 13, amplifier 14, encoder 15, shift register 16, element 25, 17, counter 18, pulse generator 19, control input 20, control output 21, information outputs 22, triggers 23 and 24, generator 25 pulses, element 26, element 30, NOT 27, inputs 28 and 29 of the synchronizer, outputs 30 and 31 of the synchronizer, element And 32, the element OR 33, the element And 34, the elements NOT 35 and 36, the element And 37, the information inputs 38 of the torus cipher-jj, the control input 39 of the encoder, the outputs 40 - 42 of the encoder, trigger 43, shift register 44, inputs 45 and 46 registers, outputs 47 registers.

The device works as follows.

The receiving side 3 forms into the information bus 2 a control sequence of positive 45 impulses for receiving the information word (data). The transmitting side 1 inserts the negative receive signals into the positive pulses of the block. If it transmits 1 and does not do this, if it sends O about the EU-50, if the transmitting side is not ready (no data), then it supports in the information bus 2 low potential. If the receiving party is not ready to receive (information word in 16-gister 16), then it also maintains low potential in bus 2.

Assume that the transmitting side is ready to transmit information and, at the receiving side, a counter 18 is sent to control input 20 and received a pulse, which sets the counter 18 to its initial (o) state. In this case, the output of the encoder 15 and, accordingly, the output of amplifier 14- , as well as element And 17 sets a high level of potential. Alternator pulses 19 are allowed to pass through element 17 and to the input of counter 18. The counter generates a sequence of pulses (the length of which corresponds to the information word) arriving at information bus 2. After the last pulse of the sequence passes, the level O of the element 17 is generated, preventing the counter from working 18. At the same time, the information bus 2 also sets the level of the logical O and the operation stops (the information word is received). The pulses from the output of the encoder 15 also arrive at the input of the register 16. On the falling edge of the pulse (i.e., after receiving the bit), the information in the register 16 is shifted by one bit. This can be achieved as follows.

The trigger 43 of register 16 before each pulse is set to state O. If, during a pulse, the transmitting side forms 1 (inserts a low level), then the trigger 43 is set by this pulse to state 1, and then on the falling edge its state is written to the register 44 shift.

Assume that the transmitting side is not ready to transmit. On the receiving side, by pulse, Counter 18 is set to the O state, and a level is generated at the output of the encoder 15, but the logical O level remains on the information bus 2, as it is supported by the transmitting side. This level of logical O through the elements OR 33 and AND 37 of the encoder 15 prohibits the passage of pulses through the element AND 17 to the input of the counter 18. At the remaining inputs of the element SH 33 - O, since the counter 18 is in the state O. The device is in the waiting state. If the transmitting side enters the ready state, then on the information bus 2 a logical level 1 is set and counter 18 is enabled. Consider the operation of the transmitting side. Assume that the receiving side is ready to receive information. On the leading edge of the pulse. Information arriving at the control input P is made by resetting the counter 6 and writing to the shift register 4 of the information word (data) from inputs 13. At the output of the element HE 8 and, accordingly, bus 2 sets the logic level 1 and the receiving side starts forming a control sequence. On the front of the control sequence pulse pulse, the synchronizer trigger 23 is set to state 1, if the output of shift register 4 is a logical 1 (transmission of one bit). On the leading edge of the pulse generator 25, the trigger 24 is set to the state and at the output of the element 26 and 26 and, accordingly, on the bus 2, a logical pulse O of a duration equal to the pulse duration of the generator 25 pulses is formed. At the same time, the trigger 23 sets the state to O. At the time of the pulse passing from the AND 26 element on the bus 2, the output of the OR 7 element is maintained at a logic level 1 prohibiting the triggering of the trigger 23, the counter 6 and the shift register 4. Thus, a bit of information is transmitted. On the trailing edge of the control pulse, counter 6 is triggered and the register 4 is shifted by 1 bit. After the last control pulse arrives, counter 6 changes to the state corresponding to the size of the information word and the output level HE 8 is set to low. Accordingly, a low level is established on the information bus 2 and on the control input 12 of the transmitting side, which is ready to transmit the next information word. If the receiving side is not ready (keeps bus 2 at a low level), then the Information pulse is written to register 4 and the counter 6 is reset to state O, and a high level is set at control input 12. But since the receiving side does not generate control pulses at the control input 12, the device is in the waiting state. With an information word size of 1 byte (8 bits), 8 buses for data transmission and 1 bus for control must be used in the base object. The proposed device uses only one bus for both data transmission (information word) and control. At the same time, there is no significant deterioration in speed, since the generator frequency can be chosen sufficiently large (1 MHz and Bbmie).

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Claims (1)

DEVICE FOR TRANSMISSION AND RECEIVING OF INFORMATION, containing on the transmitting side an element NOT whose output is connected to the first input of the AND element, an amplifier whose output is connected to the information bus, an OR element, on the receiving side an amplifier whose output is connected to the information bus, AND element, characterized in that, in order to increase the information content of the device, a shift register, a synchronizer, a counter, the first inputs of the shift register are information inputs of the device, the output of the register with the wig is connected to the first input of the synchronizer, the first output of which is connected to the second input of the AND element, the output of which is connected to the input of the amplifier, the output of the amplifier is connected to the first input of the OR element, the second input of which is connected to the second output of the synchronizer, the output of the OR element is connected to the second input of the synchronizer , the second input of the shift register and the first input of the counter, the output of the counter is connected to the input of the element NOT, the output of which is the first control output of the device, the combined third input of the shift register and the second counter input is the first control input of the device, an encoder, a counter, a shift register, a pulse generator, the output of which is connected to the first input of the And element, the output of which is connected to the first input of the counter, the outputs of which are connected to the first inputs of the encoder, are introduced at the receiving side, the first output the encoder is connected to the input of the amplifier and the first input of the shift register, the second output of the encoder is connected to the second input of the And element, the combined second input of the encoder and the second input of the shift register are connected to the information onnoy bus input of the counter is a second control input device, the third output of the encoder and the outputs of the shift register are respectively the second control and information outputs of the device.