SU1193789A1 - Programmable delay line - Google Patents

Abstract

1. A PROGRAMMABLE DELAY LINE containing a random access memory, the KOTopjOro information input is the device input, and the address inputs and the control input, which are connected respectively to the address control outputs and to the first control output of the control unit, characterized in that functionality due to the possibility of the simultaneous formation of N output signals shifted by predetermined time intervals, buffer registers are entered into it, a switch, whose information input is under for prison to the output of random access memory, a second control yupschyk, a control output of the control unit, and outputs coupled to respective inputs of buffer registers whose outputs are the outputs of the device, and the control inputs are connected to the first control output of the control unit. 2. A line in accordance with claim 1, wherein the control unit comprises a clock pulse generator connected by an output to a counter of the tap number and to the same inputs of the first and second elements AND, the outputs of which are respectively the first and the second control outputs of the control unit, and the others (L, their combined inputs are connected respectively to the direct and inverse outputs of the zero state decoder, the inputs of which are connected to the outputs of the retraction number counter and to the memory inputs of delay values, output which are connected to vhodami.vychitatel, with other inputs of which the current through the meter 00 connected to the write address counter 00 overflow outlet tap numbers, and register inputs torogo obliquely connected to the outputs of the subtractor, and the outputs are addressable outputs control unit.

Description

The invention relates to a pulse technique, namely to devices for temporarily delaying digital signals, for example, in the apparatus for generating and scanning the directivity characteristics of MHoroaneMeHTHbik antenna arrays.

The aim of the invention is to extend the functionality due to the possibility of the simultaneous generation of N output signals shifted by predetermined time intervals.

In the drawing: shows a block diagram of the programmable delay line.

The programmable delay line contains random access memory 1, for example, organizing M-cells with 1-bit binary words each, switch 2, providing switching of 1-bit binary words from one to N directions and performed, for example, on J shift registers with N outputs, N buffer-bit parallel registers (g and. unit 4 controls.

The address inputs and the control input of the random access memory 1 are connected respectively to the address AND to the first control output of the control unit A, to the second control output of which the control input of the switch 2 is connected, the information input of which is connected to the output of the random access memory 1, and outputs - to inputs of buffer registers 3ts,

The control unit 4 contains a clock pulse generator 5, connected by an output to the counter 6 of the outlet number, the output of which is connected to the input of the counter 7 of the current write address; the output of the counter 6 of the outlet number is connected to the input of the storage device 8, connected by the output to the first input of the subtractor 9, the output of which connected through register 10 to the address outputs of control unit 4; The output of the counter 6 of the outlet number is also connected via the zero state decoder 1.1 to the first inputs of the first second 13 elements And, respectively, the outputs to Secondly, the first and second control outputs of the control unit 4 are respectively, and the second combined inputs of the elements 12 and 13 are connected to the output of the generator 5 clock pulses. The output of the counter 7 of the current address of the record is connected to the second input of the subtractor 9,

The programmable delay line works as follows,

The pulses of the generator 5 clock pulses, arriving at the counting input of the counter 6 of the tap number, transfer it successively to the position from O to. N, Information from the outputs of the counter 6 of the outlet number in the form of a parallel code is fed to the address inputs of the storage device 8 delay values, the address of the memory cell in which the binary number is stored (delay coefficient) is proportional to the delay time on the iM retraction line, Counter overflow pulses 6 numbers of the tap are sent to the counting input of the counter 7 of the current address of the record, transferring it sequentially to the position from O to M, Information from the outputs of the storage device 8 delay values and the counter 7 of the current addr The recordings are fed to the inputs of the subtractor 9, where by subtracting the delay coefficient from the parallel status code of the counter 7 of the current write address, the cell address of the random access memory 1 is obtained, from which information is read to form the output signal for the i-ro tap. This information affects the delayed in relation to the current time, which, determined by the state of the counter 7 of the current write address, to the number of ticks equal to the tenth equivalent of the delay coefficient. The calculated cell address is fed to the address-sine inputs of the random access memory 1, through register 10 , Reading and writing to the random access memory 1 takes place depending on the state of the 6-number tap. When information arrives at the inputs of the zero-state decoder 11, the outputs of counter 6 of the tap number for its status from .1 to N from the direct code of the zero-state decoder 11 receive a signal that prohibits the passage of clock pulses from the clock generator 5 through pulses And 12, as a result of the last

The signal setting the random access memory 1 to read mode.

In the zero state of the counter 6 of the outlet number from the direct output of the decoder 11 of the zero state, a signal arrives at the element 12 allowing the passage of a single clock pulse through it, for which time the random access memory 1 is set to the recording mode and the input signal is written into random access memory 1. In the states of the counter of nonmeasure 6 from 1 to N, the subtractor 9 sequentially generates N read addresses from the random access memory 1 signal recorded in it. Random access memory in accordance with the calculated addresses generates N signals corresponding to the signals on the taps on the current clock of the delay line. The binary word from the output of the operational storage device 1 is fed to the switch 2, which transforms the serial information at its input into the N-bit at the outputs by setting the switch to position 1 to N of the control clock from the output of the 5 clock generator, passing through the Earth gate And 13 in the presence of a resolution signal coming from the inverse output of the G1 decoder of the zero state for the states of the counter 6 of the tap number from 1 to N.

For the zero state of the counter 6 of the outlet number, the decoder 1 1 of the zero state prohibits the passage of clock pulses to the control input of the switch 2 and its switching does not occur. The parallel N-code from the outputs of the switch 2 is fed to the information inputs of the 3-L buffer registers, which are written when a single pulse of the clock frequency from the output of the I 12 element arrives at their control inputs when the count number of the discharge number 6 is zero while recording in the random access memory 1 of the next value of the input signal. When the counter is 6, the numbers from 1 to N, the buffer registers 3 J -3c, are in the

93789

storage of information. The outputs of the buffer registers 3, -3fi are the taps of the delay line from which the output signals are taken.

With the operation of determining the read address and the read itself from the random access memory 1 to the buffer registers 3 - 3 jjj, is repeated N times in one operation cycle or 10 scientific research institutes. The duration of one clock cycle is equal to N periods of the generator pulses of 5 clock pulses. The N-th clock pulse arriving at the 6th tap counter transfers it from the N-ro state

15 to zero, with this, an overflow pulse is generated, which arrives at the counting input of the counter 7 of the current write address and takes it to the next position (t + 1). At the new position of the counter 6, the number of taps in the subtractor 9, the zero code read from the memory 8 of the required delay value is subtracted from the code from counter 7. The result of the subtraction is the write address of the input signal for a given beat.

Further, the line operation is repeated cyclically M times, i.e. until the counter 7 of the current write address is filled, after which the M + 1 pulse at the input of the counter 7 of the current write address goes to the zero state and the recording of the input signal again goes from 0 to the memory cell.

The random access memory capacity is selected from the following considerations:

jOKc

M

T - N

M - the number of memory cells}

where max required is max

delay;

T - the period of clock pulses;

N is the number of required taps.

Thus, the range of variation of the delays at the line taps lies in the range from T. N to T.-NM with a discrete step T.-N. The law of changing delays in the specified range is determined by the values of the coefficients stored in the storage device and can be selected with any accuracy T-yy N.

In order to increase the stability of the line in conditions of strong electromagnetic interference, switch 2 can be made in the form of a demultiplexer 1 - N, for control of which

In addition to the synchronization circuit from the clock generator, an additional circuit is introduced connecting the address inputs of the demultiplexer to the parallel outputs of the counter 6 of the tap.

Claims (2)

1. A PROGRAMMABLE DELAY LINE, containing random access memory, the information input of which is the input of the device, and the address inputs and control inputs. ' which are connected 'respectively to the address and to the first control outputs of the control unit, characterized in that, in order to expand the functionality due to the possibility of the simultaneous generation of N output signals shifted by predetermined time intervals, buffer registers, a switch, information the input of which is connected to the output of random access memory, which controls the second, control output of the control unit, and the outputs are connected to the inputs of the corresponding buffer registers c, the outputs of which are the outputs of the device, and the control inputs are connected to the first control output of the control unit. 2. The line along π. 1, wherein the control unit comprises a clock pulse generator connected by an output to the counter of the tap number and to one of the inputs of the first and second AND elements, the outputs of which are the first and second control outputs of the control unit, and their other inputs are combined connected respectively to the direct and inverse outputs of the zero state decoder, the inputs of which are connected to the outputs of the counter of the tap number and to the inputs of the memory of the delay values, the outputs of which are connected to the input mi.vychitatelya, other inputs of which the current through the write address counter connected to the overflow output of counter discharge rooms and the register having inputs connected to the outputs of the subtractor, and the outputs are addressable outputs control unit. SUo .. 1193789> ί