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KR970013153A - Wafer Verification Circuit and Its Verification Method - Google Patents

Wafer Verification Circuit and Its Verification Method Download PDF

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Publication number
KR970013153A
KR970013153A KR1019950025864A KR19950025864A KR970013153A KR 970013153 A KR970013153 A KR 970013153A KR 1019950025864 A KR1019950025864 A KR 1019950025864A KR 19950025864 A KR19950025864 A KR 19950025864A KR 970013153 A KR970013153 A KR 970013153A
Authority
KR
South Korea
Prior art keywords
coprocessor
random
image computer
verification
array
Prior art date
Application number
KR1019950025864A
Other languages
Korean (ko)
Other versions
KR0150106B1 (en
Inventor
홍경호
Original Assignee
김주용
현대전자산업주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김주용, 현대전자산업주식회사 filed Critical 김주용
Priority to KR1019950025864A priority Critical patent/KR0150106B1/en
Publication of KR970013153A publication Critical patent/KR970013153A/en
Application granted granted Critical
Publication of KR0150106B1 publication Critical patent/KR0150106B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Automation & Control Theory (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

본 발명은 웨이퍼 검증회로 및 그 검증방법에 관한 것으로서, 웨이퍼 검증장비에서 사용되는 어레이 모드 및 랜덤 모드를 동시에 실행할 수 있도록 하므로써, 어레이 모드만을 사용할때의 문제점인 페리(Peri) 지역의 측정이 가능하게 되고, 또한 상기 랜덤 모드만을 사용할때의 문제점인 측정할수 있는 스캐닝 에리어가 해결되어 셀의 감도를 향상시킬수 있도록 한 웨이퍼 검증회로 및 그 검증방법에 관한 것이다.The present invention relates to a wafer verification circuit and a method of verifying the same, and to simultaneously execute an array mode and a random mode used in a wafer verification apparatus, thereby enabling measurement of a Peri region, which is a problem when using only the array mode. In addition, the present invention relates to a wafer verification circuit and a method for verifying the same, wherein the measurable scanning area, which is a problem when using only the random mode, is solved to improve cell sensitivity.

Description

웨이퍼 검증회로 및 그 검증방법Wafer Verification Circuit and Its Verification Method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명에 따른 웨이퍼 검증회로도1 is a wafer verification circuit diagram according to the present invention.

Claims (3)

웨이퍼 검증회로에 있어서, 프로그래밍을 시행하도록 하는 어레이 프로그램 셋업모드 및 랜덤프로그램 셋업모드와, 코프로세서 인에이블단자의 출력신호를 각각 입력으로하며, 상기 어레이 프로그램 셋업모드 및 랜덤 프로그램 셋업모드의 프로그래밍에 따라 웨이퍼 표면에 대한 각각의 정보를 저장하는 어레이 이메지 컴퓨터 및 랜덤 이메지 컴퓨터와, 상기 어레이 이메지 컴퓨터 및 랜덤 이메지 컴퓨터의 출력단자간에 접속되는 독출신호부와, 상기 어레이 이메지 컴퓨터 및 랜덤 이메지 컴퓨터의 데이터를 각각 입력으로하며 상기 코프로세서 인에이블단자의 출력신호에 따라 동작되는 코프로세서와, 상기 코프로세서의 출력 데이타를 입력으로하는 검증부로 구성되는 것을 특징으로 하는 웨이퍼 검증회로.In the wafer verification circuit, an array program setup mode and a random program setup mode for executing programming and an output signal of the coprocessor enable terminal are input, respectively, and according to the programming of the array program setup mode and the random program setup mode. An array image computer and a random image computer for storing respective information on the wafer surface, a read signal unit connected between the output terminals of the array image computer and the random image computer, and data of the array image computer and the random image computer, respectively. And a verification unit configured as an input and operating according to an output signal of the coprocessor enable terminal, and a verification unit configured to input output data of the coprocessor. 제1항에 있어서, 상기 독출신호는 교호로 접속되는 한쌍의 인버터로 구성되는 것을 특징으로 하는 웨이퍼 검증회로.The wafer verification circuit according to claim 1, wherein the read signal comprises a pair of inverters connected alternately. 웨이퍼 검증방법에 있어서, 상기 코프로세서 인에이블단자가 인에이블 되어 상기 코프로세스를 직접 콘트롤 되도록 하고, 상기 코프로세서 인에이블단자로부터 인에이블신호가 발생될 때 상기 독출신호부를 디스에이블 시키며, 상기 각각의 모드에서 프로그램된 데이타는 각각의 이메지 컴퓨터에 저장되어 있다가 상기 코프로세서 인에이블단자가 인에이블되는 동시에 상기 코프로세스로 입력되도록 하고, 상기 코프로세서 내에서는 상기 두 데이타를 조합하여 검증부로 출력시켜 상기 검증부에서 하드웨어를 셋팅하여 상기 어레이 모드 및 랜덤모드를 동시에 사용하여 검증할 수 있도록 하는 것을 특징으로 하는 웨이퍼 검증회로.In the wafer verification method, the coprocessor enable terminal is enabled to directly control the coprocess, and when the enable signal is generated from the coprocessor enable terminal, the read signal unit is disabled, respectively The programmed data is stored in each image computer so that the coprocessor enable terminal is enabled and input to the coprocess, and the coprocessor is output to the verification unit by combining the two data. And verifying the array mode and the random mode at the same time by setting hardware in the verification unit.
KR1019950025864A 1995-08-22 1995-08-22 Monitoring circuit and method of wafer KR0150106B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950025864A KR0150106B1 (en) 1995-08-22 1995-08-22 Monitoring circuit and method of wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950025864A KR0150106B1 (en) 1995-08-22 1995-08-22 Monitoring circuit and method of wafer

Publications (2)

Publication Number Publication Date
KR970013153A true KR970013153A (en) 1997-03-29
KR0150106B1 KR0150106B1 (en) 1998-12-01

Family

ID=19424025

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950025864A KR0150106B1 (en) 1995-08-22 1995-08-22 Monitoring circuit and method of wafer

Country Status (1)

Country Link
KR (1) KR0150106B1 (en)

Also Published As

Publication number Publication date
KR0150106B1 (en) 1998-12-01

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