SU748413A1 - Microprogramme-control device - Google Patents

Description

one

The invention relates to computing, in particular to computer control devices.

It is known to have a jro-program control device, containing two control units, address registers, and the elements}.

The disadvantage of the indicated device is complexity.

Closest to the proposed. The device according to its technical nature is a firmware control device containing a trigger, AND elements, a switch, the first and fs second outputs of which are connected to the inputs of the first and second groups of elements, each of which consists of sequentially connected registers and a memory block, 20 connected via the element I to the corresponding input of the device, and the output of the first storage unit is connected to the zero input of the trigger, and the output of the second memory 25 is connected to the single input of the trigger, e inichny output of which is connected to the second input of the first element, and a zero output - to Auto .romu input AND gate AND. . thirty

The disadvantage of this device is complexity, due to the presence in the circuit of two switches operating alternately, as well as the need to expand the inputs of the address registers to ensure the recording of information from either of the two switches.

The purpose of the invention is to simplify the device. .

This is achieved by the fact that a firmware control device containing a switch, the first and second outputs of which are connected respectively to the inputs of the first and second address register, the outputs of which are connected to the first inputs of the first and second memory blocks, respectively, the second inputs of which are connected respectively to the outputs of the first and the second And elements, the first input of the first element And is the first input of the device, the second input is connected to the single output of the trigger, the first input of the second element And is the second input device, and the second input is connected to the zero output of the trigger, the zero input of which is connected to the first output of the first memory block, and the single input to the first output of the second memory block and contains the first and second elements NOT and OR, a group of elements OR, or the first and second inputs of the elements OR groups are connected respectively to the second outputs of the first and second memory blocks, the first output of the first memory block is connected via the first element NOT to the input of the first OR element and to the first input of the second OR element, the second input of which through the union of the second NOT member to the first output of the second memory unit and to a second input of the first OR gate whose output is connected to the first input switch, output vtofioro OR gate connected to the second input of the switch, the output elements or groups connected to the third input of the switch.

The device uses only one switch that operates during each device operation cycle and provides information from the outputs of the memory unit to the desired address register (i.e., the one from which it should be read in the next cycle). .

In the drawing. A block diagram of the firmware control device is presented. . .

The microprogram control device contains registers 1 and 2, elements 3 and 4, blocks 5 and 6 of memory, elements 7 and. 8, the group of elements OR 9, the trigger 10, the elements OR 11 and 12, the switch 13. The symbols 14 and 15 designate the clock pulse inputs, 16 and 17 the first, 18 and 19 the second outputs of the blocks.

The trigger 10 controls the operation of the device. If it is in the single (zero) state, then the element FROM (4) is opened and reading by clock pulses is allowed at input 14 (15) from block 5 (6) of the memory. A troupe of elements OR 9 forms a chain of information transfer (addresses of a microcommand)

from the outputs of memory blocks 5 and 6 to the third input of the switch 13.

The elements HE.7 and B and the elements OR 12 form a chain of control of the operation of the switch 13 through the first and second inputs. If there is a control signal at the first (second) input of the switch 13, the address of the next microcommand from the output 18 (19) of block 1 of this 5 (6) is written through the OR 9 elements and the switch 1h into register 1 (2).

The device works as follows.

In the initial state, the trigger 10 is in the single (zero) STATUS, and the address of the readable microchip is in the register. 1 (2) Since the AND 3 (4) element is open, the clock pulse coming from the input of the device 14 ( 15) through the element FROM (4) allows reading the microcommand from the memory block 5 (6).

Further, the operation of the device can be carried out in two modes. In the first mode, an alternate reading of micro-instructions from the memory blocks occurs. In the second mode, micro-instructions are read in two or more clocks from the same memory card.

In the first mode, from the first output 16. (17) of the memory block 5 (6), a single signal is read each time, which goes to the zero (single) input of the trigger 10 and simultaneously through the OR element 12 (11) to the second (first) input of the switch 13. The trigger 10 is set to zero (one) state in which the open element AND (3) 4. Simultaneously, from the second output 18 (19) of the memory block 5 (6), the address of the next microcommand is read, which through the elements OR 9. enters to the third input of the switch 13 and further by the operation of the switch 13 from its second (first o) is recorded in the output register 2 (1).

On the next clock pulse, the operation of the device is carried out as described above.

In the second mode, the signal at the output 16 (17) of the memory block 5 (6) is missing. Therefore, the trigger 10 does not change its state and the AND 3 (4) element is open. At the same time, a single signal from the NOT 7 (8) element through the OR 11 (12) element is fed to the first (second) input of the switch 13, thereby determining the address of the next microcommand from the 18 (19) output of the 5 (6) memory through the elements OR 9 and switch to .reg 1 (2). If after this it is necessary to re-implement the second mode, then the device functions as described.

The introduction of an additional two elements, HE and OR, and the group of OR elements, as well as the described connections, allows the device to be significantly simplified by using a single switch, which makes it possible to build more economical microprogrammed control devices. .

Claims (2)

Invention Formula A firmware control device containing a switch, the first and second outputs of which are connected respectively to the terminals of the first and second address registers, the outputs of which are connected to the first inputs of the first and second blocks of par.mi, respectively., The second inputs which are connected respectively to the outputs of the first and second elements I, the first input of the first element I is the first input of the device, the second input is connected to the single output of the trigger, the first input, the second, element I is the second input of the device, and the second input is connected to the zero output of the trigger, the zero input of which is connected to the first output of the first unit of the unit, and the single input to the first output of the second unit of memory, characterized in that it contains the first and second elements of the device NOT and OR, groups y OR elements, wherein the first and second inputs of OR element group are connected respectively to the second outputs of the first and second memory block, the first output of the first. the memory unit is connected through the first element NOT to the first input of the first element OR and to the first input of the second element, OR, the second input of which is connected through the second element NOT to the first output of the second memory block and to the second input of the first OR element, the output of which connected to the first input of the switch, the output of the second element OR is connected to the second input of the switch, output 0 elements OR groups are connected to the third input of the switch.  Sources of information taken into account in the examination 1, USSR Author's Certificate No. 451080, class, G 06 F 9/12, 1974. 2. Copyright certificate of the USSR in application number 2479592/24, 04/26/77 (prototype).