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KR950028022A - 반도체 소자의 패드 보호 구조 및 보호막 형성 방법 - Google Patents

반도체 소자의 패드 보호 구조 및 보호막 형성 방법 Download PDF

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Publication number
KR950028022A
KR950028022A KR1019940004292A KR19940004292A KR950028022A KR 950028022 A KR950028022 A KR 950028022A KR 1019940004292 A KR1019940004292 A KR 1019940004292A KR 19940004292 A KR19940004292 A KR 19940004292A KR 950028022 A KR950028022 A KR 950028022A
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KR
South Korea
Prior art keywords
bond
protective film
pad
semiconductor device
silicon nitride
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Application number
KR1019940004292A
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English (en)
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KR0146066B1 (ko
Inventor
이동현
Original Assignee
문정환
금성일렉트론 주식회사
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Application filed by 문정환, 금성일렉트론 주식회사 filed Critical 문정환
Priority to KR1019940004292A priority Critical patent/KR0146066B1/ko
Publication of KR950028022A publication Critical patent/KR950028022A/ko
Application granted granted Critical
Publication of KR0146066B1 publication Critical patent/KR0146066B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자의 패드 보호 구조 및 보호막 형성 방법에 관한 것으로, 특히 본드 패드뿐만 아니라 그 패드에 접속되는 본드 와이어를 오염 물질로부터 보호하고, 재질변경을 통한 보호막의 특성 향상에 목적이 있는 본 발명은 실리콘 기판(1)에 형성된 본드 패드(2)의 상면과 그 본드 패드(2)에 접속되는 본드 와이어(3)의 표면을 포함하는 전면에 걸쳐 외부의 오염 물질로부터 본드패드(2) 및 본드 와이어(3)를 보호하기 위한 보호막(10)을 형성하여 구성한 것을 특징으로 하고 있으며, 상기 보호막(10)은 실리콘 질화물을 플라즈마 화학 기상 증착법을 이용하여 0.5내지 1㎛두께로 증착하는 것으로 형성된다.

Description

반도체 소자의 패드 보호 구조 및 보호막 형성 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명에 의한 반도체 소자의 패드 보호 구조를 보인 확대 단면도.

Claims (5)

  1. 실리콘 기판에 형성된 본드 패드의 상면과 그 본드 패드에 접속되는 본드 와이어의 표면을 포함하는 전면에 걸쳐 외부의 오염 물질로부터 본드 패드 및 본드 와이어를 보호하기 위한 보호막을 형성하여 구성한 것을 특징으로 하는 반도체 소자의 패드 보호 구조.
  2. 제1항에 있어서, 상기 보호막(10)의 재질은 실리콘 질화물인 것을 반도체 소자의 패드 보호 구조.
  3. 제1항 또는 제2항에 있어서, 상기 보호막(10)은 0.5 내지 1㎛두께로 형성됨을 반도체 소자의 패드 보호 구조.
  4. 실리콘 기판의 본드 패드 위에 P-신 필름을 증착하는 단계와, 상기 P-신 필름을 에치하여 본드 패드의 본드 와이어 접속 부분을 오픈하는 단계와, 상기 본드 패드에 본드 와이어를 접속하는 단계와, 상기 본드 패드의 상면과 본드 와이어의 전표면에 걸쳐 실리콘 질화물을 증착하는 단계로 진행함을 특징으로 하는 반도체 소자의 패드 보호막 형성방법.
  5. 제4항에 있어서, 상기 실리콘 질화물을 증착하는 단계는 플라즈마 화학 기상 증착법에 의하는 것을 특징으로 하는 반도체 소자의 패드 보호막 형성 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940004292A 1994-03-05 1994-03-05 반도체 소자의 패드 보호막 형성방법 KR0146066B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940004292A KR0146066B1 (ko) 1994-03-05 1994-03-05 반도체 소자의 패드 보호막 형성방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940004292A KR0146066B1 (ko) 1994-03-05 1994-03-05 반도체 소자의 패드 보호막 형성방법

Publications (2)

Publication Number Publication Date
KR950028022A true KR950028022A (ko) 1995-10-18
KR0146066B1 KR0146066B1 (ko) 1998-11-02

Family

ID=19378417

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940004292A KR0146066B1 (ko) 1994-03-05 1994-03-05 반도체 소자의 패드 보호막 형성방법

Country Status (1)

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KR (1) KR0146066B1 (ko)

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Publication number Publication date
KR0146066B1 (ko) 1998-11-02

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