KR20240162202A - Semiconductor device - Google Patents

Abstract

A semiconductor device may include first and second gate structures embedded in an upper portion of a substrate, each of which extends in a first direction and is alternately and repeatedly arranged along a second direction intersecting the first direction; bit line structures each of which extends in the second direction on the first and second gate structures and is spaced apart from each other in the first direction; and capacitors formed on the bit line structures. A width of a first end of each of the first gate structures in the first direction in the second direction may be larger than a width of the remaining portions of each of the first gate structures in the second direction, and a width of a first end of each of the second gate structures in the first direction may be larger than a width of the remaining portions of each of the second gate structures in the second direction. The first ends of the first gate structures may be aligned with each other in the second direction, and the first ends of the second gate structures may be aligned with each other in the second direction. The first ends of the first gate structures and the second ends of the second gate structures can be arranged in a zigzag pattern along the second direction.

Description

SEMICONDUCTOR DEVICE

The present invention relates to a semiconductor device. More specifically, the present invention relates to a DRAM memory device.

Each gate structure of a DRAM device extends in one direction and is arranged to be spaced apart from each other in a direction perpendicular thereto. As the DRAM device becomes more highly integrated, the gap between the gate structures decreases, and accordingly, the difficulty of the process of forming the gate structures increases.

An object of the present invention is to provide a semiconductor device having improved electrical characteristics.

According to exemplary embodiments of the present invention for achieving the above-described task, a semiconductor device may include: first and second gate structures embedded in an upper portion of a substrate, each of which extends in a first direction and is alternately and repeatedly arranged along a second direction intersecting the first direction; bit line structures each of which extends in the second direction on the first and second gate structures and is spaced apart from each other in the first direction; and capacitors formed on the bit line structures. A width of a first end of each of the first gate structures in the first direction in the second direction may be larger than a width of the remaining portions of each of the first gate structures in the second direction, and a width of a first end of each of the second gate structures in the first direction may be larger than a width of the remaining portions of each of the second gate structures in the second direction. The first ends of the first gate structures may be aligned with each other in the second direction, and the first ends of the second gate structures may be aligned with each other in the second direction. The first ends of the first gate structures and the second ends of the second gate structures can be arranged in a zigzag pattern along the second direction.

In a semiconductor device according to exemplary embodiments, a terminal portion of a gate structure formed to be buried in an upper portion of a cell region of a substrate and a peripheral circuit region adjacent thereto may have a width greater than the width of the remaining portions, and thus electrical connection with a contact plug formed to contact the terminal portion may be good.

FIGS. 1 to 44 are plan views and cross-sectional views for explaining a method of manufacturing a semiconductor device according to exemplary embodiments.

Hereinafter, a semiconductor device and a manufacturing method thereof according to preferred embodiments of the present invention will be described in detail with reference to the attached drawings. When materials, layers (films), regions, pads, electrodes, patterns, structures or processes are referred to as “first,” “second” and/or “third” in this specification, it is not intended to limit these elements but merely to distinguish each material, layer (film), region, electrode, pad, pattern, structure and process. Accordingly, “first,” “second” and/or “third” may be used selectively or interchangeably with respect to each material, layer (film), region, electrode, pad, pattern, structure and process.

[Example]

FIGS. 1 to 44 are plan views and cross-sectional views for explaining a method of manufacturing a semiconductor device according to exemplary embodiments. Specifically, FIGS. 1, 4, 6, 8, 11, 14, 20, 25, 31, 35 and 41 are plan views, FIGS. 2, 5, 7, 9-10, 12, 15, 18, 21, 24, 26, 29, 32, 36, 37, 39 and 42 are cross-sectional views of corresponding plan views taken along line A-A', FIGS. 16, 19, 22, 27, 30, 33-34, 38, 40 and 43 are cross-sectional views of corresponding plan views taken along line B-B', and FIGS. 3, 13, 17, 23, 28 and 44 are cross-sectional views of corresponding plan views taken along line C-C'.

In the detailed description of the invention below, two directions that are parallel to the upper surface of the substrate (100) and are orthogonal to each other are defined as first and second directions (D1, D2), respectively, and a direction that is parallel to the upper surface of the substrate (100) and forms an acute angle with each of the first and second directions (D1, D2) is defined as a third direction (D3). Meanwhile, a direction that is perpendicular to the upper surface of the substrate (100) is referred to as a vertical direction.

Referring to FIGS. 1 to 3, first and second active patterns (101, 105) can be formed on a substrate (100) including first and second regions (I, II).

The substrate (100) may include silicon, germanium, silicon-germanium, or a III-V group compound such as GaP, GaAs, GaSb, etc. According to some embodiments, the substrate (100) may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

The first region (I) of the substrate (100) may be a cell region where memory cells are formed, and the second region (II) of the substrate (100) may be a peripheral circuit region where peripheral circuit patterns that drive the memory cells are formed while surrounding the first region (I). In the drawing, only a part of the first region (I) and a part of the second region (II) that is adjacent to the first region (I) in the first and second directions (D1, D1) are illustrated.

The first and second active patterns (101, 105) can be formed by removing an upper portion of the substrate (100) to form a recess structure. The first active pattern (101) can be formed in a plurality of pieces, each of which can extend in a third direction (D3) on a first region (I) of the substrate (100) and be spaced apart from each other along the first and second directions (D1, D2). In addition, the second active pattern (105) can be formed in a plurality of pieces, each of which can be spaced apart from each other along the first and second directions (D1, D2) on a second region (II) of the substrate (100).

The above recess structure may include first to third recesses (102, 104, 106). At this time, the first recess (102) may be formed between portions of the first active patterns (101) that are spaced apart from each other by a relatively small distance along the first direction (D1) on the first region (I) of the substrate (100), the second recess (104) may be formed between portions of the first active patterns (101) that are spaced apart from each other by a relatively large distance along the first direction (D1) on the first region (I) of the substrate (100), and the third recess (106) may be formed on the second region (II) of the substrate (100) or between the first and second regions (I, II) of the substrate (100).

In exemplary embodiments, the third recess (106) may have a greater width and/or greater depth than the second recess (104), and the second recess (104) may have a greater width and/or greater depth than the first recess (102).

Thereafter, a preliminary element isolation structure (111) covering the side walls and upper surfaces of the first and second active patterns (101, 105) can be formed.

In one embodiment, the preliminary device isolation structure (111) can be formed by sequentially stacking a first device isolation film (113), a second device isolation film, and a third device isolation film on a substrate (100) on which first and second active patterns (101, 105) are formed, performing a planarization process on an upper portion of the third device isolation film until an upper surface of the second device isolation film is exposed, and then performing an etching process on an upper portion of the second device isolation film. The planarization process can include, for example, a chemical mechanical polishing (CMP) process and/or an etch-back process, and the etching process can include, for example, a wet etching process.

In exemplary embodiments, the preliminary element isolation structure (111) may include a first element isolation film (113), a second element isolation pattern (114), and a third element isolation pattern (116) sequentially stacked from an inner wall of the third recess (106). However, the first element isolation film (113) and the second element isolation pattern (114) may be formed in the second recess (104) having a smaller width than the third recess (106), and only the first element isolation film (113) may be formed in the first recess (102) having a smaller width than the second recess (104).

At this time, the first element isolation film (113) can cover the upper surfaces of the first and second active patterns (101, 105), the second element isolation pattern (114) can be formed in the second recess (104), and the third element isolation pattern (116) can be formed in the third recess (106).

Each of the first element isolation film (113) and the third element isolation pattern (116) may include an oxide such as silicon oxide, for example, and the second element isolation pattern (114) may include an insulating nitride such as silicon nitride, for example.

Referring to FIGS. 4 and 5, after forming a pad film (10), a first mask film (20), a second mask film (30), and a third mask (40) on a preliminary element separation structure (111), an etching process using the third mask (40) as an etching mask is performed to remove the second mask film (30), the first mask film (20), the pad film (10), and an upper portion of the preliminary element separation structure (111), thereby forming fourth and fifth recesses (52, 54).

In one embodiment, the etching process can be performed through a double patterning process.

Each of the fourth and fifth recesses (52, 54) may be formed on an upper portion of a third element isolation pattern (116) formed on a portion of a second region (II) of the substrate (100) adjacent to a first region (I) of the substrate (100) in the first direction (D1). In exemplary embodiments, a plurality of fourth recesses (52) may be formed on a portion of a second region (II) of the substrate (100) formed on one side of the first region (I) of the substrate (100) in the first direction (D1) so as to be spaced apart from each other along the second direction (D2), and a plurality of fifth recesses (54) may be formed on a portion of a second region (II) of the substrate (100) formed on the other side of the first region (I) of the substrate (100) in the first direction (D1) so as to be spaced apart from each other along the second direction (D2).

In exemplary embodiments, the fourth and fifth recesses (52, 54) may not overlap each other in the first direction (D1), and thus the fourth and fifth recesses (52, 54) may be arranged alternately in a zigzag pattern along the second direction (D2) on portions of the second region (II) of the substrate (100) formed on both sides of the first region (I) of the substrate (100) in the first direction (D1).

The fourth recess (52) may have a first width (W1) in the second direction (D2), and the fifth recess (54) may have a second width (W2) in the second direction (D2). In one embodiment, the first and second widths (W1, W2) may have the same value, but the concept of the present invention is not limited thereto.

The pad film (10) may include, for example, an oxide such as silicon oxide, the first mask film (20) may include, for example, a spin-on-hardmask (SOH) film, the second mask film (30) may include, for example, plasma-enhanced silicon oxynitride (PE-SiON), and the third mask (40) may include, for example, a photoresist pattern.

Referring to FIGS. 6 and 7, the first mask film (20), the second mask film (30), and the third mask (40) may be removed, for example, through an etching process, an ashing process, and/or a stripping process, to expose the upper surface of the pad film (10), and then first and second sacrificial patterns (62, 64) may be formed to fill the fourth and fifth recesses (52, 54), respectively.

In exemplary embodiments, the first and second sacrificial patterns (62, 64) may be formed by forming a first sacrificial film filling the fourth and fifth recesses (52, 54) on the pad film (10) and the spare element isolation structure (111), and then removing an upper portion of the first sacrificial film, for example, through an etch back process, until the upper surface of the pad film (10) is exposed.

Depending on the arrangement of the fourth and fifth recesses (52, 54), the first and second sacrificial patterns (62, 64) may be arranged alternately in a zigzag pattern along the second direction (D2) on portions of the second region (II) of the substrate (100) formed on both sides of the first region (I) of the substrate (100) in the first direction (D1). In addition, the first and second sacrificial patterns (62, 64) may have first and second widths (W1, W2) in the second direction (D2), respectively.

Referring to FIGS. 8 and 9, after forming fourth to eighth mask films (70, 80, 90, 25, 35) and a ninth mask (45) on the pad film (10) and the first and second sacrificial patterns (62, 64), an etching process using the ninth mask (45) as an etching mask is performed to remove the fourth to eighth mask films (70, 80, 90, 25, 35), the pad film (10), the first and second sacrificial patterns (62, 64), the upper portion of the preliminary element isolation structure (111), and the upper portion of the first active pattern (101), thereby forming sixth and seventh recesses (98, 99).

In one embodiment, the etching process may be performed through a double patterning process. In another embodiment, the etching process may be performed through a quadruple patterning process.

Each of the sixth and seventh recesses (98, 99) may extend in the first direction (D1) on portions of the first region (I) of the substrate (100) and the second region (II) of the substrate (100) formed on both sides thereof in the first direction (D1). In exemplary embodiments, one end of the sixth recess (98) may penetrate a portion of the first sacrificial pattern (62), and one end of the seventh recess (99) may penetrate a portion of the second sacrificial pattern (64).

The sixth and seventh recesses (98, 99) may have third and fourth widths (W3, W4) in the second direction (D2), respectively. In one embodiment, the third and fourth widths (W3, W4) may have the same value, but the concept of the present invention is not necessarily limited thereto. In exemplary embodiments, the first width (W1) of the first sacrificial pattern (62) may be larger than the third width (W3) of the sixth recess (98), and the second width (W2) of the second sacrificial pattern (64) may be larger than the fourth width (W4) of the seventh recess (99).

The fourth mask film (70), the sixth mask film (90), and the eighth mask film (35) may include, for example, plasma-enhanced silicon nitride (PE-SiON), the fifth mask film (80) may include, for example, an amorphous carbon layer (ACL), the seventh mask film (25) may include, for example, a spin-on-hard mask (SOH), and the ninth mask (45) may include, for example, a photoresist pattern.

Referring to FIG. 10, the fourth to eighth mask films (70, 80, 90, 25, 35), the ninth mask (45), and the first and second sacrificial patterns (62, 64) may be removed, for example, through an etching process, an ashing process, and/or a stripping process, to expose the upper surface of the pad film (10).

As the first and second sacrificial patterns (62, 64) are removed, the fourth and fifth recesses (52, 54) can be formed again, which can be connected to the sixth and seventh recesses (98, 99), respectively. At this time, the first width (W1) of the fourth recess (52) can be larger than the third width (W3) of the sixth recess (98), and the second width (W2) of the fifth recess (54) can be larger than the fourth width (W4) of the seventh recess (99).

Thereafter, a first gate insulating film (125) can be formed on the upper surface of the exposed pad film (10), the upper surface of the preliminary element isolation structure (111) exposed by the fourth to seventh recesses (52, 54, 98, 99), the upper surface of the first active pattern (101), and the sidewalls of the fourth to seventh recesses (52, 54, 98, 99).

The first gate insulating film (125) may include an oxide such as silicon oxide, for example.

Thereafter, a first conductive film is formed on the first gate insulating film (125), and an upper portion of the first conductive film can be removed, for example, through an etch back process, so that a first conductive pattern (140) can be formed at the lower portion of each of the fourth to seventh recesses (52, 54, 98, 99).

The first challenge pattern (140) may include, for example, a metal such as tungsten, a metal nitride such as titanium nitride, tantalum nitride, a metal silicide, etc.

Referring to FIGS. 11 to 13, a second conductive film may be formed on a first conductive pattern (140) and a first gate insulating film (125), and an upper portion of the second conductive film may be removed, for example, through an etch-back process, to form a second conductive pattern (150) in the central portion of each of the fourth to seventh recesses (52, 54, 98, 99).

The second challenge pattern (150) may include, for example, polysilicon doped with impurities.

In one embodiment, a portion of a second conductive pattern (150) formed on a second region (II) of a substrate (100), that is, a portion of a second conductive pattern (150) formed on the fourth and fifth recesses (52, 54) and the sixth and seventh recesses (98, 99) adjacent thereto, can be removed through an etching process, whereby an upper surface of an end portion of the first conductive pattern (140) in the first direction (D1) can be exposed.

Thereafter, a first gate mask film is formed on the first and second challenge patterns (140, 150) and the first gate insulating film (125), and an upper portion of the first gate mask film is removed, for example, through an etch back process, to form a first gate mask (160) on the upper portion of each of the fourth to seventh recesses (52, 54, 98, 99).

The first gate mask (160) may include an insulating nitride, such as silicon nitride, for example.

Thereafter, the first gate insulating film (125) portion formed on the pad film (10), the pad film (10), and the first element isolation film (113) portion formed on the upper surface of the first and second active patterns (101, 105) can be removed, and accordingly, the first gate insulating film (125) can be converted into the first gate insulating pattern (120), and the first element isolation film (113) can be converted into the first element isolation pattern (112). In one embodiment, the pad film (10), and the first gate insulating film (125) and first element isolation film (113) portions can be removed through a planarization process, such as a chemical mechanical polishing (CMP) process and/or an etch back process.

The first gate insulating pattern (120), the first conductive pattern (140), and the first gate mask (160) sequentially stacked within the fourth and sixth recesses (52, 98) may together form a first gate structure (172), and the first gate insulating pattern (120), the first conductive pattern (140), and the first gate mask (160) sequentially stacked within the fifth and seventh recesses (54, 99) may together form a second gate structure (174). In addition, the first to third element isolation patterns (112, 114, 116) may together form an element isolation structure (110).

In exemplary embodiments, each of the first and second gate structures (172, 174) may extend along the first direction (D1) within portions of the first region (I) of the substrate (100) and the second region (II) of the substrate (100) formed on both sides thereof in the first direction (D1), and may be alternately and repeatedly arranged along the second direction (D2).

In exemplary embodiments, a first width (W1) of a first end (173) in the first direction (D1) of each of the first gate structures (172) in the second direction (D2) may be greater than a third width (W3) of a second end (173) in the first direction (D1) and the remaining portions in the second direction (D2), and a second width (W2) of a first end (175) in the first direction (D1) of each of the second gate structures (174) in the second direction (D2) may be greater than a fourth width (W4) of a second end (173) in the first direction (D1) and the remaining portions in the second direction (D2).

In exemplary embodiments, the first ends (173) of the first gate structures (172) and the second ends (174) of the second gate structures (174) may be arranged in the second direction (D2) on a portion of the second region (II) of the substrate (100) formed on one side of the first region (I) of the substrate (100) in the first direction (D1), and the second ends (172) of the first gate structures (172) and the first ends (175) of the second gate structures (174) may be arranged in the second direction (D2) on a portion of the second region (II) of the substrate (100) formed on the other side of the first region (I) of the substrate (100) in the first direction (D1).

At this time, the first ends (173) of the first gate structures (172) may be aligned with each other in the second direction (D2), and further, the first ends (175) of the second gate structures (174) may be aligned with each other in the second direction (D2). In one embodiment, the second ends of the second gate structures (174) may partially overlap with the first ends (173) of the first gate structures (172) in the second direction (D2), and the second ends of the first gate structures (172) may partially overlap with the first ends (175) of the second gate structures (174) in the second direction (D2).

In exemplary embodiments, first ends (173) of the first gate structures (172) and first ends (175) of the second gate structures (174) having relatively large widths may be arranged in a zigzag pattern along the second direction (D2) on both sides of the substrate (100) in the first direction (D1).

In exemplary embodiments, the bottom surfaces of the first ends (173, 175) of each of the first and second gate structures (172, 174) may be formed at substantially the same height as the bottom surfaces of the remaining portions.

In exemplary embodiments, the first ends (173, 175) of each of the first and second gate structures (172, 174) may include a gate insulating pattern (120), a first conductive pattern (140), and a first gate mask (160) sequentially stacked along the vertical direction, and may not include a second conductive pattern (150).

Referring to FIGS. 14 to 17, an insulating film structure (210) including first to third insulating films (180, 190, 200) sequentially laminated along the vertical direction on first and second regions (I, II) of a substrate (100) can be formed, and a portion of the insulating film structure (210) formed on the second region (II) of the substrate (100) except for a portion of the second region (II) adjacent to the first region (I) of the substrate (100) can be removed.

Thereafter, a second gate insulating film (220) can be formed on the second active pattern (105) formed on the second region (II) of the substrate (100), for example, by performing a thermal oxidation process.

Thereafter, the insulating film structure (210) is patterned, and by using it as an etching mask, the first active pattern (101), the device isolation structure (110), and the first gate mask (160) included in each of the first and second gate structures (172, 174) are partially etched to form the first opening (230). In exemplary embodiments, the insulating film structure (210) remaining after the etching process may have a circular or elliptical shape when viewed from above, and may be formed in multiple pieces so as to be spaced apart from each other along the first and second directions (D1, D2) on the first region (I) of the substrate (100) and the second region (II) adjacent thereto. At this time, each insulating film structure (210) can overlap the ends of the first active patterns (101) facing each other in the third direction (D3) and in the vertical direction perpendicular to the upper surface of the substrate (100).

Referring to FIGS. 18 and 19, a third conductive film (240), a first barrier film (250), a fourth conductive film (260), and a tenth mask film (270) may be sequentially laminated on an insulating film structure (210) formed on a first region (I) of a substrate (100), a first active pattern (101) exposed by a first opening (230), a device isolation structure (110), and an upper surface of the first and second gate structures (172, 174), and a second gate insulating film (220) and the device isolation structure (110) formed on a second region (II) of the substrate (100), and these may together form a conductive structure film. At this time, the third conductive film (240) may fill the first opening (230).

The third conductive film (240) may include, for example, polysilicon doped with impurities, the first barrier film (250) may include, for example, a metal silicon nitride such as titanium silicon nitride (TiSiN), the fourth conductive film (260) may include, for example, a metal such as tungsten, and the tenth mask film (270) may include, for example, a nitride such as silicon nitride.

Referring to FIGS. 20 to 23, the challenge structure film can be patterned to form a third gate structure (330) on the second region (II) of the substrate (100).

The third gate structure (330) may include a second gate insulating pattern (280), a third conductive pattern (290), a first barrier pattern (300), a fourth conductive pattern (310), and a second gate mask (320) that are sequentially stacked along a vertical direction perpendicular to the upper surface of the substrate (100), and the third conductive pattern (290), the first barrier pattern (300), and the fourth conductive pattern (310) that are sequentially stacked may together form a second gate electrode.

The third gate structure (330) may be formed on the second region (II) of the substrate (100) to at least partially overlap with the second active pattern (105) along the vertical direction.

In addition, the conductive structure film portion formed on the edge portion of the first region (I) of the substrate (100) adjacent to the second region (II) of the substrate (100) can also be removed together, and accordingly, the upper surfaces of the insulating film structure (210), the first active pattern (101), the device isolation structure (110), and the first and second gate structures (172, 174) exposed by the first opening (230) can also be partially exposed.

Meanwhile, a first spacer structure may be formed on a sidewall of the third gate structure (330), and a second spacer structure may be formed on a sidewall of the conductive structure film remaining on the first region (I) of the substrate (100). At this time, the first spacer structure may include first and third gate spacers (340, 350) sequentially stacked along a horizontal direction parallel to an upper surface of the substrate (100) from a sidewall of the third gate structure (330), and the second spacer structure may include second and fourth gate spacers (345, 355) sequentially stacked along the horizontal direction from a sidewall of the conductive structure film.

The first and second spacers (340, 345) can be formed by forming a first spacer film on a substrate (100) on which the conductive structure film and the third gate structure (330) are formed, and then anisotropically etching the same, and the third and fourth spacers (350, 355) can be formed by forming a second spacer film on a substrate (100) on which the conductive structure film, the third gate structure (330), and the first and second spacers (340, 345) are formed, and then anisotropically etching the same.

The first and second spacers (340, 345) may include a nitride, such as silicon nitride, for example, and the third and fourth spacers (350, 355) may include an oxide, such as silicon oxide, for example.

However, the configuration of each of the first and second spacer structures is not limited to the above, and may include only a single spacer, or may have a configuration in which three or more spacers are stacked.

Thereafter, a first etch-stop film (360) may be formed on the substrate (100) on which the above-described challenge structure film, the third gate structure (330), the first and second spacer structures, and the device isolation structure (110) are formed. The first etch-stop film (360) may include a nitride such as silicon nitride, for example.

Referring to FIG. 24, a first interlayer insulating film (370) is formed on a first etch-stop film (360) to a sufficient height, and the upper portion thereof is flattened until the upper surface of the third gate structure (330) and the upper surface of the first etch-stop film (360) formed on the upper surface of the conductive structure film are exposed, and then a first capping film (380) can be formed on the first interlayer insulating film (370) and the first etch-stop film (360).

Accordingly, the first interlayer insulating film (370) can fill the space between the first spacer structures formed on the sidewalls of the third gate structures (330), and the space between the first spacer structure formed on the sidewall of the third gate structure (330) and the second spacer structure formed on the sidewall of the conductive structure film.

The first interlayer insulating film (370) may include an oxide, such as silicon oxide, for example, and the first capping film (380) may include a nitride, such as silicon nitride, for example.

Referring to FIGS. 25 to 28, a first capping pattern (385) can be formed by etching a portion of a first capping film (380) formed on a first region (I) of a substrate (100), and using this as an etching mask, a first etch-stop film (360), a tenth mask film (270), a fourth conductive film (260), a first barrier film (250), and a third conductive film (240) can be sequentially etched.

In exemplary embodiments, a plurality of first capping patterns (385) may be formed on the first region (I) of the substrate (100) so as to extend in the second direction (D2) and be spaced apart from each other along the first direction (D1). Meanwhile, a first capping film (380) may remain on the second region (II) of the substrate (100).

By performing the above etching process, a fifth conductive pattern (245), a second barrier pattern (255), a sixth conductive pattern (265), a tenth mask (275), a first etching stop pattern (365), and a first capping pattern (385) may be sequentially formed on the first opening (230) on the first region (I) of the substrate (100), and a third insulating pattern (205), a fifth conductive pattern (245), a second barrier pattern (255), a sixth conductive pattern (265), a tenth mask (275), a first etching stop pattern (365), and a first capping pattern (385) may be sequentially formed on the second insulating film (190) of the insulating film structure (210) outside the first opening (230).

Hereinafter, the sequentially stacked fifth conductive pattern (245), the second barrier pattern (255), the sixth conductive pattern (265), the tenth mask (275), the first etching stop pattern (365), and the first capping pattern (385) are collectively referred to as a bit line structure (395). In exemplary embodiments, the bit line structure (395) may extend in the second direction (D2) on the first region (I) of the substrate (100) and may be formed in multiple pieces spaced apart from each other along the first direction (D1).

Meanwhile, a dummy bit line structure (397) including a seventh conductive pattern (247), a third barrier pattern (257), an eighth conductive pattern (267), an eleventh mask (277), a second etch-stop pattern (367), and a second capping pattern (387) sequentially stacked on a first region (I) of the substrate (100) adjacent to a second region (II) of the substrate (100) along the first direction (D1) may be formed, and a first etch-stop film (360) may remain on the third gate structure (330), the first and second spacer structures, a portion of the insulating film structure (210), the second active pattern (105), and the device isolation structure (110). Additionally, a first capping film (380) may remain on the first etching-stop film (360) formed on the upper surface of the third gate structure (330) and on the first interlayer insulating film (370).

Referring to FIGS. 29 and 30, after forming a fifth spacer film on a substrate (100) on which a bit line structure (395), a dummy bit line structure (397), and a first capping film (380) are formed, fourth and fifth insulating films can be sequentially formed on the fifth spacer film.

The fifth spacer film can also cover the sidewall of the third insulating pattern (205) below the bit line structure (395) formed on the second insulating film (190), and the fifth insulating film can fill the remaining portion of the first opening (230).

The fifth spacer film may include a nitride, such as, for example, silicon nitride, the fourth insulating film may include an oxide, such as, for example, silicon oxide, and the fifth insulating film may include a nitride, such as, for example, silicon nitride.

Thereafter, an etching process may be performed to etch the fourth and fifth insulating films. In exemplary embodiments, the etching process may be performed by a wet etching process using, for example, phosphoric acid (H ₂ PO ₃ ), SC1, and hydrofluoric acid (HF) as an etchant, and all portions of the fourth and fifth insulating films except for a portion formed within the first opening (230) may be removed. Accordingly, most of the surface of the fifth spacer film, that is, all portions of the fifth spacer film except for a portion formed within the first opening (230), may be exposed, and portions of the fourth and fifth insulating films remaining within the first opening (230) may form fourth and fifth insulating patterns (410, 420), respectively.

Thereafter, a sixth spacer film is formed on the exposed fifth spacer film surface and the fourth and fifth insulating patterns (410, 420) formed in the first opening (230), and then anisotropically etched to form a sixth spacer (430) covering a sidewall of the bit line structure (395) on the fifth spacer film surface and the fourth and fifth insulating patterns (410, 420). At this time, the sixth spacer (430) may also be formed on one sidewall of the dummy bit line structure (397). The sixth spacer (430) may include, for example, an oxide such as silicon oxide.

Thereafter, for example, a dry etching process may be additionally performed to form a second opening (440) that exposes the upper surface of the first active pattern (101), and the upper surface of the element isolation structure (110) and the upper surface of the first gate mask (160) may also be exposed through the second opening (440).

By the above dry etching process, the fifth spacer film portion formed on the upper surface of the first capping film (380), the first and second capping patterns (385, 387), and the second insulating film (190) can be removed, and thus, the fifth spacer (400) covering the sidewall of the bit line structure (395) can be formed. At this time, the fifth spacer (400) can also cover the sidewall of the dummy bit line structure (397).

In addition, in the dry etching process, the first and second insulating films (180, 190) may also be partially removed and remain as first and second insulating patterns (185, 195), respectively, under the bit line structure (395). The first to third insulating patterns (185, 195, 205) sequentially stacked under the bit line structure (395) may together form an insulating pattern structure (215).

Referring to FIGS. 31 to 33, a seventh spacer film is formed on the upper surface of the first capping film (380) and the first and second capping patterns (385, 387), the outer wall of the sixth spacer (430), a portion of the upper surface of the fourth and fifth insulating patterns (410, 420), and the upper surface of the first active pattern (101), the device isolation structure (110), and the first gate mask (160) exposed by the second opening (440), and then the seventh spacer film may be anisotropically etched to form a seventh spacer (450) that covers the outer wall of the sixth spacer (430) formed on the sidewall of the bit line structure (395) and the dummy bit line structure (397). The seventh spacer (450) may include, for example, a nitride such as silicon nitride.

The fifth to seventh spacers (400, 430, 450) sequentially stacked along the horizontal direction on the sidewall of the bit line structure (395) on the first region (I) of the substrate (100) may be collectively referred to as a preliminary third spacer structure (460).

Thereafter, a preliminary lower contact plug film including amorphous silicon doped with impurities is formed on the first region (I) of the substrate (100) to a sufficient height to fill the second opening (440) formed on the first region (I) of the substrate (100), and a melting laser annealing (MLA) process can be performed by irradiating laser light, whereby the preliminary lower contact plug film can be crystallized to form a lower contact plug film including polysilicon doped with impurities.

Thereafter, the upper portion of the lower contact plug film may be flattened until the upper surfaces of the first capping film (380) and the first and second capping patterns (385, 387) are exposed, thereby forming a lower contact plug (475). The lower contact plug (475) may be formed between bit line structures (395) adjacent to each other in the first direction (D1) on the first region (I) of the substrate (100), and between the bit line structure (395) and the dummy bit line structure (397), and may extend in the second direction (D2), and may be formed in multiple pieces so as to be spaced apart from each other along the first direction (D1).

Thereafter, an etching mask having third openings extending in the first direction (D1) and spaced apart from each other in the second direction (D2) is formed on the first capping film (380), the bit line structure (395), the dummy bit line structure (397), and the lower contact plug (475), and an etching process using the mask is performed on the lower contact plug (475) to form a fourth opening (445).

In exemplary embodiments, the third opening may overlap the first and second gate structures (172, 174) along the vertical direction, and thus the fourth opening (445) may be formed to expose a top surface of the first gate mask (160) included in each of the first and second gate structures (172, 174). As the fourth opening (445) is formed, the lower contact plug (475) extending in the second direction (D2) may be separated into a plurality of portions spaced apart from each other in the second direction (D2). At this time, each of the lower contact plugs (475) may contact a top surface of each end portion of the first active pattern (101) extending in the third direction (D3) in the third direction (D3).

After removing the etching mask, a barrier pattern (480) may be formed to fill the fourth opening (445). The barrier pattern (480) may be formed in multiple pieces between bit line structures (395) adjacent to each other in the first direction (D1) on the first region (I) of the substrate (100) and between the bit line structure (395) and the dummy bit line structure (397) so as to be spaced apart from each other in the second direction (D2). The barrier pattern (480) may include, for example, an insulating nitride such as silicon nitride.

Up to now, the preliminary lower contact plug film extending in the second direction (D2) between the bit line structures (395) adjacent to each other in the first direction (D1) has been formed, and the MLA process is performed thereon to form the lower contact plug film, and then the upper portion of the lower contact plug film is planarized to form the lower contact plug (475), and a fourth opening (445) penetrating therethrough and spaced apart from each other along the second direction (D2) is formed, and then a barrier pattern (480) filling the fourth opening (445) is formed, thereby forming lower contact plugs (475) and barrier patterns (480) that are alternately and repeatedly arranged along the second direction (D2). However, the concept of the present invention is not limited thereto.

That is, in another embodiment, a barrier film extending in the second direction (D2) is formed between bit line structures (395) adjacent to each other in the first direction (D1), fifth openings are formed penetrating the barrier film and spaced apart from each other along the second direction (D2) to separate the barrier film into barrier patterns (480) spaced apart from each other in the second direction (D2), and then the preliminary lower contact plug film filling the fifth openings is formed on the barrier film, and an MLA process is performed thereon to form the lower contact plug film, and then the upper portion thereof is planarized to form lower contact plugs (475), thereby forming lower contact plugs (475) and barrier patterns (480) that are alternately and repeatedly arranged along the second direction (D2).

In another embodiment, a second sacrificial film including an oxide such as silicon oxide is formed between neighboring bit line structures (395) in the first direction (D1) and extends in the second direction (D2), and barrier patterns (480) are formed that penetrate the second sacrificial film and are spaced apart from each other along the second direction (D2), and then the remaining second sacrificial film is removed to form sixth openings, and the preliminary lower contact plug film filling the sixth openings is formed on the barrier patterns (480), and then an MLA process is performed thereon to form a lower contact plug film (472), and an upper portion thereof is planarized to form lower contact plugs (475), thereby forming lower contact plugs (475) and barrier patterns (480) that are alternately and repeatedly arranged along the second direction (D2).

Referring to FIG. 34, the upper portion of the lower contact plug (475) is removed to expose the upper portion of the preliminary third spacer structure (460) formed on the sidewalls of the bit line structure (395) and the dummy bit line structure (397), and then the upper portions of the sixth and seventh spacers (430, 450) of the exposed preliminary third spacer structure (460) can be removed.

Thereafter, the upper portion of the lower contact plug (475) can be additionally removed. Accordingly, the upper surface of the lower contact plug (475) can be lower than the uppermost surfaces of the sixth and seventh spacers (430, 450).

Thereafter, an eighth spacer film is formed on the bit line structure (395), the dummy bit line structure (397), the preliminary third spacer structure (460), the barrier pattern (480), the first capping film (380), and the lower contact plug (475), and by anisotropically etching the film, an eighth spacer (490) that covers the upper portion of the preliminary third spacer structure (460) formed on each of the two sidewalls of the bit line structure (395) in the first direction (D1) can be formed, thereby exposing the upper surface of the lower contact plug (475).

Thereafter, an ohmic contact pattern (500) can be formed on the upper surface of the exposed lower contact plug (475). In exemplary embodiments, the ohmic contact pattern (500) can be formed by forming a first metal film on the first and second capping patterns (385, 387), the barrier pattern (480), the first capping film (380), the eighth spacer (490), and the lower contact plug (475), performing a heat treatment, and then removing an unreacted portion of the first metal film. The ohmic contact pattern (500) can include, for example, a metal silicide such as cobalt silicide, nickel silicide, or titanium silicide.

Referring to FIGS. 35 and 36, a first capping film (380) portion formed on a second region (II) of the substrate (100) adjacent to a first region (I) of the substrate (100) in a first direction (D1), and a seventh opening (520) that penetrates the first interlayer insulating film (370), the first etch-stop film (360), the insulating pattern structure (215), the device isolation structure (110), and the first gate mask (160) thereunder to expose the first conductive pattern (140) can be formed.

In exemplary embodiments, the seventh opening (520) may penetrate the first gate mask (160) formed at the first end (173) of the first gate structure (172) or the first end (175) of the second gate structure (174) to expose the upper surface of the first conductive pattern (140).

Referring to FIGS. 37 and 38, after forming the first and second capping patterns (385, 387), the barrier pattern (480), the eighth spacer (490), the ohmic contact pattern (500), and the lower contact plug (475) formed on the first region (I) of the substrate (100), and the first capping film (380) formed on the second region (II) of the substrate (100), and the fourth barrier film (530) on the sidewall of the seventh opening (520) and the device isolation structure (110) and the first conductive pattern (140) exposed thereby, a second metal film (540) can be formed on the fourth barrier film (530) to fill the space between the bit line structures (395), the space between the bit line structure (395) and the dummy bit line structure (397), and the seventh opening (520).

Referring to FIGS. 39 and 40, the second metal film (540) and the fourth barrier film (530) can be patterned.

Accordingly, an upper contact plug (549) may be formed on a first region (I) of the substrate (100), and a third wiring (605) may be formed on a second region (II) of the substrate (100). In addition, first and second wirings (602, 604) may be formed on a portion of a second region (II) of the substrate (100) adjacent to the first region (I) of the substrate (100) in the first direction (D1), and a fourth wiring (607) may be formed on a portion of the first region (I) of the substrate (100) adjacent to the second region (II) of the substrate (100) in the first direction (D1). At this time, an eighth opening (547) may be formed between the upper contact plug (549) and the first to fourth wirings (602, 604, 605, 607).

In exemplary embodiments, the first wiring (602) may overlap the first end (173) of the first gate structure (172) along the vertical direction, and the second wiring (604) may overlap the first end (175) of the second gate structure (174) along the vertical direction. Accordingly, the first wiring (602) may be formed in multiple pieces so as to be spaced apart from each other along the second direction (D2) on the second region (II) portion of the substrate (100) formed on the first side of the first region (I) of the substrate (100), and the second wiring (604) may be formed in multiple pieces so as to be spaced apart from each other along the second direction (D2) on the second region (II) portion of the substrate (100) formed on the second side of the first region (I) of the substrate (100). In exemplary embodiments, the first and second wires (602, 604) may be arranged in a zigzag pattern along the second direction (D2) on portions of the second region (II) of the substrate (100) formed on each of the two sides in the first direction (D1) of the substrate (100).

The eighth opening (547) can be formed by partially removing not only the second metal film (540) and the fourth barrier film (530), but also the first and second capping patterns (385, 387), the barrier pattern (480), the first capping film (380), the preliminary third spacer structure (460), the eighth spacer (490), the first etch-stop film (360), the first etch-stop pattern (365), and the tenth mask (275), thereby exposing the upper surface of the sixth spacer (430).

As the eighth opening (547) is formed, the second metal film (540) and the fourth barrier film (530) on the first region (I) of the substrate (100) may be converted into the first metal pattern (545) and the fourth barrier pattern (535) covering the lower surface thereof, respectively, and these may together form an upper contact plug (549). In exemplary embodiments, the upper contact plugs (549) may be formed in multiple pieces so as to be spaced apart from each other along the first and second directions (D1, D2) on the first region (I) of the substrate (100) and may be arranged in a honeycomb shape when viewed from above. Each of the upper contact plugs (549) may have, for example, a circular, oval, or polygonal shape when viewed from the top.

The lower contact plug (475), the ohmic contact pattern (500), and the upper contact plug (549) sequentially stacked on the first region (I) of the substrate (100) can together form a first contact plug structure.

Each of the first and second wires (602, 604) may include a third metal pattern (590) and a sixth barrier pattern (580) covering a lower surface thereof. The third wire (605) may include a fourth metal pattern (595) and a seventh barrier pattern (585) covering a lower surface thereof. The fourth wire (607) may include a fifth metal pattern (597) and an eighth barrier pattern (587) covering a lower surface thereof.

Meanwhile, a second contact plug (570) including a second metal pattern (560) and a fifth barrier pattern (550) may be formed within the seventh opening (520). In exemplary embodiments, the second contact plug (570) may contact the first ends (173, 175) included in each of the first and second gate structures (172, 174). At this time, since the first ends (173, 175) included in each of the first and second gate structures (172, 174) do not include the second conductive pattern (150), the second contact plug (570) may contact the first conductive pattern (140) by penetrating the first gate mask (160) and may not contact the second conductive pattern (150).

The first and second wirings (602, 604) may be in contact with the first conductive pattern (140) through the second contact plug (570), thereby applying electrical signals to the first and second gate structures (172, 174), respectively. The third wiring (605) may overlap the third gate structure (330) in the vertical direction. The fourth wiring (607) may overlap the dummy bit line structure (397) in the vertical direction.

Referring to FIGS. 41 to 44, the exposed sixth spacer (430) may be removed to form an air gap (435) communicating with the eighth opening (547). The sixth spacer (430) may be removed, for example, by a wet etching process.

In exemplary embodiments, the sixth spacer (430) formed on the sidewall of the bit line structure (395) extending in the second direction (D2) and the sidewall of the dummy bit line structure (397) can be removed not only in the portion directly exposed by the eighth opening (547) but also in the portion parallel to the portion in the horizontal direction. That is, not only in the portion of the sixth spacer (430) exposed by the eighth opening (547) and not covered by the upper contact plug (549), but also in the portion covered by the upper contact plug (549) can be removed.

Afterwards, a second interlayer insulating film can be formed to fill the eighth opening (547).

In exemplary embodiments, the second interlayer insulating film may include sixth and seventh insulating films (610, 620) that are sequentially laminated. The sixth insulating film (610) may be formed using an insulating material having low gapfill characteristics, and thus, the air gap (435) below the eighth opening (547) may remain unfilled. At this time, the air gap (435) may also be referred to as an air spacer (435) and may form a third spacer structure (465) together with the fifth and seventh spacers (400, 450). That is, the air gap (435) may be a spacer that includes air. The seventh insulating film (620) may include an oxide, such as silicon oxide, or a nitride, such as silicon nitride.

Afterwards, a capacitor (665) that comes into contact with the upper surface of the upper contact plug (549) can be formed.

That is, a second etch-stop film (630) and a mold film (not shown) may be sequentially formed on the upper contact plug (549), the second interlayer insulating film, and the first to fourth wirings (602, 604, 605, 607), and these may be partially etched to form a ninth opening that partially exposes the upper surface of the upper contact plug (549). The second etch-stop film (630) may include, for example, a nitride such as silicon nitride.

A lower electrode film filling the ninth opening may be formed on the upper surface of the exposed upper contact plug (549) and the mold film, and the upper portion of the lower electrode film may be planarized until the upper surface of the mold film is exposed, thereby node-separating the lower electrode film. Thereafter, for example, the mold film may be removed by performing a wet etching process, and thus a pillar-shaped lower electrode (640) may be formed on the upper surface of the exposed upper contact plug (549). Alternatively, a cylindrical lower electrode (640) may be formed within the ninth opening. The lower electrode (640) may include a metal, a metal nitride, a metal silicide, polysilicon doped with impurities, or the like.

Thereafter, a dielectric film (650) is formed on the surface of the lower electrode (640) and the second etching-stop film (630), and an upper electrode (660) is formed on the dielectric film (650), thereby forming a capacitor (670) including the lower electrode (640), the dielectric film (650), and the upper electrode (660) on the first region (I) of the substrate (100).

The dielectric film (650) may include, for example, a metal oxide, and the upper electrode (660) may include a metal, a metal nitride, a metal silicide, polysilicon doped with impurities, etc.

Thereafter, by forming contact plugs and upper wirings electrically connected to the capacitor (670), bit line structure (395), and first to fourth wirings (602, 604, 605, 607) formed on the substrate (100), the manufacturing of the semiconductor device can be completed.

As described above, the upper portion of the preliminary device isolation structure (111) is removed on portions of the second region (II) of the substrate (100) adjacent to the first region (I) of the substrate (100) to form the fourth and fifth recesses (52, 54), and the upper portion of the preliminary device isolation structure (111) and the first active pattern (101) is removed on the first region (I) of the substrate (100) to form the sixth and seventh recesses (98, 99) which are respectively connected to the fourth and fifth recesses (52, 54) and extend in the first direction (D1), and then the first gate structure (172) can be formed in the fourth and sixth recesses (52, 98) and the second gate structure (174) can be formed in the fifth and seventh recesses (54, 99). At this time, the first and second widths (W1, W2) of the fourth and fifth recesses (52, 54) may be larger than the third and fourth widths (W3, W4) of the sixth and seventh recesses (98, 99), respectively.

If sixth and seventh recesses (98, 99) extending in the first direction (D1) are formed on the first region (I) of the substrate (100) and the second region (II) of the substrate (100) adjacent thereto, and first and second gate structures (172, 174) are formed within them, respectively, the spacing between etching masks used in the double patterning process or quadruple patterning process for forming the sixth and seventh recesses (98, 99) may be formed differently due to the difference in the substructures formed in the first and second regions (I, II) of the substrate (100).

That is, in the double patterning process or quadruple patterning process, the gap between the etching masks formed on the second region (II) of the substrate (100) on which the preliminary element isolation structure (111) including oxide is formed may be smaller than the gap between the etching masks formed on the first region (I) of the substrate (100) on which the first active pattern (101) including silicon is formed together with the preliminary element isolation structure (111), and accordingly, the width in the second direction (D2) of each of the sixth and seventh recesses (98, 99) formed to extend in the first direction (D1) may be formed smaller on the second region (II) of the substrate (100) than on the first region (I) of the substrate (100).

Accordingly, the width of the end portions of each of the sixth and seventh recesses (98, 99) formed on the second region (II) of the substrate (100) may be formed narrowly, and the end portions of each of the first and second gate structures (172, 174) may not be formed properly within them. This may cause poor contact with the second contact plug (570) formed to contact the end portions of each of the first and second gate structures (172, 174) thereafter, thereby preventing good electrical signal transmission.

However, in exemplary embodiments, fourth and fifth recesses (52, 54) having a larger width in the second direction (D2) than the sixth and seventh recesses (98, 99) formed on the first region (I) of the substrate (100) are separately formed on the second region (II) of the substrate (100), and the sixth and seventh recesses (98, 99) are formed in the first region (I) of the substrate (100) so as to be respectively connected thereto, and then the first and second gate structures (172, 174) can be formed within the fourth and sixth recesses (52, 98) that are connected to each other and the fifth and seventh recesses (54, 99) that are connected to each other.

Accordingly, the width of the ends of the first direction (D1) of each of the first and second gate structures (172, 174) in the second direction (D2) may not be formed narrowly, and the electrical connection with the second contact plug (570) formed to make contact therewith may be good.

Although the present invention has been described with reference to preferred embodiments thereof as described above, it will be understood by those skilled in the art that various modifications and changes may be made to the present invention without departing from the spirit and scope of the present invention as set forth in the claims.

20, 30: 1st and 2nd mask membranes
40, 45, 275, 277: 3rd, 9th, 10th, 11th masks
70, 80, 90, 25, 35: 4th to 8th mask membranes
100: Substrate
102, 104, 106, 52, 54, 98, 99: 1st to 7th recesses
110: Element isolation structure 111: Spare element isolation structure
112, 114, 116: First to third element separation patterns
113: First element separator
120, 280: First and second gate insulation patterns
125, 220: First and second gate insulating films
140, 150, 290, 310, 245, 265, 247, 267: 1st to 8th challenge patterns
160, 320: 1st and 2nd gate masks
172, 174, 330: First to third gate structures
180, 190, 200: 1st to 3rd insulating films
185, 195, 205, 410, 420: 1st to 5th insulation patterns
210: Insulating film structure 215: Insulating pattern structure
230, 440: 1st and 2nd openings
240, 260: 3rd and 4th challenge curtains
250, 530: 1st, 4th barrier membrane 270: 10th mask membrane
300, 255, 257, 535, 550, 580, 585, 587: 1st to 8th barrier patterns
340, 345, 350, 355, 400, 430, 450, 490: 1st to 8th spacers
360, 630: First and second etching stop films 365, 367: First and second etching stop patterns
370: First interlayer insulating film 380: First capping film
385, 387: 1st and 2nd capping patterns
395: Bit line structure 397: Dummy bit line structure
435: Air spacer 445, 520, 547: 4th, 7th, 8th openings
460: Spare third spacer structure 465: Third spacer structure
475, 549: Lower, Upper Contact Plugs
500: Ohmic contact pattern 540: Second metal film
545, 560, 590, 595, 597: First to fifth metal patterns
570: Second contact plug 602, 604, 605, 607: First to fourth wiring
610, 620: 6th and 7th insulating films 640, 660: Lower and upper electrodes
650: dielectric film 670: capacitor

Claims (10)

First and second gate structures embedded in the upper portion of the substrate, each extending in a first direction and alternately and repeatedly arranged along a second direction intersecting the first direction;
Bit line structures extending in the second direction on the first and second gate structures and spaced apart from each other in the first direction; and
Comprising capacitors formed on the above bit line structures,
The width of the first end of each of the first gate structures in the first direction in the second direction is greater than the width of the remaining portions of each of the first gate structures in the second direction, and the width of the first end of each of the second gate structures in the first direction in the second direction is greater than the width of the remaining portions of each of the second gate structures in the second direction.
The first ends of the first gate structures are aligned with each other in the second direction, and the first ends of the second gate structures are aligned with each other in the second direction.
A semiconductor device wherein the first ends of the first gate structures and the second ends of the second gate structures are arranged in a zigzag pattern along the second direction. A semiconductor device in the first aspect, wherein the second ends of the first gate structures in the first direction are aligned with each other in the second direction, and the second ends of the second gate structures in the first direction are aligned with each other in the second direction. A semiconductor device in the second aspect, wherein the first ends of the first gate structures partially overlap with the second ends of the second gate structures in the second direction, and the first ends of the second gate structures partially overlap with the second ends of the first gate structures in the second direction. In the first paragraph, the bottom surface of the first end of each of the first gate structures is formed at substantially the same height as the bottom surfaces of the remaining portions of each of the first gate structures,
A semiconductor device wherein the bottom surface of the first end of each of the second gate structures is formed at substantially the same height as the bottom surfaces of the remaining portions of each of the second gate structures. In the first aspect, the substrate includes a first region and a second region surrounding the first region,
A semiconductor device wherein the first and second gate structures are formed in the first region of the substrate and in portions of the second region of the substrate adjacent to the first region of the substrate in the first direction. In the fifth paragraph, a semiconductor device wherein the first ends of the first and second gate structures are formed in the second region portions of the substrate. A semiconductor device in claim 1, wherein each of the gate structures includes a gate insulating pattern, a first conductive pattern, a second conductive pattern, and a gate mask sequentially stacked along a vertical direction perpendicular to an upper surface of the substrate. A semiconductor device in claim 7, wherein the second challenge pattern is not formed on the first end of each of the first and second gate structures. A semiconductor device in claim 7, further comprising a contact plug contacting the first end of each of the first and second gate structures. A semiconductor device in claim 9, wherein the contact plug penetrates the gate mask included in each of the first and second gate structures and contacts the second conductive pattern, but does not contact the first conductive pattern.