CN218998733U - Semiconductor memory device with a memory cell having a memory cell with a memory cell having a memory cell - Google Patents

Abstract

A semiconductor memory device includes a substrate; a plurality of buried word lines; and a plurality of storage node plugs. The substrate includes a plurality of active regions isolated from the shallow trenches. Buried word lines are buried within the substrate, through shallow trench isolations or active areas. The storage node plug is arranged on the substrate and is contacted with the active area, and the storage node plug comprises a plurality of first plugs which respectively comprise an insulating material and a conductive material which are sequentially stacked from bottom to top. At least one active region of the semiconductor memory device is in contact with two first plugs simultaneously; alternatively, the semiconductor memory device further includes a storage node pad physically contacting at least two first plugs. Thus, the utility model is beneficial to forming a semiconductor memory device with better component reliability.

Description

Semiconductor memory device with a memory cell having a memory cell with a memory cell having a memory cell

Technical Field

The present utility model relates to a semiconductor device, and more particularly, to a semiconductor memory device.

Background

With the trend toward miniaturization of various electronic products, the design of dynamic random access memory (dynamic random access memory, DRAM) cells must meet the requirements of high integration and high density. For a DRAM cell with a recessed gate structure, the current trend is that it has gradually replaced a DRAM cell with a planar gate structure because it can obtain a longer carrier channel length in the same semiconductor substrate to reduce the leakage of the capacitor structure. In general, DRAM cells having recessed gate structures include a transistor element and a charge storage device to receive voltage signals from bit lines and word lines. However, due to the limitations of process technology, there are a number of drawbacks to the existing DRAM cells with recessed gate structures, which further improve and effectively enhance the performance and reliability of the associated memory devices.

Disclosure of Invention

One of the objectives of the present disclosure is to provide a semiconductor memory device and a method for fabricating the same, in which a plurality of storage node plugs are simultaneously disposed in a dense region (dense region) of the semiconductor memory device, and a plurality of dummy storage node plugs are disposed in a loose region (iso region) of the semiconductor memory device, so that the same luminous flux can be maintained in both regions during the photolithography process, thereby facilitating the improvement of the fabrication yield of the semiconductor memory device. Thus, the dummy storage node plug can be formed without adding extra operation steps, so that the structural defect possibly caused by the problem can be effectively improved, and the semiconductor storage device with better component reliability can be formed.

To achieve the above object, one embodiment of the present disclosure provides a semiconductor memory device including a substrate; a plurality of buried word lines; a plurality of storage node plugs; a plurality of storage node pads. The substrate comprises a plurality of active areas and shallow trench isolations, wherein the shallow trench isolations surround the active areas. The buried word line is buried within the substrate and is located on the shallow trench isolation or the active region, respectively. The storage node plug is arranged on the substrate and contacts the active region, and comprises a plurality of first plugs, wherein each first plug respectively comprises an insulating material and a conductive material which are sequentially stacked from bottom to top. The storage node pads are disposed on the storage node plugs, one of the storage node pads being in physical contact with at least two of the first plugs simultaneously.

To achieve the above object, another embodiment of the present disclosure provides a semiconductor memory device including a substrate; a plurality of buried word lines; a plurality of storage node plugs. The substrate comprises a plurality of active areas and shallow trench isolations, wherein the shallow trench isolations surround the active areas. The buried word line is buried within the substrate and is located on the shallow trench isolation or the active region, respectively. The storage node plugs are arranged on the substrate and contact the active areas, the storage node plugs comprise a plurality of first plugs, each first plug comprises an insulating material and a conductive material which are sequentially stacked from bottom to top, and at least one active area simultaneously contacts two first plugs.

In order to achieve the above object, another embodiment of the present disclosure provides a method for manufacturing a semiconductor memory device, which includes the following steps. First, a substrate is provided, wherein a plurality of active areas and shallow trench isolations are included in the substrate, and the shallow trench isolations surround the active areas. Then, a plurality of buried word lines are formed in the substrate, buried in the substrate, and respectively located on the shallow trench isolation or the active region. And forming a plurality of storage node plugs on the substrate and contacting the active region, wherein the storage node plugs comprise a plurality of first plugs, and each first plug comprises an insulating material and a conductive material which are sequentially stacked from bottom to top. And forming a plurality of storage node pads on the storage node plugs, wherein one of the storage node pads physically contacts at least two of the first plugs at the same time.

Drawings

Fig. 1 to 8 are schematic views showing a manufacturing process of a semiconductor memory device according to a first embodiment of the present utility model; wherein the method comprises the steps of

Fig. 1 is a schematic cross-sectional view of a semiconductor memory device of the present utility model after an insulating layer is formed;

FIG. 2 is a schematic cross-sectional view of a semiconductor memory device according to the present utility model after an etching process;

FIG. 3 is a schematic cross-sectional view of a semiconductor memory device of the present utility model after forming insulating sidewalls;

fig. 4 is a schematic cross-sectional view of the semiconductor memory device of the present utility model after performing an epitaxial fabrication process;

fig. 5 is a schematic cross-sectional view of the semiconductor memory device of the present utility model after forming a mask layer;

FIG. 6 is a schematic cross-sectional view of a semiconductor memory device of the present utility model after forming a storage node pad;

fig. 7 is a schematic cross-sectional view of the semiconductor memory device of the present utility model after forming an insulating material layer; and

fig. 8 is a schematic cross-sectional view of the semiconductor memory device of the present utility model after performing an etching back process.

Fig. 9 is a schematic diagram showing a manufacturing process of a semiconductor memory device according to a second embodiment of the utility model.

Fig. 10 is a schematic diagram showing a manufacturing process of a semiconductor memory device according to a third embodiment of the utility model.

Wherein reference numerals are as follows:

the accompanying drawings provide a further understanding of the embodiments of the utility model and are incorporated in and constitute a part of this specification. These drawings and description serve to illustrate principles of some embodiments. It should be noted that all the drawings are schematic, and for convenience of description and drawing, the relative dimensions and proportions should be adjusted according to the actual situation. The same reference signs represent corresponding or similar features in different embodiments.

100. 300, 400 semiconductor memory device

110. Substrate and method for manufacturing the same

110A storage area

110B peripheral region

120. Shallow trench isolation

130. 131, 133 active area

140. Gate structure

141. Ditch groove

142. Dielectric layer

143. Gate dielectric layer

144. Gate electrode

145. Cover layer

147. Dielectric layer

150. Insulating layer

150a, 350a etched surfaces

151. 153, 155 openings

152. 154 open pore

161. 163, 165 insulating side wall

170. Mask layer

181. Epitaxial layer

190. Conductive material layer

191. 192 conductive layer

193. 195 conductive pad

200. Mask layer

201. 203 mask pattern

213. 313 first plug

215. 415 second plug

211. Third plug

220. Insulating material layer

221. 223 insulating layer

310. Air gap

310a top surface

492. Conductive layer

P1 first pitch

P2 second pitch

P3 third pitch

Detailed Description

The following description sets forth the preferred embodiments of the present utility model and, together with the accompanying drawings, provides a further understanding of the utility model, as well as details of the structure and advantages to be achieved, to those skilled in the art to which the utility model pertains. It is to be understood that the following exemplary embodiments may be substituted, rearranged, and mixed for the features of several different embodiments without departing from the spirit of the utility model to accomplish other embodiments.

Referring to fig. 1 to 8, a process for manufacturing a semiconductor memory device 100 according to a first embodiment of the present disclosure is shown. First, as shown in fig. 1, the semiconductor memory device 100 includes a substrate 110, such as a silicon base, a silicon-containing substrate (e.g., siC, siGe), or a silicon-on-insulator (SOI) substrate, and the like, and the substrate 110 further includes a memory region 110A having a relatively high device integration and a peripheral region 110B having a relatively low device integration. Preferably, the peripheral region 110B is disposed on at least one side of the storage region 110A, for example, if the peripheral region 110B is seen from a top view (not shown), the peripheral region 110B may be entirely surrounded on the outside of the storage region 110A, but is not limited thereto.

As further shown in fig. 1, at least one shallow trench isolation (shallow trench isolation, STI) 120 is formed in the substrate 110 to define a plurality of active areas 130 in the substrate 110, such that the shallow trench isolation 120 may be disposed around the active areas 130, wherein the active areas 130 further include an active area 131 formed in the memory region 110A and an active area 133 formed in the peripheral region 110B and adjacent to the memory region 110A, preferably, the active area 131 and the active area 133 have different extension lengths, and the active area 133 may have a relatively large extension length, but is not limited thereto. In one embodiment, the shallow trench isolation 120 is formed by etching a plurality of trenches (not shown) in the memory region 110A and the peripheral region 110B of the substrate 110, filling the trenches with an insulating material (such as silicon oxide or silicon oxynitride) and forming the shallow trench isolation 120 after the planarization process, but not limited thereto.

In addition, a plurality of buried gate structures 140 are formed in the substrate 110, and each of the buried gate structures includes a dielectric layer 142, a gate dielectric layer 143, a gate 144 and a cap layer 145 sequentially stacked from bottom to top, wherein a top surface of the cap layer 145 of each of the gate structures 140 is cut out of a top surface of the cap layer Ji Chende, such that each of the gate structures 140 can be used as a buried Word Line (WL) of the semiconductor memory device 100 to receive or transmit a voltage signal from each of the memory cells (not shown). In one embodiment, the gate structure 140 is fabricated by, but not limited to, forming a plurality of trenches 141 in the substrate 110, sequentially forming a dielectric layer 142 covering the entire surface of each trench 141, a gate dielectric layer 143 covering the bottom half of each trench 141, and a gate 144 filling the bottom half of each trench 141, and forming a cap layer 145 filling the top half of each trench 141 after etching back portions of the gate 144 and the gate dielectric layer 143. It should be noted that the gate structures 140 formed in the memory region 110A are arranged in sequence according to the same first pitch P1 and are simultaneously staggered with the active regions 131 and the shallow trench isolations 120 in the memory region 110A, and the gate structures 140 formed in the peripheral region 110B are arranged in sequence according to a relatively larger second pitch P2 (the second pitch P2 is larger than the first pitch P1) and are staggered with the active regions 133 and the shallow trench isolations 120 in the peripheral region 110B.

Although the specific extending directions of the active regions 130 (the active regions 131 and 133) and the gate structures 140 are not specifically shown in the drawings in this embodiment, it should be understood that, if viewed from a top view (not shown), the active regions 131 and 133 should extend parallel to each other along a first direction (not shown) and be arranged in an array in the memory region 110A and the peripheral region 110B, and the gate structures 140 should extend parallel to each other along a second direction (not shown) and pass through the active regions 131 and 133 and the shallow trench isolation 120 in the memory region 110A and the peripheral region 110B, wherein the second direction intersects but is not perpendicular to the first direction, for example. In addition, in an embodiment, the active region 133 may further include a first portion (not shown) extending along the second direction, and a second portion (not shown) extending along a third direction (not shown) perpendicular to the second direction, so as to entirely take a rectangular frame shape or other suitable shape and surround the active region 131. Thus, the first portion and the second portion of the active region 133 form a protection structure, so as to avoid structural collapse or damage of the active region 131 in the storage region 110A.

Next, bit line contact (BLC, not shown) is formed in the substrate 110, and a plurality of bit lines (BL, not shown), a dielectric layer 147, and an insulating layer 150 filling a space between the bit lines are formed on the substrate 110. The bit lines extend in the third direction, for example, parallel to each other, and are spaced apart from each other, and are staggered with the buried word lines (i.e., the gate structures 140) and the active regions 131 in the memory region 110A, and the bit line contact plugs may be integrally formed with the bit lines and directly contact each of the active regions 131 to receive or transmit the voltage signals from each of the memory cells. In one embodiment, each of the bit lines includes a semiconductor layer (e.g., polysilicon, not shown), a barrier layer (e.g., titanium and/or titanium nitride, not shown), a conductive layer (e.g., low-resistance metal such as tungsten, aluminum, or copper), and a cap layer (e.g., silicon oxide, silicon nitride, or silicon oxynitride, not shown), the dielectric layer 147 preferably has a composite structure, such as an oxide-nitride-oxide (ONO) structure, and the insulating layer 150 includes an insulating material such as silicon oxide, silicon oxynitride, or the like, but is not limited thereto.

As shown in fig. 2, a mask layer (not shown) is formed on the insulating layer 150, and a plurality of openings 151, 153, 155 penetrating the insulating layer 150 and the dielectric layer 147 are formed by performing an etching process, such as a dry etching process, through the mask layer. The openings 151, 153, 155 are arranged in sequence according to the same third pitch P3, and preferably, the third pitch P3 is equal to the first pitch P1 and smaller than the second pitch P2, but not limited thereto. In detail, since the openings 151 formed in the storage region 110A and the gate structures 140 have substantially the same arrangement pitch (the third pitch P3 is equal to the first pitch P1), each opening 151 in the storage region 110A can be exactly located in each gate structure 140 in the substrate 110, such that the cap layer 145 of the gate structure 140 can be exposed from each opening 151.

On the other hand, since the gate structures 140 formed in the peripheral region 110B have a relatively large arrangement pitch (the second pitch P2), the openings 153 and 155 in the peripheral region 110B may not completely expose the cap layer 145 of the gate structure 140 to the respective gate structures 140 located in the peripheral region 110B, for example, only a portion of the openings 153 may completely expose only a portion of the surface of the active region 133, or only a portion of the surface of the gate structure 140, or only a portion of the shallow trench isolation 120 may be exposed by the remaining openings 153 and 155. In addition, since the material of the insulating layer 150 may have the same or a relatively smaller etching selectivity as the sti 120 and a relatively larger etching selectivity as the cap layer 145 of the gate structure 140, each opening 155 may further penetrate the surface of the sti 120 and extend into a portion of the sti 120, particularly the sti 120 extending down to the peripheral region 110B, but each opening 151, 153 may stop at the surface of the cap layer 145 or the active region 133, as shown in fig. 2. In other words, the openings 155 are formed by overetching in the etching process, and the etching degree of the openings 155 is different from each other, so that bottom surfaces having different heights can be formed.

As shown in fig. 3, deposition and etching back processes are sequentially performed on the substrate 110 to form a plurality of insulating sidewalls 161, 163, 165 respectively filling the openings 151, 153, 155, which are arranged between the bit lines along the third direction, for example. The insulating sidewalls 161 formed in the memory region 110A contact the cap layer 145 of each gate structure 140, respectively, and the insulating sidewalls 163, 165 formed in the peripheral region 110B contact the surface of the active region 133 or the shallow trench isolation 120, respectively. It should be noted that, by controlling the parameters of the size of the opening, the spacing between the openings, the etching time, and the position of the opening in the peripheral region 110B, each insulating sidewall 165 formed in the peripheral region 110B further extends into a portion of the shallow trench isolation 120, so as to increase the aspect ratio of the opening, and increase the difficulty of etching the opening and backfilling the insulating material, so that the insulating sidewalls 165 have bottom surfaces with different heights, as shown in fig. 3.

As shown in fig. 4, a mask layer 170 is formed on the insulating layer 150 and the insulating sidewalls 161, 163, 165 to cover the insulating layer 150 and the insulating sidewalls 163, 165 in the peripheral region 110B, so as to completely expose the insulating layer 150 and the insulating sidewalls 161 in the storage region 110A and partially expose the insulating layer 150 adjacent to and on both sides of the insulating sidewalls 163 of the storage region 110A. Then, an etching process, such as a wet etching process, is performed by covering the mask layer 170 to completely remove the insulating layer 150 and the dielectric layer 147 in the storage region 110A, so as to form a plurality of openings 152 to expose the surface of the active region 131, and simultaneously, to partially remove the insulating layer 150 adjacent to both sides of the insulating sidewall 163 of the storage region 110A, so as to form a plurality of openings 154. Then, a selective epitaxy (selective epitaxial growth, SEG) process is performed again with the coverage of the mask layer 170, a plurality of epitaxial layers 181 are formed from the exposed surfaces of the active region 131, and the mask layer 170 is removed. In one embodiment, the epitaxial layer 181 includes a conductive material, such as silicon (Si), silicon-phosphorus (SiP), silicon-germanium (SiGe), or germanium (Ge), but is not limited thereto.

It should be noted that, due to the difference of the component integration in the memory region 110A and the peripheral region 110B, the present utility model can further control the size of the opening 154, the spacing and the size of the insulating sidewalls 163 and 165, and the etching time, so that the etching process is easy to generate the incomplete etching in the peripheral region 110B adjacent to the memory region 110A due to the micro-loading effect (micro loading effect). Thus, the insulating sidewall 163 adjacent to the memory region 110A and the insulating layer 150 on both sides thereof are only partially removed, and the surface of the underlying active region 133 cannot be exposed, so that an epitaxial layer cannot be formed in the selective epitaxial process. Further, since the etching process is different in etching degree, the remaining insulating layers 150 on both sides of the insulating sidewall 163 may have top surfaces different from each other, and simultaneously form uneven etching surfaces 150a, as shown in fig. 4.

As shown in fig. 5, a deposition process is performed on the substrate 110 to form a layer 190 of conductive material that fills each of the openings 152, 154 and further overlies the insulating sidewalls 161, 163, 165 and the top surface of the insulating layer 150. In one embodiment, the conductive material layer 190 includes, but is not limited to, tungsten, titanium, aluminum, or copper. In one embodiment, a barrier layer (not shown) may be formed before the conductive material layer 190 is formed, and the barrier layer may include, but is not limited to, titanium/titanium nitride (TiN), tantalum (Ta)/tantalum nitride (TaN), and the like. Then, a mask layer 200 including a plurality of mask patterns 201, 203 is formed on the conductive material layer 190. In detail, the mask patterns 201 formed in the memory region 110A have relatively small widths and pitches for the conductive material layers 190 filled in the openings 152, and the mask patterns 203 formed in the peripheral region 110B have relatively large widths and pitches to alleviate the difference in pattern integration in the memory region 110A and the peripheral region 110B, so that each mask pattern 203 can cover the conductive material layers 190 filled in all the openings 154 at the same time or cover more than one insulating sidewall 165 and the insulating layers 150 on both sides thereof at the same time, as shown in fig. 5.

The etching process, such as a dry etching process, is performed by using the mask layer 200 to pattern the conductive material layer 190 covering the top surfaces of the insulating sidewalls 161, 163, 165 and the insulating layer 150, exposing the top surfaces of the insulating sidewalls 161, 163, 165 and the insulating layer 150 underneath, then further removing the insulating sidewalls 161, 163, 165 and the insulating layer 150 exposed from the mask layer 200, and finally removing the mask layer 200. Thus, as shown in fig. 6, conductive layers 191, 192 may be formed within openings 152, 154, respectively, while a plurality of conductive pads 193, 195 are formed over conductive layers 191, 192. It should be noted that the conductive layer 191 and the conductive pad 193 formed in the memory region 110A are sequentially stacked over the epitaxial layer 181, and the conductive layer 191 and the epitaxial layer 181 may be formed together to form the third plug 211. The third plugs 211 have a top surface higher than the insulating sidewalls 161, which are in physical contact with the upper conductive pads 193, respectively, and are located between the adjacent insulating sidewalls 161 and the buried word lines (gate structures 140), and in physical contact with the lower active regions 131. Thus, the third plug 211 is electrically connected to a transistor device (not shown) in the active region 131 by the underlying epitaxial layer 181, and is electrically connected to a subsequently formed capacitor device (not shown) by the overlying conductive pad 193.

On the other hand, each conductive layer 192 formed in the peripheral region 110B is stacked on the etched surface 150a of the insulating layer 150, and the first plug 213 is formed by sequentially stacking the insulating material (insulating layer 150) and the conductive material (conductive layer 192) between the adjacent insulating sidewalls 163, so as to physically contact the underlying active region 133. The first plugs 213 have the same or a higher top surface than the insulating sidewalls 163, wherein part of the first plugs 213 are not completely located between adjacent buried word lines, and even partially overlap the buried word lines in a direction perpendicular to the substrate 110. Thus, not only can the first plugs 213 not be electrically connected to the transistor elements in the active region 133, but at least two first plugs 213 are simultaneously in physical contact with the same conductive pad 195 to serve as dummy plugs. In this embodiment, all of the first plugs 213 are physically connected to the same conductive pad 195 at the same time, as shown in fig. 6. In addition, the remaining conductive pad 195 formed in the peripheral region 110B physically contacts the plurality of insulating sidewalls 165 and/or the insulating layer 150 over the shallow trench isolation 120 at the same time, such that the insulating layer 150 over the shallow trench isolation 120 and between adjacent insulating sidewalls 165 may also form a plurality of second plugs 215, the second plugs 215 may serve as dummy plugs, as shown in fig. 6.

As shown in fig. 7, a deposition process is performed on the substrate 110 to form a layer of insulating material 220 conformally covering the top surfaces of the conductive pads 193, 195, completely filling the space between the conductive pads 193 and partially filling the space between the conductive pads 195. In one embodiment, the insulating material layer 220 includes, but is not limited to, an insulating material such as silicon nitride, silicon carbonitride, etc., and preferably includes the same insulating material as the insulating sidewalls 161, 163, 165.

Then, as shown in fig. 8, an etching back process is performed to remove the insulating material layer 220 covering the top surfaces of the respective conductive pads 193, 195, form the insulating layer 221 between the respective conductive pads 193, and form the insulating layer 223 between the respective conductive pads 195. Wherein the top surface of the insulating layer 221 formed in the memory region 110A may be aligned with the top surface of each of the conductive pads 193, 195 and directly contact each of the insulating sidewalls 161 thereunder; the insulating layer 223 formed in the peripheral region 110B has a top surface that is not level with the top surface of each conductive pad 195, but has a relatively low recessed top surface and is also in direct contact with each underlying insulating sidewall 163, 165. Thus, the semiconductor memory device 100 in the first embodiment of the present utility model is completed.

According to the first embodiment of the present utility model, the semiconductor memory device 100 has buried word lines (i.e., gate structures 140) buried in the substrate 110, and plugs 211, 213, 215 and insulating sidewalls 161, 163, 165 disposed on the substrate 110, wherein each insulating sidewall 161, 163, 165 and each plug 211, 213, 215 are alternately disposed on the substrate 110. The plugs 211, 213, 215 physically contact the underlying active regions 131, 133 as storage node plugs (storage node contact, SNC) of the semiconductor memory device 100, and the conductive pads 193, 195 are formed as storage node pads (SN pads) of the semiconductor memory device 100, and are disposed on the storage node plugs and connected to the storage node plugs, respectively. In detail, each third plug 211 is formed by sequentially stacking an epitaxial layer 181 (including a conductive material) and a conductive layer 191 (including a conductive material) together, so as to electrically connect the transistor element in the substrate 110, and further electrically connect the capacitor element by means of a conductive pad 193 thereon, thereby forming a minimum memory cell of the semiconductor memory device 100, and receiving or transmitting a desired signal.

The first plug 213 is composed of sequentially stacked insulating layers 150 (including insulating materials) and conductive layers 192 (including conductive materials), and the second plug 215 is composed entirely of the insulating layers 150 (including insulating materials), wherein two or more of the first plugs 213 simultaneously contact the active region 133 and/or the storage node pad (conductive pad 195), and the second plugs 215 directly contact the shallow trench isolation 120, such that neither the first plugs 213 nor the second plugs 215 can be electrically connected to any of the transistor elements, and simultaneously serve as dummy plugs. In other words, the manufacturing method of the present disclosure is to easily induce micro-loading effect or incomplete etching in the etching process due to the difference of the device density in the memory region 110A and the peripheral region 110B of the semiconductor memory device 100, and more simply form a plurality of dummy storage node plugs in the peripheral region 110B, so that the dummy storage node plugs can be formed without adding additional operation steps, and meanwhile, the manufacturing problem induced by the lower device density in the peripheral region 110B can be improved, and the manufacturing yield of the semiconductor memory device 100 can be improved.

In addition, it should be noted that, each of the insulating sidewalls 161 is disposed above each of the gate structures 140 correspondingly, but the gate structures 140 in the peripheral region 110B have a relatively larger disposing distance (the second distance P2), such that the insulating sidewalls 163 cannot be disposed above the gate structures 140 completely, but can only be disposed on the active region 133 or only partially overlap the underlying gate structures 140. With this arrangement, the process window (process tolerance) or the process window) of the device in the peripheral region 110B can be increased, and the micro-loading effect or etching defects generated by the device density difference during the fabrication process of the device in the peripheral region 110B can be avoided, thereby being beneficial to achieving more optimized structural integrity and device performance.

However, it should be readily understood by those skilled in the art that the semiconductor memory device and the manufacturing process thereof of the present disclosure may have other aspects or may be achieved by other means, and are not limited to the foregoing. Other embodiments or variations of the semiconductor memory device and its fabrication process in the present disclosure are further described below. In order to simplify the description, the following description mainly aims at the differences of the embodiments, and the details of the differences will not be repeated. In addition, like elements in the various embodiments of the present utility model are labeled with like reference numerals to facilitate cross-reference between the various embodiments.

Referring to fig. 9, a schematic diagram of a method for manufacturing a semiconductor memory device 300 according to a second embodiment of the disclosure is shown. The manufacturing steps of the semiconductor memory device 300 in this embodiment are substantially the same as those of the semiconductor memory device 100 in the first embodiment, and will not be repeated here. The main difference between this embodiment and the first embodiment is that in this embodiment, after the epitaxial layer 181 is formed (as shown in fig. 4 in the first embodiment), another etching process, such as a wet etching process, is performed to further remove the insulating layer 150 adjacent to the storage region 110A, so as to expose the underlying dielectric layer 147. Then, the subsequent manufacturing processes are sequentially performed, as shown in fig. 5 to 8 in the first embodiment. Thus, the semiconductor memory device 300 in the second embodiment of the present utility model can be completed.

In particular, in the present embodiment, due to the difference of the assembly degree in the memory region 110A and the peripheral region 110B, when the deposition process (as shown in fig. 5 in the first embodiment) of the conductive material layer 190 is performed, the problem of incomplete hole filling in the peripheral region 110B adjacent to the memory region 110A is likely to occur, and the air gap 310 is formed. Wherein the air gaps 310 may have top surfaces that are not equal to each other, even forming an uneven top surface 310a, as shown in fig. 9. Thus, each conductive layer 192 formed in the peripheral region 110B is stacked on the air gap 310, and the first plug 313 is formed by sequentially stacking the air gap 310 (including the insulating material) and the conductive layer 192 (including the conductive material). However, in another embodiment, plugs (not shown) having sequentially stacked insulating layers 150, air gaps and conductive layers 192 may also be formed in the peripheral region 110B adjacent to the memory region 110A. In this embodiment, two or more first plugs 313 also contact the active region 133 and/or the storage node pad (conductive pad 195) at the same time, but cannot be electrically connected to any of the transistor elements, and serve as dummy plugs. Therefore, the manufacturing method of the present disclosure can also form the dummy storage node plug without adding additional operation steps, and can improve various manufacturing problems in the peripheral region 110B due to the low component density, and improve the manufacturing yield of the semiconductor memory device 300.

Referring to fig. 10, a schematic diagram of a method for manufacturing a semiconductor memory device 400 according to a third embodiment of the disclosure is shown. The manufacturing steps of the semiconductor memory device 400 in this embodiment are substantially the same as those of the semiconductor memory device 100 in the first embodiment, and will not be repeated here. The main difference between this embodiment and the first embodiment is that in this embodiment, the etching process of the insulating layer 150 is performed by covering with another mask layer (not shown) as shown in fig. 4 of the first embodiment, so as to completely remove the insulating layer 150 in the storage region 110A, partially remove the insulating layer 150 on both sides of the insulating sidewall 163, and simultaneously partially remove the insulating layer 150 on both sides of the insulating sidewall 165, and then sequentially perform the subsequent manufacturing processes as shown in fig. 5 to 8 of the first embodiment, thereby forming the epitaxial layer 181 and other components. Thus, the semiconductor memory device 400 according to the third embodiment of the present utility model can be completed.

In particular, in the present embodiment, due to the difference of the assembly degree in the storage area 110A and the peripheral area 110B, the insulating layer 150 is not completely etched by controlling the parameters such as the opening size, the opening pitch, or the etching time, so as to form top surfaces with different heights and uneven etching surfaces 350A, as shown in fig. 10. Thus, the conductive layers 492 subsequently formed in the peripheral region 110B are stacked on the etched surface 350a of the insulating layer 150, and the sequentially stacked insulating layer 150 (including insulating material) and the conductive layers 492 (including conductive material) together form a plurality of second plugs 415 directly contacting the underlying shallow trench isolation 120. In addition, two or more second plugs 415 may also contact the storage node pads at the same time, and cannot be electrically connected to any component, and are used as dummy plugs, as shown in fig. 10. Therefore, the manufacturing method of the present disclosure can also form the dummy storage node plug without adding additional operation steps, and can improve various manufacturing problems in the peripheral region 110B due to the low component density, and improve the manufacturing yield of the semiconductor memory device 400.

In the semiconductor memory device of the present utility model, the plurality of storage node plugs and the dummy storage node plugs are respectively disposed in the dense region and the loose region having larger component density difference, so that the same luminous flux can be maintained in each region during the photolithography process, thereby being beneficial to improving the manufacturing yield of the semiconductor memory device. Meanwhile, the manufacturing process of the dummy storage node plug is easy to cause micro-loading effect or incomplete etching and other manufacturing problems in the etching manufacturing process due to the component density difference between the dense region and the loose region, so that the dummy storage node plug can be formed on the premise of not adding extra operation steps. Therefore, the manufacturing method of the semiconductor memory device can form the semiconductor memory device with better component reliability, so that the semiconductor memory device can achieve more optimized device performance.

The above description is only of the preferred embodiments of the present utility model and is not intended to limit the present utility model, but various modifications and variations can be made to the present utility model by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present utility model should be included in the protection scope of the present utility model.

Claims (18)

1. A semiconductor memory device characterized by comprising:

a substrate, wherein the substrate comprises a plurality of active areas isolated from the shallow trenches;

a plurality of buried word lines buried within the substrate, through the shallow trench isolation or the active region;

the storage node plugs are arranged on the substrate and contact the active area, and each storage node plug comprises a plurality of first plugs, wherein each first plug comprises an insulating material and a conductive material which are sequentially stacked from bottom to top; and

and a plurality of storage node pads disposed on the storage node plugs, one of the storage node pads being in physical contact with at least two of the first plugs at the same time.

2. The semiconductor memory device according to claim 1, wherein the first plug partially overlaps the buried word line in a direction perpendicular to the substrate.

3. The semiconductor memory device according to claim 1, wherein the insulating material comprises silicon oxide or air.

4. The semiconductor memory device according to claim 1, wherein the insulating material provided in the first plug has top surfaces that are different from each other in height.

5. The semiconductor memory device according to claim 1, wherein the insulating material in each of the first plugs has an uneven etched surface.

6. The semiconductor memory device according to claim 1, further comprising: and a plurality of insulating sidewalls disposed on the substrate and alternately disposed with the storage node plugs.

7. The semiconductor memory device of claim 6, wherein the insulating sidewall extends into a portion of the shallow trench isolation and has bottom surfaces that are not equal to each other.

8. The semiconductor memory device according to claim 6, wherein each of the insulating sidewalls is spaced apart from each other and has a same third pitch, each of the buried word lines is spaced apart from each other and has a first pitch and a second pitch, the third pitch is equal to the first pitch, and the second pitch is greater than the first pitch.

9. The semiconductor memory device according to claim 1, wherein the storage node plug further comprises a plurality of second plugs, each of the second plugs comprising an insulating material and a conductive material stacked sequentially from bottom to top and directly contacting the shallow trench isolation, wherein the insulating materials in the second plugs have top surfaces different from each other.

10. The semiconductor memory device according to claim 1, wherein at least one of the active regions contacts both of the first plugs simultaneously.

11. A semiconductor memory device characterized by comprising:

a substrate, wherein the substrate comprises a plurality of active areas isolated from the shallow trenches;

a plurality of buried word lines buried within the substrate, through the shallow trench isolation or the active region; and

the storage node plugs are arranged on the substrate and contact the active area, each storage node plug comprises a plurality of first plugs, each first plug comprises an insulating material and a conductive material which are sequentially stacked from bottom to top, and at least one active area simultaneously contacts two first plugs.

12. The semiconductor memory device according to claim 11, wherein the at least one active region is circumferentially disposed outside the remaining active regions.

13. The semiconductor memory device according to claim 11, wherein the storage node plug further comprises a plurality of second plugs, each of the second plugs comprising an insulating material and a conductive material stacked sequentially from bottom to top and directly contacting the shallow trench isolation, wherein the insulating materials in the second plugs have top surfaces different from each other.

14. The semiconductor memory device according to claim 11, wherein the first plug partially overlaps the buried word line in a direction perpendicular to the substrate.

15. The semiconductor memory device according to claim 11, wherein the insulating material in the first plug has top surfaces different from each other in height, and the insulating material comprises silicon oxide or air.

16. The semiconductor memory device according to claim 11, further comprising: and a plurality of insulating sidewalls disposed on the substrate and alternately disposed with the storage node plugs.

17. The semiconductor memory device of claim 16, wherein a top surface of the insulating sidewall is flush with a top surface of the conductive material of each of the first plugs.

18. The semiconductor memory device of claim 16, wherein the insulating sidewall extends into a portion of the shallow trench isolation and has bottom surfaces that are not equal to each other.

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