KR20240103367A - Gate Driving Circuit and Display Device including the same - Google Patents

Abstract

This embodiment includes a display panel that displays an image; a data driver that supplies data voltage to the display panel; and a gate driver including an N-th scan signal generator for supplying an N-th scan signal to the display panel and an N-th light-emitting signal generator for supplying an N-th light-emitting signal to the display panel, wherein the gate driver includes the first scan signal. It is connected to the input terminal of the N light emitting signal generator and includes an external signal line for transmitting an external signal and a control clock signal line for transmitting a control clock signal, and the N light emitting signal generator is generated based on the external signal and the control clock signal. A display device that generates an Nth clear signal for initializing at least one of the nodes can be provided.

Description

Gate driving circuit and display device including the same}

This specification relates to a gate driving circuit and a display device including the same.

As information technology develops, the market for display devices, which are a connecting medium between users and information, is growing. Accordingly, the use of display devices such as Light Emitting Display Device (LED), Quantum Dot Display Device (QDD), and Liquid Crystal Display Device (LCD) is increasing.

The display devices described above include a display panel including subpixels, a driver that outputs a driving signal to drive the display panel, and a power supply that generates power to be supplied to the display panel or the driver.

The above display devices can display images by transmitting light or directly emitting light through the selected subpixels when driving signals, such as scan signals and data signals, are supplied to the subpixels formed on the display panel.

This embodiment improves the driving reliability and driving stability of the display device based on a gate signal generating circuit having a light emitting signal generating unit capable of sequential initialization for each stage.

This embodiment includes a display panel that displays an image; a data driver that supplies data voltage to the display panel; and a gate driver including an N-th scan signal generator for supplying an N-th scan signal to the display panel and an N-th light-emitting signal generator for supplying an N-th light-emitting signal to the display panel, wherein the gate driver includes the first scan signal. It is connected to the input terminal of the N light emitting signal generator and includes an external signal line for transmitting an external signal and a control clock signal line for transmitting a control clock signal, and the N light emitting signal generator is generated based on the external signal and the control clock signal. A display device that generates an Nth clear signal to initialize at least one of the nodes can be provided.

The gate driver may initialize at least one of the nodes of the N-th light-emitting signal generator based on the N-th clear signal during a clear period of the N-th light-emitting signal generator in which the N-th light-emitting signal is not output.

The N-th light-emitting signal generator alternately controls the Q2 node and the Qb2 node to generate the N-th light-emitting signal, and includes a light-emitting node control circuit unit that controls a net node for controlling the Qb2 node, the Q2 node, and the It may include a light-emitting signal output unit that outputs the N-th light-emitting signal through an N-th light-emitting signal output terminal of the N-th light-emitting signal generator in response to the potential of the Qb2 node and the net node.

The Nth light emitting signal generator includes a clear signal generator that generates the Nth clear signal based on the external signal and the control clock signal, and the clear signal generator operates based on the control clock signal and generates the external signal. A first signal generation transistor that transmits, a second signal generation transistor that operates in response to the external signal transmitted from the first signal generation transistor and generates the clear signal based on a high voltage, and an N+1 light emitting signal It may include a third signal generation transistor that changes the voltage state of the clear signal based on the signal transmitted from the generator.

The N-th light-emitting signal generator includes a clear circuit unit that initializes at least one of the nodes of the N-th light-emitting signal generator based on the N-th clear signal, and the clear circuit unit initializes the Q2 based on the N-th clear signal. It may include a first clear transistor for initializing a node, a second clear transistor for initializing the net node, and a third clear transistor for initializing the Nth light emitting signal output terminal.

The clear circuit unit may simultaneously initialize the Q2 node, the net node, and the Nth light emitting signal output terminal based on the Nth clear signal.

The first signal generation transistor has a gate electrode connected to the control clock signal line, a first electrode connected to the external signal line, and a second electrode connected to the Clear Q node. A gate electrode is connected to the node, a first electrode is connected to the high voltage line, a second electrode is connected to the output terminal of the clear signal generator, and the third signal generating transistor emits an N+i (i is an integer greater than 1) light signal. A gate electrode may be connected to the output terminal of the N+i-th clear signal generator of the generator, a first electrode may be connected to the output terminal of the clear signal generator, and a second electrode may be connected to the low voltage line.

The first clear transistor has a gate electrode connected to the output terminal of the clear signal generator, a first electrode connected to the Q2 node, and a second electrode connected to a low voltage line, and the second clear transistor is connected to the output terminal of the clear signal generator. A gate electrode is connected to the net node, a first electrode is connected to the net node, a second electrode is connected to the low voltage line, and the third clear transistor has a gate electrode connected to the output terminal of the clear signal generator and the Nth light emitting signal. A first electrode may be connected to the output terminal, and a second electrode may be connected to a low voltage line having a different level from the low voltage line.

From another aspect, this embodiment includes a scan node control circuit that alternately controls the Q1 node and the Qb1 node, and an Nth scan signal generator that outputs the Nth scan signal in response to potentials of the Q1 node and the Qb1 node. A light emitting node control circuit unit that alternately controls the Q2 node and the Qb2 node and controls a net node for controlling the Qb2 node, and generates an Nth light emitting signal in response to the potentials of the Q2 node, the Qb2 node, and the net node. An N-th light emitting signal generator that outputs; And it is connected to the input terminal of the Nth light emitting signal generator and includes an external signal line for transmitting an external signal and a control clock signal line for transmitting a control clock signal, wherein the Nth light emitting signal generator transmits the external signal and the control clock signal. Based on , it is possible to provide a gate driving circuit that generates an Nth clear signal for initializing at least one of the nodes of the Nth light emitting signal generator.

The N-th light-emitting signal generator may initialize at least one of the nodes of the N-th light-emitting signal generator based on the N-th clear signal during a clear section of the N-th light-emitting signal generator in which the N-th light-emitting signal is not output. .

The Nth light emitting signal generator includes a clear signal generator that generates the Nth clear signal based on the external signal and the control clock signal, and the clear signal generator operates based on the control clock signal and generates the external signal. A first signal generation transistor that transmits, a second signal generation transistor that operates in response to the external signal transmitted from the first signal generation transistor and generates the clear signal based on a high voltage, and an N+1 light emitting signal It may include a third signal generation transistor that changes the voltage state of the clear signal based on the signal transmitted from the generator.

The N-th light-emitting signal generator includes a clear circuit unit that initializes at least one of the nodes of the N-th light-emitting signal generator based on the N-th clear signal, and the clear circuit unit initializes the Q2 based on the N-th clear signal. It may include a first clear transistor for initializing a node, a second clear transistor for initializing the net node, and a third clear transistor for initializing the Nth light emitting signal output terminal.

This embodiment is a display device based on a gate signal generation circuit having a light emitting signal generator capable of sequential initialization for each stage by applying a self-generated clear signal to its nodes and applying it to dependently connected stages. It has the effect of improving driving reliability and driving stability.

FIG. 1 is a block diagram schematically showing a light emitting display device, and FIG. 2 is a block diagram schematically showing the subpixel shown in FIG. 1.
Figures 3 and 4 are diagrams for explaining the configuration of a gate-in-panel type gate driver, and Figure 5 is a diagram showing an example of the arrangement of a gate-in-panel type gate driver.
FIG. 6 is a block diagram schematically showing a subpixel according to the first embodiment, FIG. 7 is a block diagram schematically showing a shift register according to the first embodiment, and FIG. 8 is a block diagram schematically showing a subpixel according to the first embodiment. This is a block diagram showing part of the illustrated shift register.
FIG. 9 is a circuit diagram showing the N-th light-emitting signal generator according to the first embodiment, FIG. 10 is a diagram showing a portion of the driving waveform of the N-th light-emitting signal generator according to the first embodiment, and FIG. 11 is FIG. This is a diagram to explain the initialization operation of the Nth light emitting signal generator according to the driving waveform.
FIG. 12 is a circuit diagram showing in more detail the circuit included in the N-th light-emitting signal generator according to the second embodiment, and FIG. 13 is a diagram showing a portion of the driving waveform of the N-th light-emitting signal generator according to the second embodiment. , and FIG. 14 is a diagram for explaining the initialization operation of the Nth light emitting signal generator according to the driving waveform of FIG. 13.
Figure 15 is a diagram showing the change in clear signal generation according to the variation of the clear input signal applied to the Nth light emitting signal generator according to the second embodiment, and Figures 16 and 17 are diagrams showing the change in clear signal generation according to the second embodiment. These are simulation results showing the signals and the initialization of the Nth light emitting signal generator using them.

The display device according to this embodiment can be implemented as a television, video player, personal computer (PC), home theater, automobile electric device, smartphone, etc., but is not limited thereto. The display device according to the present invention may be implemented as a light emitting display device (LED), a quantum dot display device (QDD), a liquid crystal display device (LCD), etc. However, hereinafter, for convenience of explanation, a light emitting display device that directly emits light based on an inorganic light emitting diode or an organic light emitting diode is taken as an example.

In addition, the thin film transistor described below may be implemented as an n-type thin film transistor, a p-type thin film transistor, or a combination of n-type and p-type. A thin film transistor is a three-electrode device including a gate, source, and drain. The source is an electrode that supplies carriers to the transistor. Within a thin film transistor, carriers begin to flow from a source. The drain is the electrode through which carriers go out in a thin film transistor. That is, in a thin film transistor, carriers flow from the source to the drain.

In the case of a p-type thin film transistor, since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-type thin film transistor, current flows from the source to the drain because holes flow from the source to the drain. On the other hand, in the case of an n-type thin film transistor, since the carriers are electrons, the source voltage has a lower voltage than the drain voltage so that electrons can flow from the source to the drain. In an n-type thin film transistor, since electrons flow from the source to the drain, the direction of current flows from the drain to the source. However, the source and drain of a thin film transistor can change depending on the applied voltage. Reflecting this, in the following description, one of the source and drain will be described as the first electrode, and the other one of the source and drain will be described as the second electrode.

FIG. 1 is a block diagram schematically showing a light emitting display device, and FIG. 2 is a block diagram schematically showing the subpixel shown in FIG. 1.

As shown in Figures 1 and 2, the light emitting display device includes an image supply unit 110, a timing control unit 120, a gate driver (gate driving circuit) 130, a data driver (data driving circuit) 140, and a display unit. It may include a panel 150 and a power supply unit 180.

The image supply unit (set or host system) 110 can output various driving signals in addition to image data signals supplied from outside or image data signals (image data signals) stored in internal memory. The image supply unit 110 may supply data signals and various driving signals to the timing control unit 120.

The timing control unit 120 includes a gate timing control signal (GDC) for controlling the operation timing of the gate driver 130, a data timing control signal (DDC) for controlling the operation timing of the data driver 140, and various synchronization signals ( The vertical synchronization signal (VSYNC) and the horizontal synchronization signal (HSYNC) can be output. The timing control unit 120 may supply the data signal DATA supplied from the image supply unit 110 together with the data timing control signal DDC to the data driver 140. The timing control unit 120 may be formed in the form of an integrated circuit (IC) and mounted on a printed circuit board, but is not limited to this.

The gate driver 130 may output a gate signal (or gate voltage) in response to a gate timing control signal (GDC) supplied from the timing control unit 120. The gate driver 130 may supply a gate signal to subpixels included in the display panel 150 through the gate lines GL1 to GLm. The gate driver 130 may be formed in the form of an IC or directly on the display panel 150 using a gate in panel method, but is not limited thereto.

The data driver 140 samples and latches the data signal (DATA) in response to the data timing control signal (DDC) supplied from the timing control unit 120 and converts the digital data signal into analog data based on the gamma reference voltage. It can be converted to voltage and output. The data driver 140 may supply a data voltage to subpixels included in the display panel 150 through the data lines DL1 to DLn. The data driver 140 may be formed in the form of an IC and mounted on the display panel 150 or on a printed circuit board, but is not limited thereto.

The power supply unit 180 generates a high potential voltage and a low potential voltage based on an external input voltage supplied from the outside, and can output them through a high potential power line (EVDD) and a low potential power line (EVSS). The power supply unit 180 may generate and output not only a high potential voltage and a low potential voltage, but also a voltage necessary to drive the gate driver 130 or a voltage necessary to drive the data driver 140.

The display panel 150 can display an image in response to a driving signal including a gate signal and a data voltage, and a driving voltage including a high potential voltage and a low potential voltage. Subpixels of the display panel 150 directly emit light. The display panel 150 may be manufactured based on a rigid or flexible substrate such as glass, silicon, or polyimide. And the subpixels that emit light may be composed of pixels containing red, green, and blue, or pixels containing red, green, blue, and white.

For example, one subpixel (SP) may be connected to the first data line (DL1), the first gate line (GL1), the high potential power line (EVDD), and the low potential power line (EVSS), and a switching transistor, driving It may include a pixel circuit made of transistors, capacitors, organic light emitting diodes, etc. Sub-pixels (SP) used in light-emitting displays directly emit light, so the circuit configuration is complex. In addition, there are various compensation circuits that compensate for the deterioration of not only the organic light-emitting diode that emits light, but also the driving transistor that supplies the driving current required to drive the organic light-emitting diode. Therefore, please refer to the fact that the subpixel SP is simply shown in the form of a block.

Meanwhile, in the above description, the timing control unit 120, gate driver 130, data driver 140, etc. were described as if they were individual components. However, depending on the implementation method of the light emitting display device, one or more of the timing control unit 120, gate driver 130, and data driver 140 may be integrated into one IC.

Figures 3 and 4 are diagrams for explaining the configuration of a gate-in-panel type gate driver, and Figure 5 is a diagram showing an example of the arrangement of a gate-in-panel type gate driver.

As shown in FIG. 3, the gate-in-panel type gate driver 130 may include a shift register 131 and a level shifter 135. The level shifter 135 may generate clock signals Clks and a start signal Vst based on signals and voltages output from the timing control unit 120 and the power supply unit 180. The shift register 131 operates based on the clock signals (Clks) and the start signal (Vst) output from the level shifter 135 and can output gate signals (Gout[1] to Gout[m]). there is.

As shown in Figures 3 and 4, unlike the shift register 131, the level shifter 135 may be formed independently in the form of an IC or may be included inside the power supply unit 180. However, this is only an example and is not limited to this.

As shown in FIG. 5, the first and second shift registers 131a and 131b that output gate signals from the gate-in-panel type gate driver may be disposed in the non-display area (NA) of the display panel 150. . The first and second shift registers 131a and 131b may be formed in a thin film form on the display panel 150 using a gate-in-panel method. The first and second shift registers 131a and 131b are shown as an example of being disposed in the left and right non-display areas (NA) of the display panel 150, but the present invention is not limited thereto.

FIG. 6 is a block diagram schematically showing a subpixel according to the first embodiment, FIG. 7 is a block diagram schematically showing a shift register according to the first embodiment, and FIG. 8 is a block diagram schematically showing a subpixel according to the first embodiment. This is a block diagram showing part of the illustrated shift register.

As shown in FIG. 6, the subpixel SP according to the first embodiment includes a first gate line (GL1), a first data line (DL1), a high potential power line (EVDD), and a low potential power line (EVSS). ) can be connected to. The first gate line GL1 may include a scan signal line GL1a and a light emission signal line GL1b. The scan signal line GL1a and the light emission signal line GL1b may be arranged on the same horizontal line. The subpixel according to the first embodiment may operate based on a scan signal applied through the scan signal line GL1a and a light emission signal applied through the light emission signal line GL1b.

As shown in FIG. 7, the shift register 131a according to the first embodiment includes scan signal generators that output scan signals to drive the display panel including the subpixel SP shown in FIG. 6. It may include SCG[1] ~ SCG[m]) and light emitting signal generators (EMG[1] ~ EMG[m]) that output light emitting signals.

The shift register 131a may be composed of stages (STG1 to STGm) that are dependently connected to sequentially output scan signals and light emitting signals through the gate lines (GL1 to GLm), which are as follows.

As shown in FIG. 8, the scan signal generators (SCG[1] to SCG[2]) include a first clock signal line (CLKS1), a first high voltage line (GVDD), a first low voltage line (GVSS0), It can be connected to the second low voltage line (GVSS1), the third low voltage line (GVSS2), and the first start signal line (GVST). The scan signal generators (SCG[1] to SCG[2]) include a first clock signal line (CLKS1), a first high voltage line (GVDD), a first low voltage line (GVSS0), a second low voltage line (GVSS1), It can operate based on various signals and voltages applied through the third low voltage line (GVSS2) and the first start signal line (GVST).

The light emitting signal generators (EMG[1] ~ EMG[2]) include the second clock signal line (CLKS2), the second high voltage line (GVDD0), the third high voltage line (GVDD1), the first low voltage line (GVSS0), It can be connected to the third low voltage line (GVSS2), the external signal line (CLR_IN), and the second start signal line (EVST). The light emitting signal generators (EMG[1] ~ EMG[2]) include the second clock signal line (CLKS2), the second high voltage line (GVDD0), the third high voltage line (GVDD1), the first low voltage line (GVSS0), It can operate based on various signals and voltages applied through the third low voltage line (GVSS2) and the second start signal line (EVST).

The high voltages applied through the high voltage lines connected to the scan signal generators (SCG[1] ~ SCG[2]) and the light emitting signal generators (EMG[1] ~ EMG[2]) have the same level or are not suitable for purpose and effect. One or more may be different depending on the situation. In addition, the low voltages applied through the low voltage lines connected to the scan signal generators (SCG[1] ~ SCG[2]) and the light emitting signal generators (EMG[1] ~ EMG[2]) have the same level or have the same purpose and Depending on the effect, there may be one or more differences.

A first scan signal generator (SCG[1]) and a first emission signal generator (EMG[1]) may be located in the first stage (STG1). A second scan signal generator (SCG[2]) and a second light emitting signal generator (EMG[2]) may be located in the second stage (STG2).

The first scan signal generator (SCG[1]) may output the first scan signal through the first scan signal line (GL1a), and the first light emission signal generator (EMG[1]) may output the first light emission signal. The first light emission signal can be output through the line GL1b. The second scan signal generator (SCG[2]) may output the second scan signal through the second scan signal line (GL2a), and the second light emission signal generator (EMG[2]) may output the second light emission signal. A second light emitting signal can be output through the line GL2b.

The first light emitting signal generator (EMG[1]) can receive a clear signal from the outside as an input through the external signal line (CLR_IN), and can initialize at least one of its nodes based on this. The second light-emitting signal generator (EMG[2]) can receive as input a signal formed in a circuit that initializes at least one of the nodes in the first light-emitting signal generator (EMG[1]), and based on this, its At least one of the nodes can be initialized.

The above connection and operation relationship can also be applied to the light emitting signal generators of all stages included in the shift register 131a. Hereinafter, the embodiment will be described in more detail, taking the N-th light emitting signal generator located in the N-th stage as an example.

FIG. 9 is a circuit diagram showing the N-th light-emitting signal generator according to the first embodiment, FIG. 10 is a diagram showing a portion of the driving waveform of the N-th light-emitting signal generator according to the first embodiment, and FIG. 11 is FIG. This is a diagram to explain the initialization operation of the Nth light emitting signal generator according to the driving waveform.

As shown in FIG. 9, the Nth emission signal generator (EMG[n]) includes a first emission node control circuit unit (ENC1), a first emission carry signal output unit (E6cr, E7cr), and a first emission signal output unit. (E6, C2, E7), a first clear signal generation unit (CLRC), and a first clear circuit unit (CLC).

The first light emitting node control circuit unit (ENC1) operates based on various signals and voltages applied through the first high voltage line (GVDD), the third low voltage line (GVSS2), and the second start signal line (EVST). , charging and discharging of the Q2 node (Q2) and Qb2 node (Qb2) can be controlled. The Q2 node (Q2) of the first light-emitting node control circuit (ENC1) is connected to the second start signal applied through the second start signal line (EVST) or the N-1th light-emitting carry signal output terminal of the N-1th light-emitting signal generator ( It can be controlled by the N-1th light-emitting carry signal output from (CC[n-1]).

Meanwhile, Figure 9 shows an example in which the second start signal line (EVST) is connected to the N-th emission signal generator (EMG[n]). However, the second start signal line (EVST) can be applied to the light emitting signal generator located in the first stage, and the light emitting signal generator located in the remaining stages can receive the previous light emitting carry signal as the second start signal. .

The first light emitting signal output unit (E6, C2, E7) may include a 1-1 control pull-up transistor (E6), a second capacitor (C2), and a 1-1 control pull-down transistor (E7). The first light emission signal output unit (E6, C2, E7) outputs the Nth light emission signal through the Nth light emission signal output terminal (EO[n]) according to the potential of the Q2 node (Q2) and Qb2 node (Qb2) that operate alternately. Can be printed.

When the 1-1 control pull-up transistor (E6) is turned on by the potential of the Q2 node (Q2), bootstrapping occurs by the second capacitor (C2) and the second high voltage applied through the second high voltage line (GVDD0) Based on this, the Nth light emitting signal of high voltage can be output. When the 1-1st control pull-down transistor (E7) is turned on by the potential of the Qb2 node (Qb2), the Nth light emitting signal of low voltage is output based on the first low voltage applied through the first low voltage line (GVSS0). It can be.

The first light-emitting carry signal output unit (E6cr, E7cr) may include a 1-2 control pull-up transistor (E6cr) and a 1-2 control pull-down transistor (E7cr). The first light-emitting carry signal output unit (E6cr, E7cr) outputs the Nth light-emitting carry signal through the Nth light-emitting carry signal output terminal (CC[n]) according to the potential of the Q2 node (Q2) and Qb2 node (Qb2) that operate alternately. can be output.

When the 1-2 control pull-up transistor (E6cr) is turned on by the potential of the Q2 node (Q2), the Nth light-emitting carry signal of high voltage is generated based on the third high voltage applied through the third high voltage line (GVDD1). can be printed. When the 1-2 control pull-down transistor (E7cr) is turned on by the potential of the Qb2 node (Qb2), the Nth light-emitting carry signal of low voltage is generated based on the 3rd low voltage applied through the 3rd low voltage line (GVSS2). can be printed.

The first clear signal generator (CLRC) receives an external signal (CLR_in) applied from the outside or an N-1 clear signal (CLR[n-) output from the N-1 clear signal generator of the N-1 light emitting signal generator. 1]). The first clear signal generation unit (CLRC) may include a first signal generation transistor (Eclr1), a second signal generation transistor (Eclr2), and a third signal generation transistor (Eclr3). The first signal generation transistor (Eclr1), the second signal generation transistor (Eclr2), and the third signal generation transistor (Eclr3) operate based on the external signal (CLR_in) and control clock signal (ECLK) and the Nth clear signal (CLR). [n]) can be output.

The first clear circuit unit (CLC) is configured to operate at least one of the nodes of the Nth light emitting signal generator (EMG[n]) based on the Nth clear signal (CLR[n]) output from the first clear signal generator (CLRC). You can initialize one. The first clear circuit unit (CLC) may include a first clear transistor (Eclrq), a second clear transistor (Eclrn), and a third clear transistor (Eclro). The first clear transistor (Eclrq), the second clear transistor (Eclrn), and the third clear transistor (Eclro) operate based on the Nth clear signal (CLR[n]) output from the first clear signal generator (CLRC). can do.

As shown in Figures 10 and 11, the Nth light emitting signal generator (EMG[n]) operates based on the external signal (CLR_in) and the control clock signal (Eclk) applied from the outside and generates the Nth clear signal ( CLR[n]) can be output.

The first clear signal generator (CLRC) may operate when the control clock signal (Eclk) of the high voltage (H) is input after the external signal (CLR_in) of the high voltage (H) is input. In contrast, if the control clock signal (Eclk) of the high voltage (H) or the control clock signal (Eclk) of the low voltage (L) is input after the external signal (CLR_in) of the low voltage (L) is input, it does not operate. It may not be possible.

When the control clock signal (Eclk) of the high voltage (H) is input after the external signal (CLR_in) of the high voltage (H) is input, the first signal generation transistor (Eclr1) and the second signal generation transistor (Eclr2) It can be turned on. In this case, the Clear Q node (CLR_Q) is charged with high voltage (H) by the external signal (CLR_in) of high voltage (H), and is charged with high voltage (H) based on the high voltage applied through the high voltage line (GVDD1). The Nth clear signal (CLR[n]) may be output.

The third signal generation transistor (Eclr3) receives the N+i clear signal (CLR[n+i]) output from the output terminal of the N+i clear signal generator of the N+i (i is an integer greater than 1) light emitting signal generator. It operates based on and can control the high voltage (H) external signal (CLR_in) with the low voltage (L) external signal (CLR_in) (discharge control to change the voltage state). When the external signal (CLR_in) of the low voltage (L) occurs, the first clear transistor (Eclrq), the second clear transistor (Eclrn), and the third clear transistor (Eclro) included in the first clear circuit unit (CLC) are simultaneously activated. It can be turned off.

The first clear circuit unit (CLC) may not operate when the Nth clear signal (CLR[n]) of the low voltage (L) is input, and the Nth clear signal (CLR[n]) of the high voltage (H) may not be operated. ) is entered, it can operate. When the Nth clear signal (CLR[n]) of the high voltage (H) is input, the first clear transistor (Eclrq), the second clear transistor (Eclrn), and the third clear transistor ( Eclro) can be turned on at the same time.

When the first clear transistor (Eclrq) is turned on, the Q2 node (Q2) of the Nth light emitting signal generator (EMG[n]) can be initialized, and when the second clear transistor (Eclrn) is turned on, the Nth light emitting signal generator (EMG[n]) can be initialized. The net node (NET) of (EMG[n]) can be initialized, and when the third clear transistor (Eclro) is turned on, the Nth light emitting signal output terminal (EO[n]) of the Nth light emitting signal generator (EMG[n]) can be initialized. ]) can be initialized. That is, the Q2 node (Q2), the net node (NET), and the Nth light emitting signal output terminal (EO[n]) of the Nth light emitting signal generator (EMG[n]) can be initialized simultaneously.

Meanwhile, the initialization of the nodes included in the N-th light-emitting signal generator (EMG[n]) is performed so that the N-th light-emitting signal generator (EMG[n]) generates a valid light-emitting signal (on voltage for turning on the light-emitting control transistor of the display panel). This can be done during non-driving time when the light emitting signal) is not output. In addition, the third signal generation transistor (Eclr3 of the last stage) included in the light emitting signal generator located in the last stage among the light emitting signal generators can be turned on by a separate clear reset signal (CLR_reset) input from the outside. .

Note that the first clear signal generator (CLRC) and the first clear circuit portion (CLC) can be applied to various types of light emitting signal generators. Hereinafter, to facilitate understanding of the embodiment, the second embodiment will be described based on an example of a circuit included in the first light emitting node control circuit unit ENC1 of the Nth light emitting signal generator EMG[n].

FIG. 12 is a circuit diagram showing in more detail the circuit included in the N-th light-emitting signal generator according to the second embodiment, and FIG. 13 is a diagram showing a portion of the driving waveform of the N-th light-emitting signal generator according to the second embodiment. , and FIG. 14 is a diagram for explaining the initialization operation of the Nth light emitting signal generator according to the driving waveform of FIG. 13.

As shown in FIG. 12, the Nth emission signal generator (EMG[n]) includes a first emission node control circuit unit (ENC1), a first emission carry signal output unit (E6cr, E7cr), and a first emission signal output unit. (E6, C2, E7), a first clear signal generation unit (CLRC), and a first clear circuit unit (CLC).

The first light emitting node control circuit unit (ENC1) includes a 1-1 control transistor (E1), a 1-2 control transistor (E1A), a 3-1 control transistor (E3q), a 4-1 control transistor (E4), It may include a 4-2 control transistor (E41), a 4-3 control transistor (E4q), a 5-1 control transistor (E5q), and a fourth capacitor (C4).

The 1-1 control transistor (E1) has its gate electrode connected to the control clock signal line (ECLK) and the first light-emitting carry signal output terminal (CC[n-1]) of the N-1 light-emitting signal generator. The electrodes may be connected and the second electrode may be connected to the Qh2 node (Qh2). The 1-1st control transistor (E1) operates based on the control clock signal and can transmit the N-1th light-emitting carry signal to the Qh2 node (Qh2).

The 1-2 control transistor E1A may have a gate electrode connected to the control clock signal line ECLK, a first electrode connected to the Qh2 node (Qh2), and a second electrode connected to the Q2 node (Q2). The 1-2 control transistor (E1A) operates based on the control clock signal and can control the Q2 node (Q2) and the Qh2 node (Qh2).

The 3-1st control transistor E3q may have a gate electrode connected to the Q2 node (Q2), a first electrode connected to the third high voltage line (GVDD1), and a second electrode connected to the Qh2 node (Qh2). The 3-1st control transistor (E3q) operates based on the potential of the Q2 node (Q2) and can transmit the third high voltage to the Qh2 node (Qh2).

The 4-1 control transistor (E4) has a gate electrode connected to the net node (NET) and the first electrode of the fourth capacitor (C4), a first electrode connected to the third high voltage line (GVDD1), and a Qb2 node (Qb2). ) The second electrode may be connected to. The 4-1 control transistor (E4) operates based on the potential of the net node (NET) and can transmit the third high voltage to the Qb2 node (Qb2).

The 4-2 control transistor (E41) has a gate electrode connected to the Qb2 node (Qb2[n-1]) of the N-1 light emitting signal generator, a first electrode connected to the third high voltage line (GVDD1), and a fourth -3 The second electrode may be connected to the first electrode of the control transistor E4q. The 4-2 control transistor (E41) operates based on the potential of the Qb2 node (Qb2[n-1]) of the N-1 light emitting signal generator and is connected to the first electrode of the 4-3 control transistor (E4q). 3Can transmit high voltage.

The 4-3 control transistor (E4q) has a gate electrode connected to the Qh2 node (Qh2), a first electrode connected to the second electrode of the 4-2 control transistor (E41), and a second electrode connected to the Qb2 node (Qb2). This can be connected. The 4-3 control transistor (E4q) operates based on the potential of the Qh2 node (Qh2) and can control the Qb2 node (Qb2) with the voltage transmitted from the 4-2 control transistor (E41).

The 5-1 control transistor E5q may have a gate electrode connected to the Qh2 node (Qh2), a first electrode connected to the Qb2 node (Qb2), and a second electrode connected to the third low voltage line (GVSS2). The 5-1st control transistor (E5q) operates based on the potential of the Qh2 node (Qh2) and can control the Qb2 node (Qb2) with the third low voltage.

The first light emitting signal output unit (E6, C2, E7) may include a 1-1 control pull-up transistor (E6), a second capacitor (C2), and a 1-1 control pull-down transistor (E7). The first light emission signal output unit (E6, C2, E7) outputs the Nth light emission signal through the Nth light emission signal output terminal (EO[n]) according to the potential of the Q2 node (Q2) and Qb2 node (Qb2) that operate alternately. Can be printed.

The 1-1 control pull-up transistor (E6) has a gate electrode connected to the Q2 node (Q2) and the first electrode of the second capacitor (C2), a first electrode connected to the second high voltage line (GVDD0), and emits N light. The second electrode may be connected to the Nth light emitting signal output terminal (EO[n]) of the signal generator (EMG[n]). The 1-1st control pull-up transistor (E6) operates based on the potential of the Q2 node (Q2) and can output the second high voltage as the Nth light emitting signal of high voltage.

The 1-1 control pull-down transistor (E7) has its gate electrode connected to the Qb2 node (Qb2) and its first electrode connected to the N-th light-emitting signal output terminal (EO[n]) of the N-th light-emitting signal generator (EMG[n]). This connection can be made, and the second electrode can be connected to the first low voltage line (GVSS0). The 1-1st control pull-down transistor (E7) operates based on the potential of the Qb2 node (Qb2) and can output the first low voltage as the Nth light emitting signal of low voltage.

The first light-emitting carry signal output unit (E6cr, E7cr) may include a 1-2 control pull-up transistor (E6cr) and a 1-2 control pull-down transistor (E7cr). The first light-emitting carry signal output unit (E6cr, E7cr) outputs the Nth light-emitting carry signal through the Nth light-emitting carry signal output terminal (CC[n]) according to the potential of the Q2 node (Q2) and Qb2 node (Qb2) that operate alternately. can be output.

The 1-2 control pull-up transistor (E6cr) has its gate electrode connected to the Q2 node (Q2), its first electrode connected to the third high voltage line (GVDD1), and the first electrode of the N-th light emitting signal generator (EMG[n]). The second electrode may be connected to the N light-emitting carry signal output terminal (CC[n]). The 1-2 control pull-up transistor (E6cr) operates based on the potential of the Q2 node (Q2) and can output the third high voltage as the Nth light-emitting carry signal of high voltage.

The 1-2 control pull-down transistor (E7cr) has its gate electrode connected to the Qb2 node (Qb2) and the first light-emitting carry signal output terminal (CC[n]) of the N-th emitting signal generator (EMG[n]). The electrode may be connected and the second electrode may be connected to the first low voltage line (GVSS0). The first-second control pull-down transistor (E7cr) operates based on the potential of the Qb2 node (Qb2) and can output the first low voltage as the Nth light-emitting carry signal of low voltage.

The first clear signal generation unit (CLRC) may include a first signal generation transistor (Eclr1), a second signal generation transistor (Eclr2), and a third signal generation transistor (Eclr3). The first signal generation transistor (Eclr1), the second signal generation transistor (Eclr2), and the third signal generation transistor (Eclr3) operate based on the external signal (CLR_in) and the control clock signal, and the Nth clear signal (CLR[n]) ) can be output.

The first signal generation transistor (Eclr1) has its gate electrode connected to the control clock signal line (ECLK) and the output terminal of the N-1 clear signal generator of the N-1 light emitting signal generator or the external signal line (CLR[n-1) The first electrode may be connected to (see CLR_in)) and the second electrode may be connected to the Clear Q node (CLR_Q). The first signal generation transistor (Eclr1) operates based on the control clock signal and can control the clear Q node (CLR_Q) with an external signal (CLR_in), etc.

The second signal generation transistor (Eclr2) has a gate electrode connected to the clear Q node (CLR_Q), a first electrode connected to the third high voltage line (GVDD1), and a second electrode connected to the output terminal of the first clear signal generator (CLRC). This can be connected. The second signal generation transistor (Eclr2) operates based on the potential of the clear Q node (CLR_Q) and can output the Nth clear signal (CLR[n]) of high voltage through the output terminal of the first clear signal generator.

The third signal generation transistor (Eclr3) has a gate electrode connected to the output terminal (see CLR[n+i]) of the N+i clear signal generator of the N+i (i is an integer greater than 1) light emitting signal generator, and a second The first electrode may be connected to the output terminal of the first clear signal generator, which is the first electrode of the signal generation transistor (Eclr2), and the second electrode may be connected to the third low voltage line (GVSS2). The third signal generation transistor (Eclr3) operates based on the N+i-th clear signal and can output the low-voltage N-th clear signal (CLR[n]) through the output terminal of the first clear signal generator.

The first clear circuit unit (CLC) may include a first clear transistor (Eclrq), a second clear transistor (Eclrn), and a third clear transistor (Eclro). The first clear transistor (Eclrq), the second clear transistor (Eclrn), and the third clear transistor (Eclro) may operate based on the Nth clear signal output through the output terminal of the first clear signal generator (CLRC). .

The first clear transistor (Eclrq) has a gate electrode connected to the output terminal of the first clear signal generator (CLRC), a first electrode connected to the Q2 node (Q2), and a second electrode connected to the third low voltage line (GVSS2). You can. The first clear transistor (Eclrq) operates based on the Nth clear signal (CLR[n]) output through the output terminal of the first clear signal generator (CLRC) and initializes the Q2 node (Q2) with the third low voltage. You can.

The second clear transistor (Eclrn) has a gate electrode connected to the output terminal of the first clear signal generator (CLRC), a first electrode connected to the net node (NET), and a second electrode connected to the third low voltage line (GVSS2). You can. The second clear transistor (Eclrn) operates based on the Nth clear signal (CLR[n]) output through the output terminal of the first clear signal generator (CLRC) and initializes the net node (NET) with the third low voltage. You can.

The third clear transistor (Eclro) has a gate electrode connected to the output terminal of the first clear signal generator (CLRC) and is connected to the Nth light emitting signal output terminal (EO[n]) of the Nth light emitting signal generator (EMG[n]). The first electrode may be connected and the second electrode may be connected to the first low voltage line (GVSS0). The third clear transistor (Eclro) operates based on the Nth clear signal (CLR[n]) output through the output terminal of the first clear signal generator (CLRC) and is supplied to the Nth light emitting signal generator (EMG) using the third low voltage. The Nth light emitting signal output terminal (EO[n]) of [n]) can be initialized.

As shown in FIGS. 13 and 14, the Nth light emitting signal generator (EMG[n]) may operate based on an external signal (CLR_in) and a first control clock signal (Eclk1). And the N+1th light emitting signal generator located at the rear of the Nth light emitting signal generator (EMG[n]) is the output terminal of the first clear signal generator (CLRC) of the Nth light emitting signal generator (EMG[n]). It can be operated based on the Nth clear signal (CLR[n]) and the second control clock signal (Eclk2) output from.

The second start signal (Evst) may be generated as a low voltage (L) during the clear section (CLR section) and may be generated as a high voltage (H) during the light emission drive section (EMG drive section). Accordingly, the Nth light emitting signal generator (EMG[n]) and the N+1th light emitting signal generator have a clear section (CLR section) for clearing the node and a light emission drive section (EMG drive section) for generating the light emitting signal. It can be operated separately. As can be seen in EQbst, during the period when the Nth clear signal (CLR[n]) of the high voltage (H) is generated, the Qb2 node of the Nth light emitting signal generator (EMG[n]) is exposed to the low voltage (L). It can have a potential of

When the first control clock signal (Eclk1) of high voltage (H) is input after the external signal (CLR_in) of high voltage (H) is input to the Nth light emitting signal generator (EMG[n]), the Nth light emitting signal The first clear signal generator (CLRC) of the generator (EMG[n]) may output the Nth clear signal (CLR[n]) of the high voltage (H). When the Nth clear signal (CLR[n]) of high voltage (H) is output through the output terminal of the first clear signal generator (CLRC), the first clear transistor (Eclrq) included in the first clear circuit portion (CLC) , the second clear transistor (Eclrn) and the third clear transistor (Eclro) may be turned on.

When the first clear transistor (Eclrq), the second clear transistor (Eclrn), and the third clear transistor (Eclro) are turned on, the Q2 node (Q2[n]) of the Nth light emitting signal generator (EMG[n]), the net The node (NET[n]) and the Nth light emitting signal output terminal (EO[n]) may be initialized.

Afterwards, the N+1-th light-emitting signal generator located at the rear of the N-th light-emitting signal generator (EMG[n]) is the first clear signal generator (CLRC) of the N-th light-emitting signal generator (EMG[n]). Operation can be continued based on the Nth clear signal (CLR[n]) and the second control clock signal (Eclk2) output from the output terminal. And the Q2 node (Q2[n+1]), the net node (NET[n+1]), and the N+1th light emitting signal output terminal (EO[n+1]) of the N+1th light emitting signal generator emit the Nth light. The time (approximately 1/2 of can be initialized with an overlap time).

Figure 15 is a diagram showing the change in clear signal generation according to the variation of the clear input signal applied to the Nth light emitting signal generator according to the second embodiment, and Figures 16 and 17 are diagrams showing the change in clear signal generation according to the second embodiment. These are simulation results showing the signals and the initialization of the Nth light emitting signal generator using them.

As shown in FIG. 15, the pulse width of the external signal (CLR_in) can be varied. The pulse width of the external signal (CLR_in) can be varied in response to the period of the control clock signal (Eclk1 or Eclk2). This can be seen by referring to the fact that the pulse width of the first clear signal (CLR[1]) begins to vary from the second rising edge generation time of the first control clock signal (ECLK1) and ends at the third rising edge generation time.

In addition, the signal input to the third signal generation transistor included in the N-th light emitting signal generator can be varied by considering the phase of the control clock signal and the period of the control clock signal that determines the pulse width of the external signal (CLR_in). , this is expressed as "Eclk: A phase & CLR_in Width: B cycle of Eclk -> Eclr3: CLR (n + A*B)".

In the above expression, "Eclk: A phase" means that the phase of the control clock signal is A, and "CLR_in Width: B period of Eclk" means that the period of the control clock signal that determines the pulse width of the external signal (CLR_in) is B. That is, “Eclr3: CLR (n + A*B)” is a signal for controlling the third signal generation transistor. Here, if the phase corresponding to A is selected as 4 and the period corresponding to B is selected as 2, the signal for controlling the third signal generating transistor may be “Eclr3: CLR (n + 8)”.

As shown in FIG. 16, when a gate signal generation circuit capable of generating a light emitting signal is implemented according to the second embodiment, some overlapping time (approximately 1/2 overlapping time) is calculated based on the external signal (CLR_in). A first clear signal (CLR[1]), a second clear signal (CLR[2]), and a third clear signal (CLR[3]) may be sequentially generated.

As shown in FIG. 17, when the N-th clear signal (CLR[n]) generated according to the second embodiment is applied to the N-th light-emitting signal generator, the Q2 node (Q2[n]) of the N-th light-emitting signal generator ), the Nth light emitting signal output terminal (EO[n]) and the net node (NET[n]) can be initialized at the same time. If this method is applied to all stages of the light emitting signal generators, sequential initialization for each stage is possible.

Since the light emitting signal generator operates with long pulses, there may be almost no time when all output stages are turned off at the same time. However, as described above, if a circuit capable of outputting a clear signal is implemented in the light emitting signal generator and the clear signal generated from this is applied to the nodes, the driving reliability and driving stability of the device are improved through sequential initialization for each stage. You can do it.

The present embodiment is based on a gate signal generation circuit having a light emitting signal generator capable of sequential initialization for each stage by applying the self-generated clear signal to its own nodes and applying it to dependently connected stages. This has the effect of improving the driving reliability and driving stability of the device.

130: gate driver 150: display panel
SCG[n]: Nth scan signal generator EMG[n]: Nth light emitting signal generator
CLRC: First clear signal generation unit CLC: First clear circuit unit
CLR_in: external signal

Claims (12)

A display panel that displays images;
a data driver that supplies data voltage to the display panel; and
A gate driver including an N-th scan signal generator that supplies an N-th scan signal to the display panel and an N-th light-emitting signal generator that supplies an N-th light-emitting signal to the display panel,
The gate driver
It is connected to the input terminal of the Nth light emitting signal generator and includes an external signal line for transmitting an external signal and a control clock signal line for transmitting a control clock signal,
A display device that generates an Nth clear signal to initialize at least one of the nodes of the Nth light emitting signal generator based on the external signal and the control clock signal. According to paragraph 1,
The gate driver
A display device that initializes at least one of the nodes of the N-th light-emitting signal generator based on the N-th clear signal during a clear section of the N-th light-emitting signal generator in which the N-th light-emitting signal is not output. According to paragraph 1,
The Nth light emitting signal generator
A light emitting node control circuit that alternately controls the Q2 node and the Qb2 node to generate the Nth light emitting signal and controls a net node for controlling the Qb2 node;
A display device comprising a light-emitting signal output unit that outputs the N-th light-emitting signal through an N-th light-emitting signal output terminal of the N-th light-emitting signal generator in response to potentials of the Q2 node, the Qb2 node, and the net node. According to paragraph 3,
The Nth light emitting signal generator
A clear signal generator that generates the Nth clear signal based on the external signal and the control clock signal,
The clear signal generator
A first signal generation transistor that operates based on the control clock signal and transmits the external signal, and a second device that operates in response to the external signal transmitted from the first signal generation transistor and generates the clear signal based on a high voltage. A display device including a second signal generation transistor and a third signal generation transistor that changes the voltage state of the clear signal based on the signal transmitted from the N+1th light emitting signal generator. According to clause 4,
The Nth light emitting signal generator
A clear circuit unit that initializes at least one of the nodes of the N-th light emitting signal generator based on the N-th clear signal,
The clear circuit part
A display device including a first clear transistor for initializing the Q2 node based on the Nth clear signal, a second clear transistor for initializing the net node, and a third clear transistor for initializing the Nth light emitting signal output terminal. . According to clause 5,
The clear circuit part
A display device that simultaneously initializes the Q2 node, the net node, and the Nth light emitting signal output terminal based on the Nth clear signal. According to clause 4,
The first signal generation transistor has a gate electrode connected to the control clock signal line, a first electrode connected to the external signal line, and a second electrode connected to the clear Q node,
The second signal generating transistor has a gate electrode connected to the clear Q node, a first electrode connected to a high voltage line, and a second electrode connected to the output terminal of the clear signal generator,
The third signal generation transistor has a gate electrode connected to the output terminal of the N+i clear signal generator of the N+i (i is an integer greater than 1) light emitting signal generator, and a first electrode connected to the output terminal of the clear signal generator. A display device with a second electrode connected to a low voltage line. According to clause 5,
The first clear transistor has a gate electrode connected to the output terminal of the clear signal generator, a first electrode connected to the Q2 node, and a second electrode connected to a low voltage line,
The second clear transistor has a gate electrode connected to the output terminal of the clear signal generator, a first electrode connected to the net node, and a second electrode connected to the low voltage line,
The third clear transistor has a gate electrode connected to the output terminal of the clear signal generator, a first electrode connected to the output terminal of the Nth light emitting signal, and a second electrode connected to a low voltage line having a different level from the low voltage line. a scan node control circuit unit that alternately controls the Q1 node and the Qb1 node, and an Nth scan signal generator that outputs the Nth scan signal in response to potentials of the Q1 node and the Qb1 node;
A light emitting node control circuit unit that alternately controls the Q2 node and the Qb2 node and controls a net node for controlling the Qb2 node, and generates an Nth light emitting signal in response to the potentials of the Q2 node, the Qb2 node, and the net node. An N-th light emitting signal generator that outputs; and
It is connected to the input terminal of the Nth light emitting signal generator and includes an external signal line for transmitting an external signal and a control clock signal line for transmitting a control clock signal,
A gate driving circuit in which the Nth light emitting signal generator generates an Nth clear signal for initializing at least one of the nodes of the Nth light emitting signal generator based on the external signal and the control clock signal. According to clause 9,
The Nth light emitting signal generator
A gate driving circuit that initializes at least one of the nodes of the N-th light-emitting signal generator based on the N-th clear signal during a clear period of the N-th light-emitting signal generator in which the N-th light-emitting signal is not output. According to clause 9,
The Nth light emitting signal generator
A clear signal generator that generates the Nth clear signal based on the external signal and the control clock signal,
The clear signal generator
A first signal generation transistor that operates based on the control clock signal and transmits the external signal, and a second device that operates in response to the external signal transmitted from the first signal generation transistor and generates the clear signal based on a high voltage. A gate driving circuit including two signal generation transistors and a third signal generation transistor that changes the voltage state of the clear signal based on the signal transmitted from the N+1th light emitting signal generator. According to clause 9,
The Nth light emitting signal generator
A clear circuit unit that initializes at least one of the nodes of the N-th light emitting signal generator based on the N-th clear signal,
The clear circuit part
Gate driving including a first clear transistor for initializing the Q2 node based on the Nth clear signal, a second clear transistor for initializing the net node, and a third clear transistor for initializing the Nth light emitting signal output terminal. Circuit.