KR20220036185A - Light Emitting Display Device and Driving Method of the same - Google Patents

Abstract

The present invention relates to a display panel including subpixels of odd-numbered lines and subpixels of even-numbered lines commonly connected to one light emitting signal line; and a driver configured to drive the subpixels of the odd-numbered lines and the subpixels of the even-numbered lines, wherein the subpixels of the odd-numbered lines and the subpixels of the even-numbered lines store data voltages at different times and then drive at the same time. A light emitting display device that initializes a node to which current is applied can be provided.

Description

Light emitting display device and driving method thereof {Light Emitting Display Device and Driving Method of the same}

The present invention relates to a light emitting display device and a method of driving the same.

As information technology develops, the market for display devices, which are a connecting medium between users and information, is growing. Accordingly, the use of display devices such as light emitting display devices, quantum dot display devices, and liquid crystal display devices is increasing.

The display devices described above include a display panel including subpixels, a driver that outputs a driving signal to drive the display panel, and a power supply that generates power to be supplied to the display panel or the driver.

The above display devices can display images by transmitting light or directly emitting light through the selected subpixels when driving signals, such as scan signals and data signals, are supplied to the subpixels formed on the display panel.

The present invention improves the problem of brightness differences between organic light emitting diodes and improves brightness uniformity when expressing low gray levels by eliminating the brightness deviation between subpixels.

The present invention relates to a display panel including subpixels of odd-numbered lines and subpixels of even-numbered lines commonly connected to one light emitting signal line; and a driver configured to drive the subpixels of the odd-numbered lines and the subpixels of the even-numbered lines, wherein the subpixels of the odd-numbered lines and the subpixels of the even-numbered lines store data voltages at different times and then drive at the same time. A light emitting display device that initializes a node to which current is applied can be provided.

The sub-pixel of the odd-numbered line and the sub-pixel of the even-numbered line may have the same section for initializing the light-emitting diode and the same section for emitting light.

The sub-pixels of the odd-numbered lines and the sub-pixels of the even-numbered lines have an interval for initializing the light emitting diode at least twice before and after storing the data voltage in the capacitor, and the at least two initialization intervals can all be performed at the same time.

The subpixels of the odd-numbered lines and the subpixels of the even-numbered lines may have a structure in which at least three transistors are commonly connected to the one light emitting signal line.

One of the at least three transistors may operate opposite to the other two transistors.

The odd-numbered subpixel has a driving transistor that generates a driving current, a gate electrode connected to the first scan line of the odd-numbered line, a first electrode connected to the gate electrode of the driving transistor, and a second electrode connected to the driving transistor. A first transistor connected to a second electrode, a gate electrode connected to the second scan line of the odd-numbered line, a first electrode connected to the first data line, and a second electrode connected to the first electrode of the driving transistor. A transistor, a third transistor having a gate electrode connected to a light emitting signal line, a first electrode connected to a first power line, a second electrode connected to the first electrode of the driving transistor, and a gate electrode connected to the light emitting signal line. A fourth transistor has a first electrode connected to the second electrode of the driving transistor and a second electrode connected to the anode electrode of the light emitting diode, a gate electrode connected to the third scan line of the odd number line, and a fourth transistor connected to the initialization voltage line. A fifth transistor with one electrode connected to the second electrode of the driving transistor, a gate electrode connected to the light emitting signal line, a first electrode connected to the variable voltage line, and a fifth transistor connected to the anode electrode of the light emitting diode. A sixth transistor with a second electrode connected to it, a capacitor with one end connected to the first power line and the other end connected to the gate electrode of the driving transistor, and an anode electrode connected to the second electrode of the fourth transistor and a second power line. It may include the light emitting diode with a cathode electrode connected to it.

The sub-pixels of the even-numbered lines include the same circuitry as the sub-pixels of the odd-numbered lines, but only the one light-emitting signal line may be connected in common.

The types of the second to fifth transistors may be different from the types of the first transistor and the sixth transistor.

The subpixels of the odd-numbered lines and the subpixels of the even-numbered lines may maintain an initialized state for the same amount of time before the light emitting diode emits light.

In another aspect, the present invention provides a display panel including subpixels of odd lines and subpixels of even lines commonly connected to one light emitting signal line, and a driver that drives the subpixels of the odd lines and the subpixels of the even lines. A method of driving a light emitting display device comprising: storing a data voltage in a subpixel of the odd-numbered lines for a first time; storing a data voltage in a subpixel of the even-numbered line for a second time after the first time; initializing nodes to which a driving current is applied to subpixels of the odd-numbered lines and subpixels of the even-numbered lines for a third time after the second time; and emitting light in the subpixels of the odd-numbered lines and the subpixels of the even-numbered lines for a fourth time after the third time.

The sub-pixel of the odd-numbered line and the sub-pixel of the even-numbered line may have the same section for initializing the light-emitting diode and the same section for emitting light.

The subpixels of the odd-numbered lines and the subpixels of the even-numbered lines may maintain an initialized state for the same amount of time before the light emitting diode emits light.

The present invention can improve the problem of brightness differences between organic light-emitting diodes, and also improve brightness uniformity when expressing low gray levels by eliminating brightness differences between sub-pixels. Additionally, the present invention has the effect of improving display quality by eliminating luminance deviation that may occur when implementing a display panel having two subpixels commonly connected to one light emitting signal line.

FIG. 1 is a block diagram schematically showing the configuration of a light emitting display device, FIG. 2 is an exemplary configuration diagram of a device related to a gate-in-panel scan driver, and FIG. 3 is an exemplary arrangement of a gate-in-panel scan driver.
FIG. 4 is a block diagram for explaining a light emitting display device according to a first embodiment of the present invention, and FIG. 5 is a diagram briefly showing the subpixel shown in FIG. 4.
FIG. 6 is a circuit diagram of a subpixel according to the first embodiment of the present invention, and FIG. 7 is a driving waveform diagram of the subpixel shown in FIG. 6.
8 to 13 are diagrams for explaining a subpixel driving method according to the first embodiment of the present invention.
14 to 20 are diagrams for explaining a method of driving subpixels of odd-numbered lines and subpixels of even-numbered lines according to a second embodiment of the present invention.
21 to 27 are diagrams for explaining a method of driving subpixels of odd-numbered lines and subpixels of even-numbered lines according to a third embodiment of the present invention.
FIG. 28 is a circuit diagram of a subpixel according to a fourth embodiment of the present invention, and FIG. 29 is a driving waveform diagram of the subpixel shown in FIG. 28.
Figure 30 is a simulation waveform diagram showing the effects according to embodiments of the present invention.

The display device according to the present invention can be implemented in a television, video player, personal computer (PC), home theater, automobile electric device, smartphone, etc., but is not limited thereto. The display device according to the present invention can be implemented as a light emitting display device, quantum dot display device, liquid crystal display device, etc. However, hereinafter, for convenience of explanation, a light emitting display device that directly emits light based on an inorganic light emitting diode or an organic light emitting diode is taken as an example.

In addition, the light emitting display device described below takes as an example the subpixels of the display panel implemented based on n-type and p-type thin film transistors. A thin film transistor is a three-electrode device including a gate, source, and drain. The source is an electrode that supplies carriers to the transistor. Within a thin film transistor, carriers begin to flow from a source. The drain is the electrode through which carriers go out in a thin film transistor. That is, in a thin film transistor, carriers flow from the source to the drain.

In the case of a p-type thin film transistor, since the carrier is a hole, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-type thin film transistor, current flows from the source to the drain because holes flow from the source to the drain. On the other hand, in the case of an n-type thin film transistor, since the carriers are electrons, the source voltage has a lower voltage than the drain voltage so that electrons can flow from the source to the drain. In an n-type thin film transistor, since electrons flow from the source to the drain, the direction of current flows from the drain to the source. However, the source and drain of a thin film transistor can change depending on the applied voltage. Reflecting this, in the following description, one of the source and drain will be described as the first electrode, and the other one of the source and drain will be described as the second electrode.

FIG. 1 is a block diagram schematically showing the configuration of a light emitting display device, FIG. 2 is an exemplary configuration diagram of a device related to a gate-in-panel scan driver, and FIG. 3 is an exemplary arrangement of a gate-in-panel scan driver.

As shown in FIGS. 1 to 3, the light emitting display device includes an image supply unit 110, a timing control unit 120, a scan driver 130, a data driver 140, a display panel 150, and a power supply unit 180. It may include etc.

The image supply unit 110 (or host system) may output various driving signals in addition to image data signals supplied from the outside or image data signals stored in internal memory. The image supply unit 110 may supply data signals and various driving signals to the timing control unit 120.

The timing control unit 120 includes a gate timing control signal (GDC) for controlling the operation timing of the scan driver 130, a data timing control signal (DDC) for controlling the operation timing of the data driver 140, and various synchronization signals ( The vertical synchronization signal (Vsync) and the horizontal synchronization signal (Hsync) can be output. The timing control unit 120 may supply the data signal DATA supplied from the image supply unit 110 together with the data timing control signal DDC to the data driver 140. The timing control unit 120 may be formed in the form of an integrated circuit (IC) and mounted on a printed circuit board, but is not limited to this.

The power supply unit 180 converts the power supplied from the outside into a high potential first power source and a low potential second power source under the control of the timing control unit 120, and converts the power supply into the first power line and the second power line (VDDEL, VSSEL). ) can be output through. The power supply unit 180 provides not only the first power and the second power, but also the voltage required to drive the scan driver 130 (e.g., a gate voltage including the gate high voltage and the gate low voltage) or the data driver 140. The necessary voltage (drain voltage including drain voltage and half-drain voltage) can be generated and output.

The data driver 140 samples and latches the data signal (DATA) in response to the data timing control signal (DDC) supplied from the timing control unit 120 and converts the digital data signal into analog data based on the gamma reference voltage. It can be converted to voltage and output. The data driver 140 may supply a data voltage to subpixels included in the display panel 150 through the data lines DL1 to DLn. The data driver 140 may be formed in the form of an IC and mounted on the display panel 150 or on a printed circuit board, but is not limited thereto.

The display panel 150 can display images in response to driving signals including scan signals and data voltages, power sources, and other lights. Subpixels of the display panel 150 directly emit light. The display panel 150 may be manufactured based on a rigid or flexible substrate such as glass, silicon, or polyimide. And the subpixels that emit light may be composed of pixels containing red, green, and blue, or pixels containing red, green, blue, and white.

The scan driver 130 may output a scan signal (or scan voltage) in response to a gate timing control signal (GDC) supplied from the timing control unit 120. The scan driver 130 may supply scan signals to subpixels included in the display panel 150 through scan lines GL1 to GLm. The scan driver 130 may be formed in the form of an IC or directly on the display panel 150 using a gate in panel method.

The gate-in-panel scan driver 130 may include a shift register 131 and a level shifter 135. The level shifter 135 may generate and output one or more clock signals (Clks) and a start signal (Vst) based on signals output from the timing controller 120. Clock signals Clks may be generated and output in the form of K (K is an integer greater than 2) with different phases, such as 2-phase, 4-phase, and 8-phase.

The shift register 131 operates based on signals (Clks, Vst) output from the level shifter 135, and scan signals (Scan[ 1] ~ Scan[m]) can be output. The shift register 131 is formed in the form of a thin film on the display panel 150 using the gate-in-panel method.

The shift register 131 may generally be placed in the non-display area (NA) of the display panel 150. At this time, the shift register 131 is disposed in the left and right non-display areas (NA) of the display panel 150, as shown in FIG. 3 (a), or in the upper and lower non-display areas (NA) of the display panel 150, as shown in FIG. 3 (b). NA) can be placed.

Meanwhile, FIG. 3 shows, as an example, that the first shift register 131a and the second shift register 131b are arranged in the non-display area (NA) located on the left and right or top and bottom of the display area (AA). As explained, only one may be placed on the left, right, top, or bottom. Additionally, the shift register 131 may be divided into the non-display area (NA) and the display area (AA), or may be distributed throughout the display area (AA).

In addition, the level shifter 135, unlike the shift register 131, may be formed as an independent IC or included within the power supply unit 180. However, this is only an example, and depending on the implementation method of the light emitting display device, one or more of the timing control unit 120, scan driver 130, and data driver 140 may be implemented in various forms, such as being integrated into one IC. You can. However, hereinafter, for convenience of explanation, an example in which the shift register 131 is disposed in one non-display area (NA) will be shown and described.

FIG. 4 is a block diagram for explaining a light emitting display device according to a first embodiment of the present invention, and FIG. 5 is a diagram briefly showing the subpixel shown in FIG. 4.

As shown in FIG. 4, the shift register 131 may include a plurality of first to third scan signal generators (SCANG1 to SCANG3) and a plurality of light emitting signal generators (EMG).

The first to third scan signal generators (SCANG1 to SCANG3) generate first to third scan signals to control the operation of the red, green, and blue subpixels (R, G, and B) of the display panel 150. A signal may be generated. The light emitting signal generator (EMG) can generate a light emitting signal to control the light emission time (light emission start time and light emission end time) of the red, green, and blue subpixels (R, G, and B) of the display panel 150. there is.

The first to third scan signal generators (SCANG1 to SCANG3) and the light emitting signal generator (EMG) are connected to an odd horizontal line (hereinafter referred to as odd line) and an even horizontal line (hereinafter referred to as even line) on the display panel 150. The red, green, and blue subpixels (R, G, B) arranged in the (Even Line) can be paired to control them simultaneously.

Accordingly, the red, green, and blue subpixels (R, G, B) arranged on the Nth odd line ([n]Odd Line) and the Nth even line ([n]Even Line) are It can be operated by the Nth first to third scan signal generators (SCANG1[n] to SCANG3[n]) and the Nth light emission signal generator (EMG[n]). And red, green, and blue subpixels (R, G, B) arranged on the N-1th odd line ([n]Odd Line) and the N-1th even line ([n]Even Line). The N-1st first to third scan signal generators (SCANG1[n-1] ~ SCANG3[n-1]) and the N-1st light emitting signal generator (EMG[n-1]) It can be operated by .

Therefore, the light-emitting display device according to the present invention can apply the light-emitting signal output from one light-emitting signal generator to subpixels located in two horizontal lines, thereby reducing the size of the light-emitting signal generator (approximately 1/2). ) can be done. That is, subpixels located on two horizontal lines can share one light emitting signal line (a structure commonly connected to one light emitting signal line) so that their operations are controlled by one light emitting signal.

As shown in FIGS. 4 and 5, one subpixel (SP) includes a signal line (GL1), a data line (DL1), a first power line (VDDEL), a second power line (VSSEL), and a variable voltage line. (VAR) and initialization voltage line (VINI). One subpixel (SP) may include a plurality of switching transistors, driving transistors, capacitors, organic light emitting diodes, etc.

One signal line (GL1) transmits the first to third scan signals output from the first to third scan signal generators (SCANG1 to SCANG3) and the emission control signal output from the emission signal generator (EMG). Can contain lines.

Sub-pixels (SP) used in light-emitting displays directly emit light, so the circuit configuration is complex. In addition, there are various circuits that compensate for the deterioration of not only the organic light-emitting diode that emits light, but also the driving transistor that supplies driving current to the organic light-emitting diode. Therefore, in FIG. 5, the subpixel SP is simply shown in the form of a block. However, hereinafter, a circuit constituting a subpixel and its driving method will be described in detail corresponding to the first embodiment of the present invention.

FIG. 6 is a circuit diagram of a subpixel according to the first embodiment of the present invention, and FIG. 7 is a driving waveform diagram of the subpixel shown in FIG. 6.

As shown in FIGS. 6 and 7, the subpixels according to the first embodiment include signal lines (SN1 to SN3, EM), data lines (DL1), first power lines (VDDEL), and second power lines (VSSEL). ), first to sixth transistors (T1 to T6) connected to the variable voltage line (VAR) and the initialization voltage line (VINI), a driving transistor (DT), a capacitor (CST), and an organic light emitting diode (OLED). You can. One signal line (SN1 to SN3, EM) may include a first scan line (SN1), a second scan line (SN2), a third scan line (SN3), and an emission signal line (EM).

According to the first embodiment, the first transistor (T1) and the sixth transistor (T6) may be implemented as n-type, and the second to fifth transistors (T2 to T5) and the driving transistor (DT) may be implemented as p-type. It can be implemented.

The first transistor (T1) has a gate electrode connected to the first scan line (SN1), a first electrode connected to the gate electrode (or second node N2) of the driving transistor (DT), and a first electrode of the driving transistor (DT). The second electrode may be connected to the second electrode (or N3, which is the third node). The first transistor T1 may be turned on in response to the logic high first scan signal Scan1 applied through the first scan line SN1. The first transistor T1 may function to connect the gate electrode and the second electrode of the driving transistor DT to create a diode connection state in order to compensate for the threshold voltage of the driving transistor DT.

The second transistor T2 has a gate electrode connected to the second scan line SN2, a first electrode connected to the first data line DL1, and the first electrode (or first node, N1) of the driving transistor DT. ) The second electrode may be connected to. The second transistor T2 may be turned on in response to the logic low second scan signal Scan2 applied through the second scan line SN2. The second transistor T2, together with the first transistor T1, may serve to apply a data voltage to the capacitor CST.

The third transistor (T3) has a gate electrode connected to the light emitting signal line (EM), a first electrode connected to the first power line (VDDEL), and a first electrode (or first node, N1) of the driving transistor (DT). A second electrode may be connected to. The third transistor T3 may be turned on in response to the logic low emission signal Em applied through the emission signal line EM. The third transistor T3 may serve to transmit the first power to the first node N1 to drive the driving transistor DT.

The fourth transistor (T4) has a gate electrode connected to the light emitting signal line (EM), a first electrode connected to the second electrode (or third node N3) of the driving transistor (DT), and an organic light emitting diode (OLED). A second electrode may be connected to the anode electrode. The fourth transistor T4 may be turned on in response to the logic low emission signal Em applied through the emission signal line EM. The fourth transistor (T4) may serve to transmit the driving current generated from the driving transistor (DT) to the fourth node (N4) (node to which the driving current is applied) in order to cause the organic light emitting diode (OLED) to emit light. .

The fifth transistor (T5) has a gate electrode connected to the third scan line (SN3), a first electrode connected to the initialization voltage line (VINI), and a second electrode (or third node, N3) of the driving transistor (DT). A second electrode may be connected to. The fifth transistor T5 may be turned on in response to the logic low third scan signal Scan3 applied through the third scan line SN3. The fifth transistor T5 may serve to initialize the driving transistor DT or a node related to the driving transistor DT based on the initialization voltage.

The sixth transistor (T6) has a gate electrode connected to the light emitting signal line (EM), a first electrode connected to the variable voltage line (VAR), and an anode electrode (or the fourth node, N4) of the organic light emitting diode (OLED). A second electrode may be connected. The sixth transistor T6 may be turned on in response to the logic high emission signal Em applied through the emission signal line EM. The sixth transistor (T6) may serve to initialize the anode electrode of an organic light-emitting diode (OLED) based on a variable voltage.

The driving transistor (DT) has a gate electrode connected to the second node (N2) connected to the other end of the capacitor (CST) and a second electrode connected to the second electrode of the second transistor (T2) and the second electrode of the third transistor (T3). A first electrode is connected to the first node (N1), and a third node ( A second electrode may be connected to N3). The driving transistor (DT) may serve to generate a driving current in response to the data voltage.

The capacitor CST may have one end connected to the first power line VDDEL and the other end connected to the gate electrode (or second node N2) of the driving transistor DT. The capacitor (CST) can store the data voltage and drive the driving transistor (DT) based on the stored data voltage.

The organic light emitting diode (OLED) may have an anode connected to the second electrode (or fourth node N4) of the fourth transistor (T4) and a cathode connected to the second power line (VSSEL). An organic light emitting diode (OLED) can emit light based on the driving current transmitted from the fourth transistor (T4).

The subpixel according to the first embodiment may operate based on the light emission signal (Em), the first scan signal (Scan1), the second scan signal (Scan2), and the third scan signal (Scan3). The light emission signal (Em), the first scan signal (Scan1), the second scan signal (Scan2), and the third scan signal (Scan3) are explained as follows.

The light emitting signal Em may maintain logic high during the second to fifth sections (2 to 5) and maintain logic low during the first section (1) and the sixth section (6). The first scan signal (Scan1) maintains logic low during the first, second, fifth and sixth sections (1, 2, 5, 6) and logic high during the third and fourth sections (3 and 4). can be maintained. The second scan signal Scan2 maintains a logic high during the first to third sections and the fifth to sixth sections (1 to 3, 5 to 6), and maintains a logic low only in the fourth section 4. The third scan signal Scan3 maintains logic high during the first, second, fourth to sixth sections (1, 2, 4 to 6), and maintains logic low only in the third section (3).

8 to 13 are diagrams for explaining a subpixel driving method according to the first embodiment of the present invention.

During the first section 1 shown in FIG. 8, the subpixel includes a logic low light emission signal (Em), a logic low first scan signal (Scan1), a logic high second scan signal (Scan2), and a logic high light emitting signal (Em). A third scan signal (Scan3) may be applied. In this case, the third transistor (T3), driving transistor (DT), and fourth transistor (T4) may be turned on. When the third transistor T3, driving transistor DT, and fourth transistor T4 are turned on, the driving transistor DT may generate driving current. The driving current generated from the driving transistor (DT) may be applied to the organic light emitting diode (OLED). As a result, the organic light emitting diode (OLED) can emit light based on the driving current generated from the driving transistor (DT).

During the second section 2 shown in FIG. 9, the subpixel includes a logic high light emission signal (Em), a logic low first scan signal (Scan1), a logic high second scan signal (Scan2), and a logic high light emitting signal (Em). A third scan signal (Scan3) may be applied. In this case, the sixth transistor T6 may be turned on. When the sixth transistor T6 is turned on, the anode electrode of the organic light emitting diode (OLED) may be connected to the variable voltage line (VAR). As a result, an initialization stage may be entered in which voltage remaining on the anode electrode of the organic light emitting diode (OLED) is removed.

During the third section 3 shown in FIG. 10, the subpixel includes a logic high light emission signal (Em), a logic high first scan signal (Scan1), a logic high second scan signal (Scan2), and a logic low signal. A third scan signal (Scan3) may be applied. In this case, the first transistor (T1), the fifth transistor (T5), and the sixth transistor (T6) may be turned on. When the first transistor T1 and the fifth transistor T5 are turned on, the driving transistor DT may be in a diode connection state and connected to the initialization voltage line VINI. As a result, the driving transistor DT can be initialized by the initialization voltage and the threshold voltage can be sampled. Since the sixth transistor T6 is in the same turned-on state as before, it is possible to maintain an initialization stage in which voltage remaining on the anode electrode of the organic light-emitting diode (OLED) is removed.

During the fourth section 4 shown in FIG. 11, the subpixel includes a logic high light emitting signal (Em), a logic high first scan signal (Scan1), a logic low second scan signal (Scan2), and a logic high light emitting signal (Em). A third scan signal (Scan3) may be applied. In this case, the second transistor (T2), driving transistor (DT), first transistor (T1), and sixth transistor (T6) may be turned on. When the second transistor (T2), the driving transistor (DT), and the first transistor (T1) are turned on, the data voltage applied through the first data line (DL1) is applied to the second node (N2) and then applied to the capacitor ( CST). Since the sixth transistor T6 is in the same turned-on state as before, it is possible to maintain an initialization stage in which voltage remaining on the anode electrode of the organic light-emitting diode (OLED) is removed.

During the fifth section 5 shown in FIG. 12, the subpixel includes a logic high light emitting signal (Em), a logic low first scan signal (Scan1), a logic high second scan signal (Scan2), and a logic high light emitting signal (Em). A third scan signal (Scan3) may be applied. In this case, only the sixth transistor T6 can remain turned on. Since the sixth transistor T6 is in the same turned-on state as before, it is possible to maintain an initialization stage in which voltage remaining on the anode electrode of the organic light-emitting diode (OLED) is removed.

During the sixth section 6 shown in FIG. 13, the subpixel includes a logic low light emission signal (Em), a logic low first scan signal (Scan1), a logic high second scan signal (Scan2), and a logic high light emission signal (Em). A third scan signal (Scan3) may be applied. In this case, the third transistor (T3), driving transistor (DT), and fourth transistor (T4) may be turned on. When the third transistor T3, driving transistor DT, and fourth transistor T4 are turned on, the driving transistor DT may generate driving current. The driving current generated from the driving transistor (DT) may be applied to the organic light emitting diode (OLED). As a result, the organic light emitting diode (OLED) can emit light based on the driving current generated from the driving transistor (DT).

Referring to the above description, the subpixel according to the first embodiment includes a first initialization section (2), a second initialization section (3), a sampling and data voltage storage section (4), a holding section (5), and a light emission section ( As shown in 6), it can operate in at least 5 sections. However, this is only a description of the operation state for each section based on one subpixel, and the second embodiment is described based on the operation relationship linking the subpixels of odd-numbered lines and the subpixels of even-numbered lines as follows.

14 to 20 are diagrams for explaining a method of driving subpixels of odd-numbered lines and subpixels of even-numbered lines according to a second embodiment of the present invention.

Referring to FIGS. 14 to 20, the odd-numbered line subpixel (SP[N-1]) and the even-numbered line subpixel (SP[N]) may be adjacent to each other vertically, and the circuits configuring them may be the same. there is. In addition, the odd-numbered line subpixel (SP[N-1]) and the even-numbered subpixel (SP[N]) may share (commonly connect) one emission signal line (EM).

However, the subpixel (SP[N-1]) of the odd number line is connected to the first to third scan lines (SN1[Odd] to SN3[Odd]) of the odd number line, but the subpixel (SP[N]) of the even number line is connected to the first to third scan lines (SN1[Odd] to SN3[Odd]) of the odd number line. ) is connected to the first to third scan lines (SN1[Even] to SN3[Even]) of the even number lines. And as the connection relationship of the scan lines is different, the subpixels (SP[N-1]) of the odd lines operate based on the first to third scan signals (Scan1[Odd] ~ Scan3[Odd]) of the odd lines. However, please note that the subpixels (SP[N]) of the even-numbered lines operate based on the first to third scan signals (Scan1[Even] to Scan3[Even) of the even-numbered lines.

During the first section (1) shown in FIG. 14, a logic low emission signal (Em) and a logic low subpixel (SP[N-1]) of the odd line and the subpixel (SP[N]) of the even number line are applied. A first scan signal (Scan1), a logic high second scan signal (Scan2), and a logic high third scan signal (Scan3) may be applied. In this case, the third transistor (T3), driving transistor (DT), and fourth transistor (T4) of the odd-line subpixel (SP[N-1]) and the even-line subpixel (SP[N]) are turned on. It can be. As a result, the organic light emitting diode (OLED) of the odd-line subpixel (SP[N-1]) and the even-line subpixel (SP[N]) emit light based on the driving current generated from the driving transistor (DT). can emit light.

During the second section 2 shown in FIG. 15, a logic high light emission signal (Em) and a logic low subpixel (SP[N-1]) of the odd line and the subpixel (SP[N]) of the even number line are applied. A first scan signal (Scan1), a logic high second scan signal (Scan2), and a logic high third scan signal (Scan3) may be applied. In this case, the sixth transistor T6 of the odd-line subpixel (SP[N-1]) and the even-line subpixel (SP[N]) may be turned on. As a result, the voltage remaining on the anode electrode of the organic light emitting diode (OLED) of the odd-line subpixel (SP[N-1]) and the even-line subpixel (SP[N]) enters the initialization stage in which the remaining voltage is removed. It can be.

During the third section 3 shown in FIG. 16, the subpixel (SP[N-1]) of the odd-numbered line contains a logic high light emission signal (Em), a logic high first scan signal (Scan1), and a logic high light emitting signal (Em). A second scan signal (Scan2) and a third scan signal (Scan3) of logic low may be applied. In this case, the first transistor T1, the fifth transistor T5, and the sixth transistor T6 of the odd-numbered line subpixel SP[N-1] may be turned on. As a result, the driving transistor (DT) of the odd line subpixel (SP[N-1]) can be initialized by the initialization voltage and the threshold voltage can be sampled, and the organic light emitting diode (OLED) can maintain the initialization stage. .

On the other hand, the subpixel (SP[N]) of the even line includes a logic high light emission signal (Em), a logic low first scan signal (Scan1), a logic high second scan signal (Scan2), and a logic high third scan signal (Scan2). A scan signal (Scan3) may be applied. In this case, the sixth transistor T6 of the even-numbered line subpixel SP[N] may be turned on, and the organic light emitting diode (OLED) may maintain the initialization stage. That is, the subpixel (SP[N]) on the even-numbered line may have driving timing that is delayed by one section (or driving timing that lags behind) the subpixel (SP[N-1]) on the odd-numbered line.

During the fourth section 4 shown in FIG. 17, the subpixel (SP[N-1]) of the odd-numbered line has a logic high light emission signal (Em), a logic high first scan signal (Scan1), and a logic low signal. A second scan signal (Scan2) and a logic high third scan signal (Scan3) may be applied. In this case, the second transistor T2, driving transistor DT, first transistor T1, and sixth transistor T6 of the odd-numbered subpixel SP[N-1] may be turned on. As a result, the odd-numbered subpixel (SP[N-1]) is stored in the capacitor (CST) after the data voltage applied through the first data line (DL1) is applied to the second node (N2), and the organic Light emitting diodes (OLEDs) can maintain the initialization phase.

On the other hand, the subpixel (SP[N]) of the even line includes a logic high light emission signal (Em), a logic high first scan signal (Scan1), a logic high second scan signal (Scan2), and a logic low third scan signal. A scan signal (Scan3) may be applied. In this case, the first transistor T1, the fifth transistor T5, and the sixth transistor T6 of the even-numbered line subpixel SP[N] may be turned on. As a result, the driving transistor (DT) of the even-numbered subpixel (SP[N]) can be initialized by the initialization voltage and the threshold voltage can be sampled, and the organic light emitting diode (OLED) can maintain the initialization stage.

During the fifth section 5 shown in FIG. 18, a logic high light emission signal (Em), a logic low first scan signal (Scan1), and a logic high subpixel (SP[N-1]) of the odd line are generated. A second scan signal (Scan2) and a logic high third scan signal (Scan3) may be applied. In this case, since only the sixth transistor T6 of the odd line subpixel SP[N-1] is maintained in the turned-on state, the organic light emitting diode (OLED) can maintain the initialization stage.

On the other hand, the subpixel (SP[N]) of the even line includes a logic high light emission signal (Em), a logic high first scan signal (Scan1), a logic low second scan signal (Scan2), and a logic high third scan signal (Scan2). A scan signal (Scan3) may be applied. In this case, the second transistor T2, driving transistor DT, first transistor T1, and sixth transistor T6 of the even-numbered line subpixel SP[N] may be turned on. As a result, the subpixel (SP[N]) of the even number line is stored in the capacitor (CST) after the data voltage applied through the first data line (DL1) is applied to the second node (N2), and the organic light emitting diode. (OLED) can maintain the initialization phase.

During the sixth section 6 shown in FIG. 19, the odd-numbered line sub-pixel (SP[N-1]) has a logic high light emission signal (Em), a logic low first scan signal (Scan1), and a logic high signal. A second scan signal (Scan2) and a logic high third scan signal (Scan3) may be applied. That is, the odd-numbered line subpixel (SP[N-1]) can maintain the same driving state as before.

On the other hand, the subpixel (SP[N]) of the even line includes a logic high light emission signal (Em), a logic low first scan signal (Scan1), a logic high second scan signal (Scan2), and a logic high third scan signal (Scan2). A scan signal (Scan3) may be applied. In this case, since only the sixth transistor T6 of the even-numbered line subpixel SP[N] is maintained in the turned-on state, the organic light emitting diode (OLED) can maintain the initialization stage. As can be seen from the explanation of the second section (2) and the sixth section (6), the initialization step for the organic light emitting diode (OLED) has two steps before and after storing the data voltage in the capacitor (CST), and two steps. Both initialization sections may be performed at the same time.

In this way, the odd-numbered line subpixel (SP[N-1]) and the even-numbered line subpixel (SP[N]) may have an initialization section at the same point in time. As the initialization section of the light emitting diode that occurs after storing the data voltage overlaps, a current deviation occurs between the odd-numbered line subpixel (SP[N-1]) and the even-numbered line subpixel (SP[N]). problems can be prevented or improved. Refer to FIG. 30 for simulation results.

During the seventh section 7 shown in FIG. 20, a logic low emission signal (Em) and a logic low subpixel (SP[N-1]) of the odd line and the subpixel (SP[N]) of the even number line are applied. A first scan signal (Scan1), a logic high second scan signal (Scan2), and a logic high third scan signal (Scan3) may be applied. In this case, the third transistor (T3), driving transistor (DT), and fourth transistor (T4) of the odd-line subpixel (SP[N-1]) and the even-line subpixel (SP[N]) are turned on. It can be.

As a result, the organic light emitting diode (OLED) of the odd-line subpixel (SP[N-1]) and the even-line subpixel (SP[N]) emit light based on the driving current generated from the driving transistor (DT). can emit light. In this way, the odd-numbered line subpixel (SP[N-1]) and the even-numbered line subpixel (SP[N]) may have an emission section at the same point in time after the initialization section overlaps.

As can be seen from the above explanation, the odd line subpixel (SP[N-1]) and the even line subpixel (SP[N]) are initialized throughout the entire period before the organic light emitting diode (OLED) emits light. The state can be maintained (maintained in initialized state for the same amount of time).

In addition, the third embodiment will be described based on the operational relationship linking the subpixels of odd-numbered lines and the subpixels of even-numbered lines as follows.

21 to 27 are diagrams for explaining a method of driving subpixels of odd-numbered lines and subpixels of even-numbered lines according to a third embodiment of the present invention.

Referring to FIGS. 21 to 27, the odd-numbered line subpixel (SP[N-1]) and the even-numbered line subpixel (SP[N]) may be adjacent to each other vertically, and the circuits configuring them may be the same. there is. In addition, the odd-numbered line subpixel (SP[N-1]) and the even-numbered subpixel (SP[N]) may share (commonly connect) one emission signal line (EM).

However, the subpixel (SP[N-1]) of the odd number line is connected to the first to third scan lines (SN1[Odd] to SN3[Odd]) of the odd number line, but the subpixel (SP[N]) of the even number line is connected to the first to third scan lines (SN1[Odd] to SN3[Odd]) of the odd number line. ) is connected to the first to third scan lines (SN1[Even] to SN3[Even]) of the even number lines. And as the connection relationship of the scan lines is different, the subpixels (SP[N-1]) of the odd lines operate based on the first to third scan signals (Scan1[Odd] ~ Scan3[Odd]) of the odd lines. However, please note that the subpixels (SP[N]) of the even-numbered lines operate based on the first to third scan signals (Scan1[Even] to Scan3[Even) of the even-numbered lines.

During the first section (1) shown in FIG. 21, a logic low emission signal (Em) and a logic low subpixel (SP[N-1]) of the odd line and the subpixel (SP[N]) of the even number line are applied. A first scan signal (Scan1), a logic high second scan signal (Scan2), and a logic high third scan signal (Scan3) may be applied. In this case, the third transistor (T3), driving transistor (DT), and fourth transistor (T4) of the odd-line subpixel (SP[N-1]) and the even-line subpixel (SP[N]) are turned on. It can be. As a result, the organic light emitting diode (OLED) of the odd-line subpixel (SP[N-1]) and the even-line subpixel (SP[N]) emit light based on the driving current generated from the driving transistor (DT). can emit light.

During the second section 2 shown in FIG. 22, a logic high light emission signal (Em), a logic high first scan signal (Scan1), and a logic high subpixel (SP[N-1]) of the odd line are applied. A second scan signal (Scan2) and a logic high third scan signal (Scan3) may be applied. In this case, the first transistor T1 and the sixth transistor T6 of the odd line subpixel SP[N-1] may be turned on. As a result, an initialization step can be entered in which the voltage remaining on the anode electrode of the organic light emitting diode (OLED) of the odd-numbered subpixel (SP[N-1]) is removed, and the driving transistor DT is connected to the first As transistor T1 is turned on, it may enter a diode connection state.

On the other hand, the subpixel (SP[N]) of the even line includes a logic high light emission signal (Em), a logic low first scan signal (Scan1), a logic high second scan signal (Scan2), and a logic high third scan signal (Scan2). A scan signal (Scan3) may be applied. In this case, the sixth transistor T6 of the even-numbered line subpixel SP[N] may be turned on. As a result, the odd-numbered line subpixel (SP[N-1]) and the even-lined subpixel (SP[N]) are initialized at the same time, such that the voltage remaining on the anode electrode of the organic light-emitting diode (OLED) is removed. stage can be entered.

Meanwhile, if explained based on the changes in transistors, the first transistor (T1) and sixth transistor (T6) of the odd-numbered subpixel (SP[N-1]) are turned off after the fourth transistor (T4) is turned off. It can be turned on. That is, the logic high point of the first scan signal applied to the odd-numbered subpixel (SP[N-1]) may be synchronized with the logic high point of the light emission signal (the logic high of Em and Scan1 occur simultaneously). However, the logic high point of the first scan signal applied to the subpixel (SP[N]) of the even number line is delayed from the logic high point of the first scan signal applied to the subpixel (SP[N-1]) of the odd line. (e.g. at least 1 horizontal time).

During the third section 3 shown in FIG. 23, a logic high light emission signal (Em) and a logic high subpixel (SP[N-1]) of the odd line and the subpixel (SP[N]) of the even number line are applied. A first scan signal (Scan1), a logic high second scan signal (Scan2), and a logic low third scan signal (Scan3) may be applied. In this case, the first transistor (T1), the fifth transistor (T5), and the sixth transistor (T6) of the odd-line subpixel (SP[N-1]) and the even-line subpixel (SP[N]) are It can be turned on. As a result, the driving transistor DT of the odd-line subpixel (SP[N-1]) and the even-line subpixel (SP[N]) are initialized at the same time and the threshold voltage can be sampled. Additionally, the organic light emitting diode (OLED) of the odd-line subpixel (SP[N-1]) and the even-line subpixel (SP[N]) may maintain the initialization stage at the same time.

During the fourth section 4 shown in FIG. 23, a logic high light emission signal (Em), a logic high first scan signal (Scan1), and a logic low subpixel (SP[N-1]) of the odd number line. A second scan signal (Scan2) and a logic high third scan signal (Scan3) may be applied. In this case, the second transistor T2, driving transistor DT, first transistor T1, and sixth transistor T6 of the odd-numbered subpixel SP[N-1] may be turned on. As a result, the odd-numbered subpixel (SP[N-1]) is stored in the capacitor (CST) after the data voltage applied through the first data line (DL1) is applied to the second node (N2), and the organic Light emitting diodes (OLEDs) can maintain the initialization phase.

On the other hand, the subpixel (SP[N]) of the even line includes a logic high light emission signal (Em), a logic high first scan signal (Scan1), a logic high second scan signal (Scan2), and a logic high third scan signal (Scan2). A scan signal (Scan3) may be applied. In this case, the first transistor T1 and the sixth transistor T6 of the even-numbered line subpixel SP[N] may be turned on. As a result, the organic light emitting diode (OLED) of the even-numbered line subpixel (SP[N]) can maintain the initialization stage.

During the fifth section 5 shown in FIG. 25, the odd-numbered line subpixel (SP[N-1]) has a logic high light emission signal (Em), a logic low first scan signal (Scan1), and a logic high signal. A second scan signal (Scan2) and a logic high third scan signal (Scan3) may be applied. In this case, since only the sixth transistor T6 of the odd line subpixel SP[N-1] is maintained in the turned-on state, the organic light emitting diode (OLED) can maintain the initialization stage.

On the other hand, the subpixel (SP[N]) of the even line includes a logic high light emission signal (Em), a logic high first scan signal (Scan1), a logic low second scan signal (Scan2), and a logic high third scan signal (Scan2). A scan signal (Scan3) may be applied. In this case, the second transistor T2, driving transistor DT, first transistor T1, and sixth transistor T6 of the even-numbered line subpixel SP[N] may be turned on. As a result, the subpixel (SP[N]) of the even number line is stored in the capacitor (CST) after the data voltage applied through the first data line (DL1) is applied to the second node (N2), and the organic light emitting diode. (OLED) can maintain the initialization phase.

During the sixth section 6 shown in FIG. 26, the sub-pixel (SP[N-1]) of the odd-numbered line has a logic high light emission signal (Em), a logic low first scan signal (Scan1), and a logic high signal. A second scan signal (Scan2) and a logic high third scan signal (Scan3) may be applied. That is, the odd-numbered line subpixel (SP[N-1]) can maintain the same driving state as before.

On the other hand, the subpixel (SP[N]) of the even line includes a logic high light emission signal (Em), a logic low first scan signal (Scan1), a logic high second scan signal (Scan2), and a logic high third scan signal (Scan2). A scan signal (Scan3) may be applied. In this case, since only the sixth transistor T6 of the even-numbered line subpixel SP[N] is maintained in the turned-on state, the organic light emitting diode (OLED) can maintain the initialization stage. As can be seen from the explanation of the second section (2) and the sixth section (6), the initialization step for the organic light emitting diode (OLED) has two steps before and after storing the data voltage in the capacitor (CST), and two steps. Both initialization sections may be performed at the same time.

In this way, the odd-numbered line subpixel (SP[N-1]) and the even-numbered line subpixel (SP[N]) may have an initialization section at the same point in time. As the initialization section of the light emitting diode that occurs after storing the data voltage overlaps, a current deviation occurs between the odd-numbered line subpixel (SP[N-1]) and the even-numbered line subpixel (SP[N]). problems can be prevented or improved. Refer to FIG. 30 for simulation results.

During the seventh section 7 shown in FIG. 27, a logic low emission signal (Em) and a logic low subpixel (SP[N-1]) of the odd line and the subpixel (SP[N]) of the even number line are applied. A first scan signal (Scan1), a logic high second scan signal (Scan2), and a logic high third scan signal (Scan3) may be applied. In this case, the third transistor (T3), driving transistor (DT), and fourth transistor (T4) of the odd-line subpixel (SP[N-1]) and the even-line subpixel (SP[N]) are turned on. It can be.

As a result, the organic light emitting diode (OLED) of the odd-line subpixel (SP[N-1]) and the even-line subpixel (SP[N]) emit light based on the driving current generated from the driving transistor (DT). can emit light. In this way, the odd-numbered line subpixel (SP[N-1]) and the even-numbered line subpixel (SP[N]) may have an emission section at the same point in time after the initialization section overlaps.

Meanwhile, a subpixel structure that can achieve the present invention may include the following fourth embodiment.

FIG. 28 is a circuit diagram of a subpixel according to a fourth embodiment of the present invention, and FIG. 29 is a driving waveform diagram of the subpixel shown in FIG. 28.

28 and 29, like the first embodiment, the subpixel according to the fourth embodiment includes first to sixth transistors (T1 to T6), a driving transistor (DT), a capacitor (CST), and It may include an organic light emitting diode (OLED). However, the fourth embodiment has a different transistor type compared to the first embodiment. Specifically, the first transistor (T1) and the sixth transistor (T6) may be implemented as a p-type, and the second to fifth transistors (T2 to T5) and the driving transistor (DT) may be implemented as an n-type. .

The first transistor (T1) has a gate electrode connected to the first scan line (SN1), a first electrode connected to the gate electrode (or second node N2) of the driving transistor (DT), and a first electrode of the driving transistor (DT). The second electrode may be connected to the second electrode (or N3, which is the third node). The first transistor T1 may be turned on in response to the logic high first scan signal Scan1 applied through the first scan line SN1. The first transistor T1 may function to connect the gate electrode and the second electrode of the driving transistor DT to create a diode connection state in order to compensate for the threshold voltage of the driving transistor DT.

The second transistor T2 has a gate electrode connected to the second scan line SN2, a first electrode connected to the first data line DL1, and the first electrode (or first node, N1) of the driving transistor DT. ) The second electrode may be connected to. The second transistor T2 may be turned on in response to the logic low second scan signal Scan2 applied through the second scan line SN2. The second transistor T2, together with the first transistor T1, may serve to apply a data voltage to the capacitor CST.

The third transistor (T3) has a gate electrode connected to the light emitting signal line (EM), a first electrode connected to the first power line (VDDEL), and a first electrode (or first node, N1) of the driving transistor (DT). A second electrode may be connected to. The third transistor T3 may be turned on in response to the logic low emission signal Em applied through the emission signal line EM. The third transistor T3 may serve to transmit the first power to the first node N1 to drive the driving transistor DT.

The fourth transistor (T4) has a gate electrode connected to the light emitting signal line (EM), a first electrode connected to the second electrode (or third node N3) of the driving transistor (DT), and an organic light emitting diode (OLED). A second electrode may be connected to the anode electrode. The fourth transistor T4 may be turned on in response to the logic low emission signal Em applied through the emission signal line EM. The fourth transistor T4 may serve to transfer the driving current generated from the driving transistor DT to the fourth node N4 in order to cause the organic light emitting diode (OLED) to emit light.

The fifth transistor (T5) has a gate electrode connected to the third scan line (SN3), a first electrode connected to the initialization voltage line (VINI), and a second electrode (or third node, N3) of the driving transistor (DT). A second electrode may be connected to. The fifth transistor T5 may be turned on in response to the logic low third scan signal Scan3 applied through the third scan line SN3. The fifth transistor T5 may serve to initialize the driving transistor DT or a node related to the driving transistor DT based on the initialization voltage.

The sixth transistor (T6) has a gate electrode connected to the light emitting signal line (EM), a first electrode connected to the variable voltage line (VAR), and an anode electrode (or the fourth node, N4) of the organic light emitting diode (OLED). A second electrode may be connected. The sixth transistor T6 may be turned on in response to the logic high emission signal Em applied through the emission signal line EM. The sixth transistor (T6) may serve to initialize the anode electrode of an organic light-emitting diode (OLED) based on a variable voltage.

The capacitor CST may have one end connected to the first power line VDDEL and the other end connected to the gate electrode (or second node N2) of the driving transistor DT. The capacitor (CST) can store the data voltage and drive the driving transistor (DT) based on the stored data voltage.

The organic light emitting diode (OLED) may have an anode connected to the second electrode (or fourth node N4) of the fourth transistor (T4) and a cathode connected to the second power line (VSSEL). An organic light emitting diode (OLED) can emit light based on the driving current transmitted from the fourth transistor (T4).

The subpixel according to the fourth embodiment operates based on the light emission signal (Em), the first scan signal (Scan1), the second scan signal (Scan2), and the third scan signal (Scan3) like the first embodiment. You can. However, the subpixel according to the fourth embodiment has a different transistor type compared to the first embodiment, and the light emission signal (Em), the first scan signal (Scan1), the second scan signal (Scan2), and the third scan signal ( Scan3) is explained as follows.

The light emitting signal Em may maintain logic low during the second to fifth sections (2 to 5) and maintain logic high during the first section (1) and the sixth section (6). The first scan signal (Scan1) maintains logic high during the first, second, fifth, and sixth sections (1, 2, 5, 6), and logic low during the third and fourth sections (3, 4). can be maintained. The second scan signal Scan2 maintains a logic low during the first to third sections and the fifth to sixth sections (1 to 3, 5 to 6), and maintains a logic high only in the fourth section 4. The third scan signal Scan3 maintains logic low during the first, second, fourth to sixth sections (1, 2, 4 to 6), and maintains logic high only in the third section (3).

Figure 30 is a simulation waveform diagram showing the effects according to embodiments of the present invention.

Referring to FIG. 30, the current change (OLED Current) of the organic light emitting diode included in the N-1th subpixel (N-th Line pixel) and the Nth subpixel (Nth Line pixel) can be seen. The N-1th subpixel (N-th Line pixel) and the Nth subpixel (Nth Line pixel) are located on different lines, but are subpixels that receive the same light emission signal.

Based on the embodiments of the present invention described above, when subpixels are configured and driven to receive the same light emitting signal although they are located on different lines, the driving timing between the two subpixels is matched so that the brightness between the organic light emitting diodes included in them is changed. It is possible to prevent problems causing differences (or eliminate OLED current differences).

Here, matching the driving timing between the two subpixels means matching the initialization section (N4 initial) performed through the fourth node of the two subpixels. In other words, it can be explained that the turn-on point of the sixth transistor included in the two subpixels is kept the same for at least one section. For an explanation related to this, refer to section 6 of the second or third embodiment.

In this way, by matching the initialization section (N4 inital) between the two subpixels, the problem of brightness differences between the organic light emitting diodes included in them can be improved, and this also eliminates the luminance differences between subpixels, thereby improving the luminance at low gray levels. Uniformity can be improved.

As described above, the present invention can improve the problem of brightness differences between organic light emitting diodes, and also has the effect of improving brightness uniformity when expressing low gray levels by eliminating the brightness deviation between sub-pixels. Additionally, the present invention has the effect of improving display quality by eliminating luminance deviation that may occur when implementing a display panel having two subpixels commonly connected to one light emitting signal line.

120: timing control unit 130: scan driver
140: data driver 150: display panel
T1 to T6: first to sixth transistors DT: driving transistor
CST: Capacitor OLED: Organic Light Emitting Diode

Claims (12)

a display panel including subpixels of odd-numbered lines and subpixels of even-numbered lines commonly connected to one light emitting signal line; and
A driving unit that drives subpixels of the odd-numbered lines and subpixels of the even-numbered lines,
A light emitting display device in which the subpixels of the odd-numbered lines and the subpixels of the even-numbered lines store data voltages at different times and then initialize a node to which a driving current is applied at the same time. According to paragraph 1,
The subpixels of the odd-numbered lines and the subpixels of the even-numbered lines are
A light emitting display device in which a section for initializing a light emitting diode and a section for emitting light from the light emitting diode are the same. According to paragraph 1,
The subpixels of the odd-numbered lines and the subpixels of the even-numbered lines are
A light emitting display device having at least two initialization sections of the light emitting diode before and after storing the data voltage in the capacitor, wherein the at least two initialization sections are all performed at the same time. According to paragraph 1,
The subpixels of the odd-numbered lines and the subpixels of the even-numbered lines are
A light emitting display device having a structure in which at least three transistors are commonly connected to the one light emitting signal line. According to clause 4,
A light emitting display device in which one of the at least three transistors operates in the opposite manner to the other two transistors. According to paragraph 1,
The subpixels of the odd-numbered lines are
A driving transistor that generates a driving current,
a first transistor having a gate electrode connected to a first scan line of an odd number line, a first electrode connected to a gate electrode of the driving transistor, and a second electrode connected to a second electrode of the driving transistor;
a second transistor having a gate electrode connected to a second scan line of the odd-numbered line, a first electrode connected to a first data line, and a second electrode connected to the first electrode of the driving transistor;
a third transistor having a gate electrode connected to a light emitting signal line, a first electrode connected to a first power line, and a second electrode connected to the first electrode of the driving transistor;
a fourth transistor having a gate electrode connected to the light emitting signal line, a first electrode connected to a second electrode of the driving transistor, and a second electrode connected to the anode electrode of the light emitting diode;
a fifth transistor having a gate electrode connected to a third scan line of the odd-numbered line, a first electrode connected to an initialization voltage line, and a second electrode connected to a second electrode of the driving transistor;
a sixth transistor with a gate electrode connected to the light emitting signal line, a first electrode connected to a variable voltage line, and a second electrode connected to the anode electrode of the light emitting diode;
a capacitor with one end connected to a first power line and the other end connected to the gate electrode of the driving transistor;
A light emitting display device comprising the light emitting diode, wherein an anode electrode is connected to a second electrode of the fourth transistor and a cathode electrode is connected to a second power line. According to clause 6,
The subpixels of the even lines are
A light emitting display device including the same circuit as the subpixels of the odd lines, but having only the one light emitting signal line connected in common. According to clause 6,
The types of the second to fifth transistors are
A light emitting display device different from the type of the first transistor and the sixth transistor. According to paragraph 2,
The subpixels of the odd-numbered lines and the subpixels of the even-numbered lines are
A light emitting display device that maintains an initialized state for the same amount of time before the light emitting diode emits light. A light emitting display device including a display panel including subpixels of odd lines and subpixels of even lines commonly connected to one light emitting signal line, and a driver that drives the subpixels of the odd lines and the subpixels of the even lines. In the driving method,
storing data voltage in subpixels of the odd-numbered lines for a first time;
storing a data voltage in a subpixel of the even-numbered line for a second time after the first time;
initializing nodes to which a driving current is applied to subpixels of the odd-numbered lines and subpixels of the even-numbered lines for a third time after the second time; and
A method of driving a light emitting display device comprising the step of emitting light in the subpixels of the odd-numbered lines and the subpixels of the even-numbered lines for a fourth time after the third time. According to clause 10,
The subpixels of the odd-numbered lines and the subpixels of the even-numbered lines are
A method of driving a light-emitting display device in which a section for initializing a light-emitting diode and a section for emitting light are the same. According to clause 10,
The subpixels of the odd-numbered lines and the subpixels of the even-numbered lines are
A method of driving a light emitting display device that maintains the initialization state for the same amount of time before the light emitting diode emits light.