KR20220094877A - Light Emitting Display Device and Driving Method of the same - Google Patents

Abstract

The present invention provides a light emitting display device which comprises: a display panel which displays an image; and a driving unit which drives the display panel. The display panel includes a first subpixel which emits light after receiving a data voltage, and a second subpixel which does not emit light without receiving the data voltage. A driving transistor included in the second subpixel receives a lower bias stress than a driving transistor included in the first subpixel.

Description

Light Emitting Display Device and Driving Method of the Same

The present invention relates to a light emitting display device and a driving method thereof.

With the development of information technology, the market for display devices, which is a connection medium between users and information, is growing. Accordingly, the use of display devices such as a light emitting display device, a quantum dot display device, and a liquid crystal display device is increasing.

The display devices described above include a display panel including sub-pixels, a driving unit outputting a driving signal for driving the display panel, and a power supply unit generating power to be supplied to the display panel or the driving unit, and the like.

In the above display devices, when a driving signal, for example, a scan signal and a data signal, is supplied to the sub-pixels formed on the display panel, the selected sub-pixel transmits light or directly emits light to display an image.

The present invention prevents or improves (restores) deterioration due to stress applied to a driving transistor included in a sub-pixel that does not emit light, thereby improving the optical characteristics of the display panel (flicker or afterimage). to improve lifespan. In addition, the present invention has an effect of preventing a problem that a driving transistor included in a sub-pixel that does not emit light is continuously affected by hysteresis in a specific direction when driving at a variable refresh rate (VRR).

The present invention provides a display panel for displaying an image; and a driving unit for driving the display panel, wherein the display panel includes a first sub-pixel that emits light when applied with a data voltage, and a second sub-pixel that does not emit light without being applied with a data voltage, The driving transistor included in the second sub-pixel may provide a light emitting display device that receives a lower bias stress than the driving transistor included in the first sub-pixel.

The first sub-pixel and the second sub-pixel may be positioned on different horizontal lines.

The driving transistor included in the second sub-pixel may be subjected to at least two times of first bias stress and at least one second bias stress, and the second bias stress may be a stress condition opposite to the first bias stress.

The driving transistor included in the second sub-pixel may be stressed in the order of a first bias stress, a second bias stress, and a first bias stress during a turn-off period of the emission control transistor for controlling the emission period of the light emitting diode.

A high-level initialization voltage is applied to the source electrode of the driving transistor included in the second sub-pixel during the period of receiving the first bias stress, and the source electrode of the driving transistor included in the second sub-pixel is applied to the source electrode of the driving transistor included in the second sub-pixel during the period of receiving the second bias stress. A low-level initialization voltage may be applied.

The first sub-pixel and the second sub-pixel each include a switching transistor transmitting an initialization voltage, and the switching transistor of the first sub-pixel and the switching transistor of the second sub-pixel scan the same waveform during the turn-off period of the emission control transistor. signal can be obtained.

The display panel may include a first sub-pixel and a second sub-pixel in a driving environment in which the driving frequency is changed from the first frequency to the second frequency.

In another aspect, the present invention provides a display panel for displaying an image; and a driving unit for driving the display panel, wherein the display panel includes a first sub-pixel that emits light when a data voltage is applied, and a second sub-pixel that does not emit light without receiving a data voltage, The driving transistor included in the second sub-pixel may provide a light emitting display device that receives a lower bias stress than the driving transistor included in the first sub-pixel based on the initialization voltage.

The driving transistor included in the second sub-pixel is subjected to at least two first bias stresses and at least one second bias stress in response to a change in the initialization voltage, and the second bias stress is a stress condition opposite to the first bias stress. can

The first sub-pixel and the second sub-pixel each include a switching transistor that transmits an initialization voltage to the source electrode of the driving transistor, and the switching transistor of the first sub-pixel and the switching transistor of the second sub-pixel control the emission period of the light emitting diode. The scan signal of the same waveform may be applied during the turn-off period of the light emission control transistor to be controlled.

In another aspect, the present invention may provide a method of driving a light emitting display device including a display panel for displaying an image and a driving unit for driving the display panel. In the driving method of the light emitting display device, when the driving frequency of the display panel is changed to a second frequency slower than the first frequency, the data voltage is applied and the data voltage is not applied to the driving transistor included in the first sub-pixel that emits light. The method may include controlling a driving environment so that a driving transistor included in the second sub-pixel that does not emit light is subjected to a lower bias stress.

In the controlling of the driving environment, the initialization voltage applied through the source electrode of the driving transistor included in the second sub-pixel may be varied.

The driving transistor included in the second sub-pixel is subjected to at least two first bias stresses and at least one second bias stress in response to a change in the initialization voltage, and the second bias stress is a stress condition opposite to the first bias stress. can

The controlling of the driving environment may be performed during a turn-off period of the emission control transistor for controlling the emission period of the light emitting diodes included in the first sub-pixel and the second sub-pixel, respectively.

The present invention is effective in improving the hysteresis characteristic of a driving transistor included in a sub-pixel that does not emit light. In addition, the present invention prevents or improves (restores) deterioration due to stress applied to a driving transistor included in a sub-pixel that does not emit light, thereby improving the optical characteristics of the display panel (flicker or afterimage). In addition, it has the effect of improving the lifespan. In addition, the present invention can prevent the problem that the driving transistor included in the sub-pixel that does not emit light is continuously affected by hysteresis in a specific direction when driving VRR operating at various driving frequencies from high-speed driving to low-speed driving. there is an effect

1 is a block diagram schematically showing the configuration of a light emitting display device, FIG. 2 is an exemplary configuration diagram of a device related to a gate-in-panel type scan driver, and FIG. 3 is an exemplary arrangement diagram of a gate-in-panel type scan driver.
4 is a diagram showing a part of a light emitting display device according to a first embodiment of the present invention, FIG. 5 is a diagram schematically showing a sub-pixel of FIG. 4, and FIGS. 6 to 10 are views showing a first embodiment of the present invention It is a drawing for explaining the compensation method of the light emitting display device according to the present invention.
11 is a diagram showing a part of a light emitting display device according to a second embodiment of the present invention, FIG. 12 is a diagram schematically showing the sub-pixel of FIG. 11, and FIGS. 13 to 15 are views showing a second embodiment of the present invention FIG. 16 is a diagram illustrating a waveform to help understanding related to the compensation method.
17 is a view showing a part of a light emitting display device according to a third embodiment of the present invention, FIG. 18 is a view showing the sub-pixel of FIG. 17 in detail, and FIGS. 19 to 22 are views showing a third embodiment of the present invention It is a drawing for explaining the compensation method of the light emitting display device according to the present invention.

The display device according to the present invention may be implemented as a television, an image player, a personal computer (PC), a home theater, an electric vehicle, a smart phone, and the like, but is not limited thereto. The display device according to the present invention may be implemented as a light emitting display device, a quantum dot display device, a liquid crystal display device, or the like. However, hereinafter, for convenience of explanation, a light emitting display device that directly emits light based on an inorganic light emitting diode or an organic light emitting diode will be exemplified.

In addition, in the light emitting display device described below, sub-pixels of a display panel are implemented based on (1) an n-type thin film transistor, (2) a p-type thin film transistor, or (3) a structure in which an n-type and a p-type thin film transistor are mixed. Take as an example to be

The thin film transistor is a three-electrode device including a gate, a source, and a drain. The source is an electrode that supplies a carrier to the transistor. In a thin film transistor, carriers begin to flow from the source. The drain is an electrode through which carriers exit the thin film transistor. That is, in the thin film transistor, the flow of carriers flows from the source to the drain.

In the case of the p-type thin film transistor, since carriers are holes, the source voltage is higher than the drain voltage so that holes can flow from the source to the drain. In a p-type thin film transistor, since holes flow from the source to the drain, current flows from the source to the drain. On the other hand, in the case of the n-type thin film transistor, the source voltage is lower than the drain voltage so that electrons can flow from the source to the drain because carriers are electrons. In an n-type thin film transistor, since electrons flow from the source to the drain, the current flows from the drain to the source. However, the source and drain of the thin film transistor may be changed according to an applied voltage. Reflecting this, in the following description, any one of the source and the drain will be described as the first electrode, and the other one of the source and the drain will be described as the second electrode.

1 is a block diagram schematically showing a configuration of a light emitting display device, FIG. 2 is an exemplary configuration diagram of a device related to a gate-in-panel type scan driver, and FIG. 3 is an exemplary arrangement diagram of a gate-in-panel type scan driver.

1 to 3 , the light emitting display device includes an image supply unit 110 , a timing control unit 120 , a scan driving unit 130 , a data driving unit 140 , a display panel 150 , and a power supply unit 180 . and the like.

The image supply unit 110 (or the host system) may output various driving signals together with an image data signal supplied from the outside or an image data signal stored in an internal memory. The image supply unit 110 may supply a data signal and various driving signals to the timing control unit 120 .

The timing controller 120 includes a gate timing control signal GDC for controlling the operation timing of the scan driver 130 , a data timing control signal DDC for controlling the operation timing of the data driver 140 , and various synchronization signals ( Vsync, which is a vertical sync signal, and Hsync, which is a horizontal sync signal) can be output. The timing controller 120 may supply the data signal DATA supplied from the image supplier 110 together with the data timing control signal DDC to the data driver 140 . The timing controller 120 may be formed in the form of an integrated circuit (IC) and mounted on a printed circuit board, but is not limited thereto.

The power supply unit 180 converts power supplied from the outside under the control of the timing control unit 120 into a first power supply having a high potential and a second power supply having a low potential, and a first power line (VDDEL) and a second power line ( VSSEL). The power supply unit 180 is used to drive the first power and the second power as well as a voltage required for driving the scan driver 130 (eg, a gate voltage including a gate high voltage and a gate low voltage) or a data driver 140 . A necessary voltage (a drain voltage including a drain voltage and a half-drain voltage) may be generated and output.

The data driver 140 samples and latches the data signal DATA in response to the data timing control signal DDC supplied from the timing controller 120 , and converts the digital data signal to analog data based on the gamma reference voltage. It can be converted to voltage and output. The data driver 140 may supply a data voltage to the sub-pixels included in the display panel 150 through the data lines DL1 to DLn. The data driver 140 may be formed in the form of an IC and may be mounted on the display panel 150 or mounted on a printed circuit board, but is not limited thereto.

The display panel 150 may display an image corresponding to a driving signal including at least one scan signal and a data voltage, and a first power and a second power. The sub-pixels of the display panel 150 directly emit light. The display panel 150 may be manufactured based on a substrate having rigidity or flexibility, such as glass, silicon, polyimide, or the like. In addition, the sub-pixels that emit light may include pixels including red, green, and blue or pixels including red, green, blue, and white.

The scan driver 130 may output a scan signal (or a scan voltage) in response to the gate timing control signal GDC supplied from the timing controller 120 . The scan driver 130 may supply at least one scan signal to the sub-pixels included in the display panel 150 through the gate lines GL1 to GLm. The scan driver 130 may be formed in the form of an IC or may be directly formed on the display panel 150 in a gate-in-panel method.

The gate-in-panel type scan driver 130 may include a shift register 131 and a level shifter 135 . The level shifter 135 may generate and output one or more clock signals Clks and a start signal Vst based on signals output from the timing controller 120 . The clock signals Clks may be generated and output in the form of K (K is an integer greater than or equal to 2) phases having different phases, such as two-phase, four-phase, and eight-phase.

The shift register 131 operates based on signals Clks and Vst output from the level shifter 135 and scan signals Scan[ 1] to Scan[m]) can be output. The shift register 131 is formed in the form of a thin film on the display panel 150 by a gate-in-panel method.

The shift register 131 may be generally disposed in the non-display area NA of the display panel 150 . In this case, the shift register 131 is disposed in the left and right non-display areas NA of the display panel 150 as shown in FIG. 3(a) or in the upper and lower non-display areas (NA) of the display panel 150 as shown in FIG. NA).

Meanwhile, FIG. 3 shows, as an example, that the first-side shift register 131a and the second-side shift register 131b are disposed in the non-display area NA located at the left and right sides or upper and lower sides of the display area AA. Although described, only one may be disposed on the left, right, upper or lower side. Also, the shift register 131 may be dividedly disposed in the non-display area NA and the display area AA or may be distributed in the display area AA.

In addition, the level shifter 135 may be formed in the form of an independent IC unlike the shift register 131 or may be included in the power supply unit 180 . However, this is only an example, and may be implemented in various forms, such as one or more of the timing controller 120 , the scan driver 130 , and the data driver 140 being integrated into one IC depending on the implementation method of the light emitting display device. can However, hereinafter, for convenience of description, the shift register 131 is shown and described as an example in which the shift register 131 is disposed in one non-display area NA.

4 is a diagram showing a part of a light emitting display device according to a first embodiment of the present invention, FIG. 5 is a diagram schematically showing a sub-pixel of FIG. 4, and FIGS. 6 to 10 are views showing a first embodiment of the present invention It is a drawing for explaining the compensation method of the light emitting display device according to the present invention.

4 and 5 , the shift register 131 includes a plurality of stages STG1 to STG6 and may be disposed in the non-display area NA of the display panel 150 . The plurality of stages STG1 to STG6 may output scan signals for driving the sub-pixels SP disposed in the display area AA of the display panel 150 .

For example, the first stage STG1 may output a scan signal corresponding to a first line for turning on or off a transistor included in the sub-pixels SP positioned on the first horizontal line HL1 . . The second stage STG2 may output a scan signal corresponding to a second line for turning on or off a transistor included in the sub-pixels SP positioned on the second horizontal line HL2 . In the above manner, the first stage STG1 to the sixth stage STG6 may supply the scan signal to the sub-pixels SP positioned on each of the horizontal lines HL1 to HL6.

One sub-pixel SP may be connected to the first data line DL1 , the first gate line GL1 , the first power line VDDEL, and the second power line VSSEL. The first data line DL1 is a line transmitting a data voltage, the first gate line GL1 is a line transmitting a scan signal, the first power line VDDEL is a line transmitting the first power, The second power line VSSEL is a line that transmits the second power.

One sub-pixel SP includes a switching transistor that transmits a data voltage in response to a scan signal, a capacitor that stores the data voltage, a driving transistor that generates a driving current in response to the data voltage, and a driving transistor that emits light in response to the driving current. It may include an organic light emitting diode and the like.

6 , the display panel 150 may operate only the first horizontal line HL1 and the third horizontal line HL3 to the sixth horizontal line HL6 excluding the second horizontal line HL2 . . Alternatively, only the first horizontal line HL1 and the third horizontal line HL3 to the sixth horizontal line HL6 excluding the second horizontal line HL2 may be inoperative. Also, only horizontal lines other than two or more specific horizontal lines may be operated in the display panel 150 . In addition, such a driving environment may last for at least N (N is an integer greater than or equal to 2) frame time.

On the other hand, when only the first horizontal line HL1 and the third horizontal line HL3 to the sixth horizontal line HL6 operate, the data voltage Vdata is applied to them, but the data voltage is applied to the second horizontal line HL2. It may mean that (Vdata) is not authorized.

As such, even if the data voltage Vdata is not applied to the second horizontal line HL2, the driving transistor included in the sub-pixel positioned on the corresponding line may receive bias stress depending on the circuit configuration or driving method. . In addition, when such a driving environment continues for a long time (for a number of frames), the driving transistor is affected by hysteresis in a specific direction, and thus driving characteristics (eg, threshold voltage) may change.

Accordingly, the present invention provides a driving condition that can form a bias stress opposite to the current bias stress when subjected to hysteresis in a specific direction for a long time like the driving transistor included in the sub-pixel of the second horizontal line HL2. will be.

A part related to bias stress will be dealt with in more detail below, and examples before and after application of the present invention are illustrated and described as follows. The illustration of FIG. 7 shows before application of the present invention, and the illustration of FIG. 8 shows after application of the present invention.

As can be seen in FIG. 7 , before applying the first embodiment, the driving transistor included in the sub-pixel of the first horizontal line HL1 is activated during the second period ( 2 ) and the fourth period ( 4 ). It can be subjected to bias stress. The first bias stress may be On-Bias-Stress (OBS). In addition, the driving transistor included in the sub-pixel of the second horizontal line HL2 may be subjected to on-bias stress OBS during the second period ( 2 ) to the fourth period ( 4 ).

The on-bias stress may be defined as a state in which a specific voltage is applied to a specific electrode of the driving transistor even when a driving data voltage is not applied, and thus a stress similar to the turn-on state of the driving transistor is applied. For example, when a specific voltage is applied to the source electrode of the driving transistor, the gate source voltage Vgs is formed similarly to the state in which the data voltage is applied, thereby causing stress such as the turn-on state of the driving transistor.

6 , the sub-pixel of the first horizontal line HL1 may receive on-bias stress OBS of the driving transistor due to driving as the data voltage Vdata is applied. However, the sub-pixel of the second horizontal line HL2 may receive the on-bias stress OBS of the driving transistor even when the data voltage Vdata is not applied.

As can be seen in FIG. 8 , after applying the first embodiment, the driving transistor included in the sub-pixel of the first horizontal line HL1 is subjected to on-bias stress during the second period ( 2 ) and the fourth period ( 4 ). (OBS) can be obtained. In addition, the driving transistor included in the sub-pixel of the second horizontal line HL2 is subjected to on-bias stress OBS during the second period 2 and the fourth period 4 , but is subjected to a second bias during the third period 3 . It can be stressful. The second bias stress may be reverse-bias-stress (RBS).

Reverse bias stress may be defined as applying an electric field in an opposite direction to prevent a change in hysteresis characteristics of a driving transistor under on-bias stress.

As illustrated in FIG. 9 , when the driving transistor receives only the electric field E-filed in one direction, the dipole (+, -) direction of the insulating layer INS may be continuously maintained in either direction. In addition, the driving transistor is affected by hysteresis in a specific direction, and thus driving characteristics (eg, threshold voltage) may change. However, as in the example of FIG. 10 , when an electric field E-filed is applied opposite to the direction currently being received by the driving transistor, the dipole direction of the insulating layer INS is changed from (+, -) to (-, +). can

Based on the above theory, the present invention may implement the following driving conditions in order to prevent or improve (restore) deterioration due to stress that the driving transistor of the sub-pixel that does not emit light may be subjected to.

(1) If the driving transistor is subjected to stress in a positive direction, the driving condition is changed to receive stress (or negative electric field) in a negative direction, which is opposite to this. (2) If the driving transistor is under stress in a negative direction, the driving condition is changed to receive stress (or a positive electric field) in a positive direction opposite to this.

11 is a diagram illustrating a part of a light emitting display device according to a second embodiment of the present invention, FIG. 12 is a diagram schematically illustrating a sub-pixel of FIG. 11, and FIGS. 13 to 15 are views illustrating a second embodiment of the present invention FIG. 16 is a diagram illustrating a waveform to help understanding related to the compensation method.

11 and 12 , the shift register 131 includes a plurality of stages STG1 to STG6 and may be disposed in the non-display area NA of the display panel 150 . The plurality of stages STG1 to STG6 may output scan signals for driving the sub-pixels SP disposed in the display area AA of the display panel 150 .

For example, the first stage STG1 may output a scan signal corresponding to a first line for turning on or off a transistor included in the sub-pixels SP positioned on the first horizontal line HL1 . . The second stage STG2 may output a scan signal corresponding to a second line for turning on or off a transistor included in the sub-pixels SP positioned on the second horizontal line HL2 . In the above manner, the first stage STG1 to the sixth stage STG6 may supply the scan signal to the sub-pixels SP positioned on each of the horizontal lines HL1 to HL6.

One sub-pixel SP may be connected to a first data line DL1 , a first gate line GL1 , a first power line VDDEL, a second power line VSSEL, and an initialization voltage line VINI. . The first data line DL1 is a line transmitting a data voltage, the first gate line GL1 is a line transmitting scan signals, the first power line VDDEL is a line transmitting the first power, The second power line VSSEL is a line that transmits the second power. Here, the first gate line GL1 is a first scan line SCAN1 transmitting a first scan signal, a second scan line SCAN2 transmitting a second scan signal, and a light emission control signal (signal to start light emission) It may include an emission control line (EML) that transmits the .

One sub-pixel SP includes a first switching transistor that transmits a data voltage in response to the first scan signal, a capacitor that stores the data voltage, a driving transistor that generates a driving current in response to the data voltage, and a second scan signal. It may include a second switching transistor that transmits an initialization voltage correspondingly, an emission control transistor that controls the driving transistor to generate a driving current in response to an emission control signal, and an organic light emitting diode that emits light in response to the driving current. can

13 , the display panel 150 may operate only the first horizontal line HL1 and the third horizontal line HL3 to the sixth horizontal line HL6 excluding the second horizontal line HL2 . . Alternatively, only the first horizontal line HL1 and the third horizontal line HL3 to the sixth horizontal line HL6 excluding the second horizontal line HL2 may be inoperative. Also, only horizontal lines other than two or more specific horizontal lines may be operated in the display panel 150 . In addition, such a driving environment may last for at least N (N is an integer greater than or equal to 2) frame time.

14 , the driving transistor included in the sub-pixel of the second horizontal line HL2 generates a light emission control signal EM to start light emission from a logic low (L) to a logic high (H). A reverse bias stress RBS may be applied during the third period 3 in response to the change in the scan signal SC during the period.

The driving transistor included in the sub-pixel of the second horizontal line HL2 is subjected to the on-bias stress OBS during the second period 2 and the fourth period 4, but the reverse bias stress OBS during the third period 3 RBS), the problem of changing hysteresis characteristics can be prevented. In this case, the reverse bias stress RBS may be implemented to have fewer times and shorter periods than the on bias stress OBS.

15 , the driving transistor included in the sub-pixel of the second horizontal line HL2 is a scan signal during a period in which the emission control signal EM is generated from a logic low (L) to a logic high (H). A reverse bias stress RBS may be applied during the third period 3 in response to the change in SC.

The driving transistor included in the sub-pixel of the second horizontal line HL2 is subjected to the on-bias stress OBS during the second period 2 and the fourth period 4, but the reverse bias stress OBS during the third period 3 RBS), the problem of changing hysteresis characteristics can be prevented. In this case, the reverse bias stress RBS may be embodied to have a shorter period than the on-bias stress OBS, but to have a longer period.

Meanwhile, in FIGS. 14 and 15 , a state in which the sub-pixel is not driven when the emission control signal EM is generated at a logic high (H) has been described as an example. That is, a transistor operating based on the emission control signal EM is implemented as a p-type as an example. However, this is only an example, and when the transistor operating based on the emission control signal EM is implemented as an n-type, it may occur opposite to the waveforms of FIGS. 14 and 15 . That is, when the light emission control signal EM is generated at a logic low L, a bias stress capable of preventing a problem in which the hysteresis characteristic is changed may be formed.

As shown in FIG. 16 , the driving transistor may receive on-bias stress OBS during a period in which the scan signal SC is output at logic high, and may receive reverse bias stress RBS during a period in which the scan signal SC is output at logic low. It is possible to supplement the description of the related part as follows.

When the scan signal SC as shown in FIG. 16A is applied, the driving transistor may receive both the reverse bias stress RBS and the on bias stress OBS during the third period 3 . Also, when the scan signal SC as shown in FIG. 16B is applied, the driving transistor may receive both the reverse bias stress RBS and the on-bias stress OBS during the fourth period 4 .

As such, the driving transistor receives one reverse bias stress (RBS) or one on-bias stress (OBS) and one reverse bias stress (RBS) during one period for applying a specific voltage or signal to a specific node or device. can be received together.

On the other hand, the on-bias stress OBS and the reverse bias stress RBS are not distributed at the same time and the same number of times as in FIG. 16 , but may be distributed so that one of them has a longer time and a larger number of times. In addition, although the on-bias stress OBS is first generated and then the reverse bias stress RBS is generated, and these are alternately generated at least twice, as an example, the present invention is not limited thereto. That is, the bias stress condition may be set in various forms according to the sub-pixel configuration, driving method, stress condition, and the like.

17 is a view showing a part of a light emitting display device according to a third embodiment of the present invention, FIG. 18 is a view showing the sub-pixel of FIG. 17 in detail, and FIGS. 19 to 22 are views showing a third embodiment of the present invention It is a drawing for explaining the compensation method of the light emitting display device according to the present invention.

17 , the shift register 131 includes a plurality of stages STG1 to STG6 and may be disposed in the non-display area NA of the display panel 150 . The plurality of stages STG1 to STG6 may output scan signals for driving the sub-pixels SP disposed in the display area AA of the display panel 150 .

For example, the first stage STG1 may output a scan signal corresponding to a first line for turning on or off a transistor included in the sub-pixels SP positioned on the first horizontal line HL1 . . The second stage STG2 may output a scan signal corresponding to a second line for turning on or off a transistor included in the sub-pixels SP positioned on the second horizontal line HL2 . In the above manner, the first stage STG1 to the sixth stage STG6 may supply the scan signal to the sub-pixels SP positioned on each of the horizontal lines HL1 to HL6.

One sub-pixel SP includes a first data line DL1, a first gate line GL1, a first power line VDDEL, a second power line VSSEL, a first initialization voltage line VINI, and a first sub-pixel SP. 2 may be connected to the initialization voltage line VAR. The first data line DL1 is a line transmitting a data voltage, and the first gate line GL1 is a line transmitting scan signals. The first power line VDDEL is a line transmitting the first power, and the second power line VSSEL is a line transmitting the second power. The first initialization voltage line VINI is a line transmitting the first initialization voltage, and the second initialization voltage line VAR is a line transmitting the second initialization voltage. Here, the first gate line GL1 is a first scan line SCAN1 transmitting a first scan signal, a second scan line SCAN2 transmitting a second scan signal, and a third scan signal transmitting a third scan signal. It may include a line SCAN3 and a light emission control line EML that transmits a light emission control signal.

One sub-pixel SP includes a first switching transistor T1, a capacitor CST, a driving transistor DT, a second switching transistor T2, a third switching transistor T3, and a fourth switching transistor T4. , a first emission control transistor ET1 , a second emission control transistor ET2 , and an organic light emitting diode OLED. The first transistor T1 is implemented as an n-type, and the second transistors T2 to T4, the driving transistor DT, the first emission control transistor ET1 and the second emission control transistor ET2 are It may be implemented as a p type, but is not limited thereto.

The first switching transistor T1 has a gate electrode connected to the first scan line SCAN1, a gate electrode of the driving transistor DT and a first electrode connected to the other end of the capacitor CST, and the second electrode of the driving transistor DT is connected to the first switching transistor T1. A second electrode may be connected to the second electrode. The first switching transistor T1 may serve to transfer the data voltage to the other end of the capacitor CST while turning the driving transistor DT into a diode state in response to the first scan signal.

In the second switching transistor T2 , the gate electrode is connected to the second scan line SCAN2 , the first electrode is connected to the first data line DL1 , and the second electrode is connected to the first electrode of the driving transistor DT. can The second switching transistor T2 may serve to transfer the data voltage of the first data line DL1 to the first electrode of the driving transistor DT in response to the second scan signal.

The third switching transistor T3 may have a gate electrode connected to the third scan line SCAN3, a first electrode connected to the second electrode of the driving transistor DT, and a second electrode connected to the initialization voltage line VINI. have. The third switching transistor T3 may serve to transmit the first initialization voltage to the second electrode of the driving transistor DT in response to the third scan signal.

The fourth switching transistor T4 has a gate electrode connected to the third scan line SCAN3, a first electrode connected to a second initialization voltage line VAR, and a second electrode connected to the anode electrode of the organic light emitting diode OLED. can be connected The fourth switching transistor T4 may serve to transmit the second initialization voltage to the anode electrode of the organic light emitting diode OLED in response to the third scan signal.

The capacitor CST may have one end connected to the first power line VDDEL and the other end connected to the gate electrode of the driving transistor DT and the first electrode of the first switching transistor T1 . The capacitor CST may serve to store a data voltage to be provided to the gate electrode of the driving transistor DT.

The driving transistor DT has a gate electrode connected to the other terminal of the capacitor CST and a first electrode of the first switching transistor T1, and a second electrode of the second switching transistor T2 and a first emission control transistor ET1. A first electrode is connected to the second electrode of Electrodes may be connected. The driving transistor DT may serve to generate a driving current in response to the data voltage.

The first emission control transistor ET1 has a gate electrode connected to the emission control line EML, a first electrode connected to a first power line VDDEL, and a second electrode of the second switching transistor T2 and a driving transistor ( A second electrode may be connected to the first electrode of DT). The first emission control transistor ET1 may serve to transmit the first power to the first electrode of the driving transistor DT in response to the emission control signal.

The second emission control transistor ET2 has a gate electrode connected to the emission control line EML, a first electrode connected to the second electrode of the driving transistor DT, and the second electrode and organic element of the fourth switching transistor T4. A second electrode may be connected to the anode electrode of the light emitting diode (OLED). The second emission control transistor ET2 may serve to transmit a driving current to the anode electrode of the organic light emitting diode OLED in response to the emission control signal. That is, the second emission control transistor ET2 may serve to control the emission period of the organic light emitting diode OLED.

The organic light emitting diode OLED may have an anode electrode connected to the second electrode of the fourth switching transistor T4 and a second electrode of the second emission control transistor ET2, and a cathode electrode connected to the second power line VSSEL. have. The organic light emitting diode (OLED) may serve to emit light in response to a driving current.

19 and 20 , the display panel 150 operates only the first horizontal line HL1 and the third horizontal line HL3 to the sixth horizontal line HL6 excluding the second horizontal line HL2. can do. Alternatively, only the first horizontal line HL1 and the third horizontal line HL3 to the sixth horizontal line HL6 excluding the second horizontal line HL2 may be inoperative. Also, only horizontal lines other than two or more specific horizontal lines may be operated in the display panel 150 .

In the above description, a sub-pixel (a sub-pixel that does not emit light) positioned on an inactive horizontal line may be a sub-pixel that is not refreshed because there is no change in data voltage compared to the previous frame. The sub-pixels that are not refreshed may not receive a data voltage from the data driver to maintain the same state as before for a predetermined time (or a predetermined frame).

The above driving environment is at least N (N is an integer greater than or equal to 2) in a state in which the driving frequency of the display panel 150 is switched from the first frequency (faster frequency compared to the second frequency) to the second frequency (lower frequency compared to the first frequency). ) is an example when it lasts longer than the frame time. The driving frequency of the display panel 150 may be switched from the second frequency to the third frequency (faster frequency compared to the first frequency) or the fourth frequency (slower frequency compared to the second frequency).

As described above, a function of allowing the display panel 150 to operate at various driving frequencies from high-speed driving to low-speed driving is referred to as a variable refresh rate (VRR). High-speed driving can realize a smoother screen compared to normal driving, and low-speed driving can reduce unnecessary power consumption compared to normal driving.

However, in order to implement low-speed driving, it may be necessary to use a driving method in which a specific voltage is applied to the source electrode of the driving transistor. In this case, the driving transistor may be subjected to on-bias stress similar to the turn-on state of the driving transistor even if no data voltage is applied.

18 and 21 , the sub-pixels of the first horizontal line HL1 may perform an operation of emitting light (image display operation) based on the written data voltage Vdata. When the sub-pixels of the first horizontal line HL1 emit light, the emission control signal EM, the first scan signal SC1, the second scan signal SC2, and the third scan signal SC3 ) and the change of the first initialization voltage DVINI by period will be described as follows. For reference, since the first emission control transistor ET1 and the second emission control transistor ET2 are implemented as p-type, they may be turned on when the emission control signal EM is applied to the logic low L. That is, the first emission control transistor ET1 and the second emission control transistor ET2 may be turned on only during the first period ( 1 ) and the seventh period ( 7 ).

The light emission control signal EM is applied at a logic low (L) during the first period ( 1 ) and the seventh period ( 7 ) and is applied at a logic high (H) during the second period ( 2 ) to the sixth period ( 6 ). can be The first scan signal SC1 is applied as a logic low (L) during the first period ( 1 ) to the third period ( 3 ), the sixth period ( 6 ), and the seventh period ( 7 ), and is applied to the fourth period ( 4 ). and logic high (H) for the fifth period (5). The second scan signal SC2 is applied at a logic low (L) during the first period ( 1 ) to the fourth period ( 4 ), the sixth period ( 6 ) and the seventh period ( 7 ), and is applied to the fifth period ( 5 ). It may be applied to logic high (H) during the period. The third scan signal SC3 is applied as a logic low (L) during the second period ( 2 ), the fourth period ( 4 ), and the sixth period ( 6 ), and is applied to the first period ( 1 ) and the third period ( 3 ). , may be applied to a logic high (H) during the fifth period ( 5 ) and the seventh period ( 7 ). The first initialization voltage DVINI is applied at a low level (low voltage) during the first period (1), the third period (3) to the fifth period (5) and the seventh period (7), and the second period (2) , may be applied at a high level (high voltage) during the fourth period 4 and the sixth period 6 .

Under the above operating conditions, the driving transistor DT included in the sub-pixel of the first horizontal line HL1 is applied through the third switching transistor T3 during the second period 2 and the sixth period 6 . The on-bias stress OBS may be applied due to the influence of the high level (high voltage) of the first initialization voltage DVINI.

Unlike the sub-pixel of the first horizontal line HL1 , the sub-pixel of the second horizontal line HL2 may not perform an operation of emitting light (no image display operation) as the data voltage Vdata is not written. . When the sub-pixel of the second horizontal line HL2 does not emit light, the emission control signal EM, the first scan signal SC1, the second scan signal SC2, and the third scan signal SC3) and the change of the first initialization voltage DVINI by period will be described as follows.

The light emission control signal EM is applied at a logic low (L) during the first period ( 1 ) and the seventh period ( 7 ) and is applied at a logic high (H) during the second period ( 2 ) to the sixth period ( 6 ). can be The first scan signal SC1 may be applied at a logic low (L) during the first period ( 1 ) to the seventh period ( 7 ). The second scan signal SC2 may be applied at a logic high (H) during the first period ( 1 ) to the seventh period ( 7 ). The third scan signal SC3 is applied as a logic low (L) during the second period ( 2 ), the fourth period ( 4 ), and the sixth period ( 6 ), and is applied to the first period ( 1 ) and the third period ( 3 ). , may be applied at a logic high (H) during the fifth period ( 5 ) and the seventh period ( 7 ). The first initialization voltage DVINI is applied at a low level (low voltage) during the first period (1), the third period (3) to the fifth period (5) and the seventh period (7), and the second period (2) , may be applied at a high level (high voltage) during the fourth period 4 and the sixth period 6 .

Under the above operating conditions, the driving transistor DT included in the sub-pixel of the second horizontal line HL2 is also applied through the third switching transistor T3 during the second period 2 and the sixth period 6 . The on-bias stress OBS may be received under the influence of the first initialization voltage DVINI.

However, since the reverse bias stress RBS opposite to the on-bias stress OBS is applied during the fourth period 4 in response to the driving method of the present invention, deterioration due to the stress of the driving transistor DT is prevented or improved. It can be (recovered).

On the other hand, as can be seen by comparing the level of the voltage with the waveform of the signal applied to the sub-pixel of the first horizontal line HL1 and the voltage applied to the sub-pixel of the second horizontal line HL2, the fourth period ( The first scan signal SC1 and the second scan signal SC2 during 4) and the fifth period 5 may be different. However, the emission control signal EM, the third scan signal SC3, and the first initialization voltage DVINI may be the same.

Referring to FIG. 22 , changes in the third scan signal SC3 and the first initialization voltage DVINI before and after the application of the third embodiment can be seen in more detail. 22 , before the present invention is applied, the driving transistor included in the sub-pixel of the second horizontal line HL2 has a high level (high voltage) during the second period ( 2 ) to the sixth period ( 6 ). The on-bias stress OBS may be applied for a long time by the first initialization voltage DVINI. On the other hand, after applying the present invention, the driving transistor included in the sub-pixel of the second horizontal line HL2 is at a low level (low voltage) during the fourth period 4 between the second period 2 and the sixth period 6 . A reverse bias stress RBS may be received by the first initialization voltage DVINI of .

As can be seen by comparing the before and after application of the third embodiment, the sub-pixels of the second horizontal line HL2 do not emit light, but on the first horizontal line that emits light. A bias stress lower than that of the driving transistor DT included in the sub-pixel of HL1 may be applied. The reason is that the sub-pixel of the second horizontal line HL2 receives less on-bias stress OBS than the sub-pixel of the first horizontal line HL1 because a reverse bias stress RBS condition is added.

Hereinafter, to apply the reverse bias stress RBS to the driving transistor DT, the third scan signal SC3 controlling the third switching transistor T3 and the first first initialization voltage line VINI The change of the initialization voltage is as follows.

The third scan signal SC3 is maintained at a logic low (L) for the second period (2) to the sixth period (6), but is logic high (H) for the third period (3) to the fifth period (5), It varies in the order of logic low (L) and logic high (H). Accordingly, the operating conditions of the third switching transistor T3 may be changed in the order of turn-off, turn-on, and turn-off instead of maintaining the turned-on state during the second period ( 2 ) to the sixth period ( 6 ).

In addition, although the level of the first initialization voltage DVINI is maintained at a high level (high voltage) during the second period ( 2 ) to the sixth period ( 6 ), the third switching transistor T3 is turned off, turned on, and then turned off The level of the first initialization voltage DVINI is changed from a high level (high voltage) to a low level (low voltage) during the third period (3) to the fifth period (5). Accordingly, the first initialization voltage DVINI changed to a low level may be applied to the source electrode of the driving transistor DT through the turned-on third switching transistor T3 .

When viewed from the source electrode (source node) of the driving transistor DT due to the change in the driving condition as described above, the first initialization voltage DVINI at a high level (high voltage) during the second period ( 2 ) and the sixth period ( 6 ) , but may receive reverse bias stress RBS by the first initialization voltage DVINI of a low level (low voltage) during the fourth period 4 .

Therefore, when the third embodiment is applied, the driving transistor DT is a driving environment in which a bias stress in a specific direction is continuously applied for a long time in a non-operational state in which no data voltage is applied (a non-operational state in which a driving current is not generated). can get away from

The present invention is effective in improving the hysteresis characteristic of a driving transistor included in a sub-pixel that does not emit light. In addition, the present invention prevents or improves (restores) deterioration due to stress applied to a driving transistor included in a sub-pixel that does not emit light, thereby improving the optical characteristics of the display panel (flicker or afterimage). In addition, it has the effect of improving the lifespan. In addition, the present invention can prevent the problem that the driving transistor included in the sub-pixel that does not emit light is continuously affected by hysteresis in a specific direction when driving VRR operating at various driving frequencies from high-speed driving to low-speed driving. there is an effect

130: scan driver 140: data driver
150: display panels HL1 to HL6: first to sixth horizontal lines
DT: drive transistor OBS: on-bias stress
EM: light emission control signal T3: third switching transistor
ET1: first emission control transistor ET2: second emission control transistor
RBS: Reverse Bias Stress

Claims (14)

a display panel for displaying an image; and
a driving unit for driving the display panel;
The display panel includes a first sub-pixel that emits light when applied with a data voltage, and a second sub-pixel that does not emit light without being applied with the data voltage;
The driving transistor included in the second sub-pixel receives a lower bias stress than the driving transistor included in the first sub-pixel. According to claim 1,
The first sub-pixel and the second sub-pixel are
Light emitting display devices positioned on different horizontal lines. According to claim 1,
The driving transistor included in the second sub-pixel is
The light emitting display device is subjected to at least two times of first bias stress and at least one second bias stress, wherein the second bias stress is a stress condition opposite to the first bias stress. 4. The method of claim 3,
The driving transistor included in the second sub-pixel is
A light emitting display device that is subjected to stress in the order of the first bias stress, the second bias stress, and the first bias stress during a turn-off period of a light emission control transistor for controlling a light emission period of the light emitting diode. 5. The method of claim 4,
A high-level initialization voltage is applied to the source electrode of the driving transistor included in the second sub-pixel during the period subjected to the first bias stress;
a low-level initialization voltage is applied to the source electrode of the driving transistor included in the second sub-pixel during the period of receiving the second bias stress. 6. The method of claim 5,
The first sub-pixel and the second sub-pixel are
Each of the switching transistors for transferring the initialization voltage,
The switching transistor of the first sub-pixel and the switching transistor of the second sub-pixel receive a scan signal of the same waveform during a turn-off period of the emission control transistor. According to claim 1,
The display panel is
A light emitting display device comprising the first sub-pixel and the second sub-pixel in a driving environment in which a driving frequency is changed from a first frequency to a second frequency. a display panel for displaying an image; and
a driving unit for driving the display panel;
the display panel includes a first sub-pixel that emits light upon receiving a data voltage, and a second sub-pixel that does not emit light without receiving the data voltage;
The driving transistor included in the second sub-pixel receives a lower bias stress than the driving transistor included in the first sub-pixel based on the initialization voltage. 9. The method of claim 8,
The driving transistor included in the second sub-pixel is
The light emitting display device is subjected to at least two first bias stresses and at least one second bias stress in response to the change in the initialization voltage, wherein the second bias stress is a stress condition opposite to the first bias stress. 10. The method of claim 9,
The first sub-pixel and the second sub-pixel are
Each of the switching transistors for transmitting the initialization voltage to the source electrode of the driving transistor,
The switching transistor of the first sub-pixel and the switching transistor of the second sub-pixel receive a scan signal having the same waveform during a turn-off period of the emission control transistor for controlling the emission period of the light emitting diode. A method of driving a light emitting display device comprising a display panel for displaying an image and a driving unit for driving the display panel, the method comprising:
When the driving frequency of the display panel is changed to a second frequency slower than the first frequency, the display panel does not emit light without receiving the data voltage compared to the driving transistor included in the first sub-pixel that emits light after being applied with the data voltage. A method of driving a light emitting display device comprising: controlling a driving environment so that a driving transistor included in the second sub-pixel is subjected to a lower bias stress. 12. The method of claim 11,
The step of controlling the driving environment is
A method of driving a light emitting display device for varying an initialization voltage applied through a source electrode of a driving transistor included in the second sub-pixel. 13. The method of claim 12,
The driving transistor included in the second sub-pixel is
A method of driving a light emitting display device in which at least two first bias stresses and at least one second bias stress are applied in response to the change in the initialization voltage, and the second bias stress is a stress condition opposite to the first bias stress. 14. The method of claim 13,
The step of controlling the driving environment is
A method of driving a light emitting display device performed during a turn-off period of an emission control transistor for controlling emission periods of light emitting diodes included in the first sub-pixel and the second sub-pixel, respectively.

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