KR20110077108A - Shift register and display device using the same - Google Patents

Abstract

PURPOSE: A shift register and a display device using the same are provided to prevent an error of transferring a carry signal between stages when stack lines are a short circuit. CONSTITUTION: In a shift register and a display device using the same, a plurality of gate shift clocks are delayed successively. A plurality stages are a gate start pulse, a gate high voltage, and a gate low voltage which higher than the gate high voltage. The stages output a carry signal through a first output node and a scan pulse through a second output node.

Description

SHIFT REGISTER AND DISPLAY DEVICE USING THE SAME}

The present invention relates to a shift register and a display device using the same.

Various flat panel displays (FPDs) that can reduce weight and volume, which are disadvantages of cathode ray tubes, have been developed and marketed. Generally, the scan driving circuit of the flat panel display device sequentially supplies scan pulses to scan lines using a shift register.

The shift register of the scan driving circuit includes stages STn-1 to STn + 2 including a plurality of thin film transistors (“TFTs”) as shown in FIG. 1. The stages are cascaded to sequentially generate outputs Vout (n-1) to Vout (n + 2). In FIG. 1, "C1 to C4" are four phase clocks supplied to the stages.

Each of the stages STn-1 to STn + 2 includes a Q node for controlling a pull-up transistor and a Q bar (QB) node for controlling a pull-down transistor. . In addition, each of the stages STn-1 to STn + 2 fills the Q node and QB node voltages in response to a carry signal input from a previous stage, a carry signal input from a next stage, and a clock signal C1 to C4. Switch circuits for discharging.

The outputs Vout (n-1) to Vout (n + 2) of the stages STn-1 to STn + 2 of the shift register are scan pulses applied to the scan lines of the display device, and at the same time as the previous stages. It also serves as a carry signal to the next stage. Therefore, as shown in FIG. 1, the scan lines connected to the output nodes of the stages STn-1 to STn + 2 are different from the scan lines or DC voltage sources VDD and VSS mixed by the conductive particles CP or the pattern defect. If the circuit is shorted, the shift register malfunctions because carry signals are not transmitted. For example, as illustrated in FIG. 1, when an n th scan line connected to an output node of an nth (n is positive integer) stage STn and an n + 1 scan line connected to an output node of an n + 1th stage are shorted, Stages after the nth stage STn may not operate normally.

The present invention provides a shift register and a display device using the same to prevent a carry signal transfer error between stages even when scan lines of the display device are shorted.

In one aspect of the present invention, a shift register of the present invention includes a plurality of gate shift clocks, a gate start pulse, a gate high voltage, and a gate low voltage lower than the gate high voltage, which are sequentially delayed, and are connected in a dependent manner. Stages.

The n th (n is positive integer) stage may include: a first output node connected to the n th scan line to output an n th scan pulse; A second output node for outputting an n-th carry signal to be input to the reset terminal of the n-2th stage and the start terminal of the n + 1th stage; A first pull-up transistor turned on according to a voltage of a first Q node to supply an n-th gate shift clock to the first output node to charge the first output node; A second pull-up transistor turned on according to a voltage of a second Q node to supply the n-th gate shift clock to the second output node to charge the second output node; A first pull-down transistor turned on according to a voltage of a QB node to which an n + 1 gate shift clock is applied to supply the gate low voltage to a first output node to discharge the first output node; A second pull-down transistor turned on according to the voltage of the QB node to supply the gate low voltage to a second output node to discharge the second output node; And charging the Q nodes in response to an n-1 gate shift clock and an n-1 carry signal input from an n-1th stage, and input from an n + 1 gate shift clock and an n + 2 stage. And a switch circuit for discharging the Q nodes in response to an n-2th carry signal.

According to an exemplary embodiment of the present invention, a display device includes: a display panel including a plurality of pixels in which data lines and scan lines intersect and are arranged in a matrix; A data driver circuit for supplying a data voltage to the data lines; And a scan driving circuit for sequentially supplying scan pulses to the scan lines through the shift register.

According to the present invention, the carry signal and the scan pulse are separated and output at each stage, thereby preventing malfunction of the shift register even when the scan lines of the display device are shorted.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like numbers refer to like elements throughout. In the following description, when it is determined that a detailed description of known functions or configurations related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

The names of the components used in the following description are selected in consideration of the ease of preparation of the specification, and may be different from the names of the actual products.

2 is a view schematically showing a shift register configuration according to an embodiment of the present invention. FIG. 3 is a circuit diagram illustrating in detail a circuit configuration of an nth stage illustrated in FIG. 2.

2 and 3, a shift register according to an embodiment of the present invention includes a plurality of stages ST (n-2) to ST (n + 2) that are connected in a cascade manner.

Four-phase gate shift clocks clk1 to shifted by a predetermined phase difference in the stages ST (n-2) to ST (n + 2) and swinging between the gate high voltage VGH and the gate low voltage VGL. Three gate shift clocks are input during clk4). In addition, the gate high voltage VGH and the gate low voltage VGL are supplied to the stages ST (n-2) to ST (n + 2). The gate high voltage VGH is set to a voltage higher than or equal to the threshold voltages of the TFTs formed in the TFT array of the display device, and the gate low voltage VGL is set to a voltage smaller than the threshold voltage of the TFTs formed in the TFT array of the display device. The gate high voltage VGH may be set to about 20V, and the gate low voltage VGL may be set to about −5V.

Each of the stages ST (n-2) to ST (n + 2) separately outputs a carry signal Cout and a scan pulse (or gate pulse Gout). That is, the output nodes of the stages ST (n-2) to ST (n + 2) are the first output node to which the scan pulse Gout is output and the second output node to which the carry signal Cout is output. Divided.

At the start terminal start of the nth stage ST (n), the n-1th carry signal Cout (n) output from the gate start pulse GSP or the n-1th stage ST (n-1). -1)) is input. The n-1th carry signal Cout output from the gate start pulse GSP and / or the n + 2th stage ST (n + 2) to the reset terminal reset of the nth stage ST (n). (n + 2) is input The n-th carry signal Cout (n) output from the n-th stage ST (n) is connected to the reset terminal terminal of the n-th stage ST (n-2). The carry signals Cout (n-1) and Cout (n) are input to the start terminal of the n + 1th stage ST (n-1) in FIG. The carry signals other than +2)) and the gate start pulse GSP are omitted. The carry signal transmission and the gate start pulse GSP of the stages ST (n-2) to ST (n + 2) are omitted. 5a to 6 are the same.

The circuit configuration of the nth stage ST (n) is shown in FIG. The circuit configuration of each of the stages ST (n-2) to ST (n + 2) is substantially the same as in FIG. The n-th to n-th gate shift clocks clk (n-1) to clk (n + 1) are input to the clock terminals of the n-th stage ST (n).

The n th stage ST (n) is connected to an n th scan line and outputs a first output node to which an n th scan pulse Gout (n) is output, and a reset terminal of the n th stage ST (n-2). The second output node to which the n-th carry signal to be input to the reset terminal and the start terminal start of the n + 1th stage ST (n + 1) is output according to the voltage of the first Q node q. Turn on according to the voltages of the first pull-up transistor T4 and the second Q node qc that are turned on to supply the n-th gate shift clock clk (n) to the first output node to charge the first output node. A second pull-up transistor T4C that is turned on to supply the n-th gate shift clock clk (n) to the second output node to charge the second output node, and the n + 1 gate shift clock clk (n + 1) ) Is turned on according to the voltage of the QB node qb to which the first pull-down transistor T5 and QB node qb supply the gate low voltage VGL to the first output node to discharge the first output node. Turn on depending on the voltage A second pull-down transistor T5C for supplying the gate low voltage VGL to the second output node to discharge the second output node, and the n-1 gate shift clock clk (n-1) and n-1 The Q nodes q and qc are charged in response to the n-1th carry signal Cout (n-1) input from the stage ST (n-1), and the n + 1th gate shift clock clk is charged. Q nodes q and qc are discharged in response to an n + 2th carry signal Cout (n + 2) input from (n + 1)) and an n + 2th stage ST (n + 2). And a switch circuit, which switches the first Q node q in response to the n-th carry signal Cout (n-1) and the n-th gate shift clock clk (n-1). A first Q node charging circuit for charging, a second Q node charging circuit for charging the second Q node qc in response to the n-1 gate shift clock clk (n-1), and an n + 2 carry And a Q node discharge circuit for discharging the Q nodes q and qc in response to the signal Cout (n + 2). The TFTs T1 to T5C illustrated in FIG. 3 are implemented with an n-type MOS TFT (Metal Oxide Semiconductor TFT). The TFTs T1 to T5C are not limited to n-type MOS TFTs but may be implemented as p-type MOS TFTs.

The first Q node charging circuit includes first and second TFTs T1 and T2. The first and second TFTs T1 and T2 respond to the first Q node in response to the n−1 th carry signal Cout (n−1) and the n−1 th gate shift clock clk (n−1). q) is charged. The first TFT T1 charges the first Q node q at the gate high voltage VGH in response to the n−1 th carry signal Cout (n−1). The n−1 th carry signal Cout (n−1) is applied to the gate electrode of the first TFT T1, and a gate high voltage VGH is applied to the source electrode of the first TFT T1. The drain electrode of the first TFT T1 is connected to the first Q node q. The second TFT T2 receives the first Q by the gate start pulse GSP or the n-1th carry signal Cout (n-1) in response to the n−1th gate shift clock clk (n−1). Charge node (q). The n-th gate shift clock clk (n-1) is applied to the gate electrode of the second TFT T2 via the qk node, and the gate start pulse GSP is applied to the source electrode of the second TFT T2. Alternatively, the n−1 th carry signal Cout (n−1) is applied. The drain electrode of the second TFT T2 is connected to the first Q node q.

The second Q node charging circuit includes a second C TFT (T2C). The second C TFT (T2C) is supplied through the first Q node q in response to the n-1 gate shift clock clk (n-1), and the n-1 carry signal Cout (n-1). ) Charges the second Q node qc. The n-th gate shift clock clk (n-1) is applied to the gate electrode of the second C TFT (T2C) via the qk node. The source electrode of the second TFT T2 is connected to the first Q node q, and the drain electrode of the second TFT T2 is connected to the second Q node qc. When the n th scan line connected to the second output node is shorted to another scan line, the first Q node q is not bootstrapping. The second C TFT T2C does not affect the bootstrapping of the second Q node qc even if the first Q node q is not bootstrapping due to a short circuit of the nth scan line. The first Q node q and the second second Q node qc are separated for a time other than the time at which the pulse of clk (n-1) is input.

The Q node discharge circuit includes third and third C TFTs (T3, T3C). The third TFT T3 discharges the first Q node q in response to the n + 2th carry signal Cout (n + 2). The n + 2th carry signal Cout (n + 2) is applied to the gate electrode of the third TFT T3. The gate low voltage VGL is applied to the source electrode of the third TFT T3. The drain electrode of the third TFT T3 is connected to the first Q node q. The third C TFT (T3C) discharges the second Q node qc in response to the n + 2th carry signal Cout (n + 2). The n + 2th carry signal Cout (n + 2) is applied to the gate electrode of the 3C TFT (T3C). The gate low voltage VGL is applied to the source electrode of the 3C TFT (T3C). The drain electrode of the 3C TFT (T3C) is connected to the second Q node qc.

The pull-up transistor includes fourth and fourth C TFTs T4 and T4C. The fourth TFT T4 charges the first output node with the nth gate shift clock clk (n) by bootstrapping the nth gate shift clock clk (n) and the first Q node q. Rise the scan pulse Gout (n). The gate electrode of the fourth TFT T4 is connected to the first Q node q. The source electrode of the fourth TFT T4 is connected to the first output node. The nth gate shift clock clk (n) is applied to the drain electrode of the fourth TFT T4. The fourth C TFT T4C charges the second output node with the n th gate shift clock clk (n) by bootstrapping the n th gate shift clock clk (n) and the second Q node qc. The carry signal Cout (n) is raised. The gate electrode of the fourth C TFT (T4C) is connected to the second Q node qc. The source electrode of the fourth C TFT (T4C) is connected to the second output node. An nth gate shift clock clk (n) is applied to the drain electrode of the fourth C TFT (T4C).

The pull-down transistor includes fifth and fifth C TFTs (T5, T5C). The n + 1 th gate shift clock clk4 is directly applied to the QB node qb. The fifth TFT T5 discharges the first output node in response to the voltage of the QB node qb. The gate electrode of the fifth TFT T5 is connected to the QB node qb, and the drain electrode of the fifth TFT T5 is connected to the first output node. The gate low voltage VGL is supplied to the source electrode of the fifth TFT T5. The fifth C TFT (T5C) discharges the second output node in response to the voltage of the QB node qb. The gate electrode of the fifth C TFT (T5C) is connected to the QB node qb, and the drain electrode of the fifth C TFT (T5C) is connected to the second output node. The gate low voltage VGL is supplied to the source electrode of the fifth C TFT T5C.

The operation of the nth stage ST (n) will be described step by step with reference to the waveform diagram of FIG. 4.

3 and 4, an n + 2 th gate shift clock clk (n + 2) is generated at a time T1. In the Q node discharge circuit, the third and third C TFTs (T3 and T3C) respond to the n + 2 gate shift clock (clk (n + 2)) at the time T1, and the first and second Q nodes q and qc. Is discharged to maintain the voltages of the first and second Q nodes q and qc in the pull-up transistors T4 and T4C.

During the T2 time, the n-th gate shift clock clk (n-1) is generated, and the n-th carry signal Cout (n-1) starts from the n-th stage n-1. The signal is input to the start terminal start of the nth stage ST (n). During the time T2, the first TFT T1 is turned on in response to the n-1th carry signal Cout (n-1), and the second and second C TFTs T2 and T2C are nth-1. It is turned on in response to the voltage of the qk node raised to the gate high voltage VGH of the gate shift clock clk (n-1). Accordingly, the voltages of the first and second Q nodes q and qc rise to the gate high voltage VGH during the T2 period to turn on the pull-up transistors T4 and T4C. During the T2 period, the voltage of the nth gate shift clock signal line maintains the gate low voltage VGL. Accordingly, the pull-up transistors T4 and T4C are turned on at the time T2, but the voltage of the output nodes maintains the gate low voltage VGL.

During the T3 time, the nth gate shift clock clk (n) is generated. During the T3 time, the n-th gate shift clock clk (n) is applied to the drain electrodes of the pull-up transistors T4 and T4C, and the parasitic capacitance between the gate-drain electrodes of the pull-up transistors T4 and T4C is applied. Bootstrapping the first and second Q nodes q and qc further increases the voltage of the first and second Q nodes q and qc. Therefore, at the time T3, the voltage of the first output node rises to the gate high voltage VGH to rise the nth scan pulse Gout (n), and the voltage of the second output node rises to the gate high voltage VGH. To raise the nth carry signal Cout (n). The nth carry signal Cout (n) is the reset terminal reset of the n-2th stage ST (n-2) and the start terminal start of the n + 1st stage ST (n + 1) at time T3. ) Is entered.

During the T4 time, the n + 1 th gate shift clock clk (n + 1) is generated. During the time T4, the voltage of the QB node qb rises to the gate high voltage VGH of the n + 1 th gate shift clock clk (n + 1). During the T4 time, the gate low voltage VGL is applied to the drain electrodes of the pull-up transistors T4 and T4C. Pull-down transistors T5 and T5C are turned on in response to the voltage of QB node qb to discharge the voltages of the first and second output nodes. Therefore, at the time T4, the voltage of the first output node drops to the gate low voltage VGL to poll the nth scan pulse Gout (n), and the voltage of the second output node drops to the gate low voltage VGL. The nth carry signal Cout (n) is polled.

During the time T5, the n + 2 th gate shift clock clk (n + 2) is generated. At the same time, the n + 2th carry signal Cout (n + 2) generated from the n + 2th stage ST (n + 2) is applied to the reset terminal reset of the nth stage ST (n). Is entered. During the time T5, the third and third C TFTs T3 and T3C are turned on in response to the n + 2th carry signal Cout (n + 2) to thereby first and second Q nodes q and qc. ) Is discharged to the gate low voltage VGL. The voltage at QB node qb maintains the gate low voltage for T5 time. The pull-up transistors T4 and T4C and the pull-down transistors T5 and T5C are turned off because the voltages of the Q nodes q and qc and QB node qb are discharged to the gate low voltage VGL during the time T5. Hold to float the first and second output nodes. Accordingly, the voltages of the first and second output nodes maintain the gate low voltage VGL for the time T5.

The shift register of the present invention is composed of m stages for sequentially supplying scan pulses to m scan lines, and two dummy stages not connected to the scan lines. 5A and 5B illustrate stage configurations of a shift register when 'm' is 640. FIG. FIG. 6 is a waveform diagram showing input and output signals of the shift register shown in FIGS. 5A and 5B.

5A to 6, the shift register according to the present invention includes 640 stages ST1 to ST640 for sequentially supplying scan pulses to 640 scan lines, and two dummy lines not connected to the scan lines. It consists of stages DST641 and DST642.

Each of the stages ST1 to ST642 has three clock terminals to which n-th to n-th gate shift clocks clk (n-1), clk (n), and clk (n + 1) are input. And a first output terminal connected to the first output node to output the scan pulse Gout (n), and a second output terminal connected to the second output node to output the carry signal Cout (n). . In addition, each of the stages ST1 to ST642 includes a start terminal where a gate start pulse GSP or an n-1th carry signal Cout (n-1) is input as a start pulse, and a gate start pulse GSP. And / or a reset terminal to which the n + 2th carry signal Cout (n + 2) is input as a reset signal.

The gate start pulse GSP is input to the start terminal start of the first stage ST1. The n-1 th carry signal Cout (n-1) is input to the start terminal start of the second to 642th stages ST2 to DST642. The start terminal start of the stages ST1 to ST642 is connected to the gate electrode of the first TFT T1 and the source electrode of the second TFT T2 as shown in FIG. 3.

The third carry signal, that is, the n + 2th carry signal Cout (n + 2), is input to the reset terminal reset of the first stage ST1. The gate start pulse GSP and the n + 2th carry signal Cout (n + 2) are input to the reset terminals reset of the second to 640th stages ST2 to ST640 through the OR gate. The gate start pulse GSP is input to the reset terminals reset of the dummy stages DST641 and DST642. The reset terminals reset of the stages ST1 to DST642 are connected to the gate electrodes of the third and third c TFTs T3 and T3C as shown in FIG. 3. Therefore, the first stage ST1 is reset by the n + 2th carry signal Cout (n + 2), and the second to 640th stages ST2 to ST640 are the gate start pulse GSP and the n ++ th stage. It is reset by two carry signals Cout (n + 2). The dummy stages ST641 and ST642 are input by the gate start pulse GSP. The gate start pulse GSP is generated once at the start of the frame period for one frame period. When the gate start pulse GSP is generated, the Q nodes q and qc of the first stage ST1 are charged to the gate high voltage VGH, and the Q nodes q, of the remaining stages ST2 to ST642. qc) is discharged and initialized.

The display device of the present invention includes any display device which sequentially supplies scan pulses to the scan lines and writes video data to the pixels by line sequential scanning. For example, the display device of the present invention may be any one of a liquid crystal display (LCD), an organic light emitting diode display (OLED), and an electrophoresis display device (EPD). .

7 is a block diagram schematically illustrating a display device according to an exemplary embodiment of the present invention.

Referring to FIG. 7, the display device of the present invention includes a display panel 10, a data driving circuit, a scan driving circuit, a timing controller 11, and the like.

The display panel 10 includes data lines and scan lines that cross each other and pixels arranged in a matrix form. The display panel 10 may be implemented by any one of a liquid crystal display (LCD), an organic light emitting diode display (OLED), and an electrophoretic display (EPD).

The data driver circuit includes a plurality of source drive ICs 12. The source drive ICs 12 receive digital video data RGB from the timing controller 11. The source drive ICs 12 convert the digital video data RGB into a gamma compensation voltage in response to a source timing control signal from the timing controller 11 to generate a data voltage, and synchronize the data voltage with a scan pulse. The data lines of the display panel 10 may be supplied to each other. The source drive ICs may be connected to data lines of the display panel 10 by a chip on glass (COG) process or a tape automated bonding (TAB) process.

The scan driving circuit includes a level shifter 15 and a shift register 13 connected between the timing controller 11 and the scan lines of the display panel 10.

As shown in FIG. 8, the level shifter 15 converts the TTL logic level voltages of the four-phase gate shift clocks clk1 to clk4 input from the timing controller 11 to the gate high voltage VGH and the gate. Level shift to the low voltage (VGL). The level shifter 15 may down-modulate the gate high voltage VGH at the falling edge of the gate shift clocks clk1 to clk4 in response to the FLK signal input from the timing controller 11. In FIG. 8, "GPM" is the gate shift clocks clk1 to clk4 in which the gate high voltage VGH is modulated according to the FLK signal. When the gate high voltage VGH is down-modulated at the falling edges of the gate shift clocks clk1 to clk4, the waveform of the scan pulse supplied to the scan lines of the display panel 10 through the shift register 13 is also gate shifted. It is modulated in the same form as the clocks clk1 to clk4. When the gate high voltage is lowered at the falling edge of the scan pulses supplied to the scan lines, the kickback voltage ΔVp may be reduced in the liquid crystal display, thereby improving flicker, afterimage, and color deviation.

The shift register 13 shifts the gate start pulse GSP according to the gate shift clocks clk1 to clk4 as described above to sequentially output the carry signal Cout (n) and the scan pulse Gout (n). It consists of stages.

The scan driving circuit may be directly formed on the lower substrate of the display panel 10 using a gate in panel (GIP) method, or may be connected between the gate lines of the display panel 10 and the timing controller 11 in a TAB method. In the GIP method, the level shifter 15 may be mounted on the PCB 14, and the shift register 13 may be formed on the lower substrate of the display panel 10.

The timing controller 11 receives digital video data RGB from an external host computer through an interface such as a Low Voltage Differential Signaling (LVDS) interface and a Transition Minimized Differential Signaling (TMDS) interface. The timing controller 11 transmits digital video data RGB input from the host computer to the source drive ICs 12.

The timing controller 11 uses the LVDS or TMDS interface receiving circuit to control the timing of the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the data enable signal Data Enable, and the main clock MCLK. Receive a signal. The timing controller 11 generates timing control signals for controlling the operation timing of the data driving circuit and the scan driving circuit based on the timing signal from the host computer. The timing control signals include a scan timing control signal for controlling the operation timing of the scan driving circuit, and a data timing control signal for controlling the operation timing of the source drive ICs 12 and the polarity of the data voltage.

The scan timing control signal includes a gate start pulse GSP, gate shift clocks clk1 to clk4, and a gate output enable signal GOE (not shown). The gate start pulse GSP is input to the shift register 13 to control the shift start timing. The gate shift clocks clk1 to clk4 are input to the level shifter 13, level shifted, and then input to the shift register 13, and are used as clock signals for shifting the gate start pulse GSP. The gate output enable signal GOE controls the output timing of the shift register 13.

The data timing control signal includes a source start pulse (SSP), a source sampling clock (SSC), a polarity control signal (Polarity, POL), a source output enable signal (Source Output Enable, SOE), and the like. It includes. The source start pulse SSP controls the shift start timing of the source drive ICs 12. The source sampling clock SSC is a clock signal that controls the sampling timing of data in the source drive ICs 12 based on the rising or falling edge. The polarity control signal POL controls the polarity of the data voltages output from the source drive ICs. If the data transfer interface between the timing controller 11 and the source drive ICs 12 is a mini LVDS interface, the source start pulse SSP and the source sampling clock SSC may be omitted.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a view schematically showing a conventional shift register configuration.

2 is a view schematically showing a shift register configuration according to an embodiment of the present invention.

FIG. 3 is a circuit diagram illustrating in detail a circuit configuration of an nth stage illustrated in FIG. 2.

FIG. 4 is a waveform diagram showing input and output signals of the stages shown in FIG. 2.

5A and 5B illustrate stage configurations of a shift register for sequentially supplying scan pulses to 640 scan lines.

FIG. 6 is a waveform diagram showing input and output signals of the shift register shown in FIGS. 5A and 5B.

7 is a block diagram schematically illustrating a display device according to an exemplary embodiment of the present invention.

FIG. 8 is a waveform diagram illustrating input and output signals of the level shift shown in FIG. 7.

<Description of Symbols for Main Parts of Drawings>

10: display panel 12: source drive IC

13: shift register 14: PCB

15: level shifter

Claims (12)

A plurality of stages that are sequentially delayed, a plurality of gate shift clocks, a gate start pulse, a gate high voltage, and a gate low voltage lower than the gate high voltage are input and cascaded; The nth (n is positive integer) stage A first output node connected to the nth scan line and outputting an nth scan pulse; A second output node for outputting an n-th carry signal to be input to the reset terminal of the n-2th stage and the start terminal of the n + 1th stage; A first pull-up transistor turned on according to a voltage of a first Q node to supply an n-th gate shift clock to the first output node to charge the first output node; A second pull-up transistor turned on according to a voltage of a second Q node to supply the n-th gate shift clock to the second output node to charge the second output node; A first pull-down transistor turned on according to a voltage of a QB node to which an n + 1 gate shift clock is applied to supply the gate low voltage to a first output node to discharge the first output node; A second pull-down transistor turned on according to the voltage of the QB node to supply the gate low voltage to a second output node to discharge the second output node; And The Q nodes are charged in response to an n-1 gate shift clock and an n-1 carry signal input from an n-1th stage, and are input from an n + 1 gate shift clock and an n + 2 stage. And a switch circuit for discharging said Q nodes in response to an n-2th carry signal. The method of claim 1, The gate shift clocks are And a four-phase gate shift clock including the n-th gate shift clock, the n-th gate shift clock, the n + 1th gate shift clock, and the n + 2th gate shift clock. The method of claim 1, The switch circuit, A first Q node charging circuit configured to charge the first Q node in response to the n-th carry signal and the n-th gate shift clock; A second Q node charging circuit configured to charge the second Q node in response to the n−1 th gate shift clock; And And a Q node discharge circuit for discharging the Q nodes in response to the n + 2th carry signal. The method of claim 3, wherein The first Q node charging circuit, A gate electrode to which one of the gate start pulse and the n-th carry signal is applied, a source electrode to which the gate high voltage is applied, and a drain connected to the first Q node through the start terminal of the nth stage; A first TFT comprising an electrode; And A gate electrode to which the n-th gate shift clock is applied, a source electrode to which any one of the gate start pulse and the n-th carry signal is applied through a start terminal of the n-th stage, and the first Q node. And a second TFT including a connected drain electrode. The method of claim 3, wherein The second Q node charging circuit, And a second C TFT including a gate electrode to which an n-1 gate shift clock is applied, a source electrode connected to the first Q node, and a drain electrode connected to the second Q node. . The method of claim 3, wherein The Q node discharge circuit, A gate electrode to which at least one of the gate start pulse and the n + 2th carry signal are applied, a source electrode to which the gate low voltage is applied, and the first Q node through a reset terminal of the nth stage; A third TFT including a drain electrode; And A gate electrode to which at least one of the gate start pulse and the n + 2th carry signal are applied, a source electrode to which the gate low voltage is applied, and a drain connected to the second Q node through a reset terminal of the nth stage; And a 3C TFT including an electrode. The method of claim 3, wherein The first pull-up transistor, And a fourth TFT including a gate electrode connected to the first Q node, a source electrode connected to the first output node, and a drain electrode to which the nth gate shift clock is applied. The method of claim 3, wherein The first pull-up transistor, And a fourth C TFT including a gate electrode connected to the second Q node, a source electrode connected to the second output node, and a drain electrode to which the nth gate shift clock is applied. The method of claim 3, wherein The first pull-down transistor, And a fifth TFT including a gate electrode connected to the QB node, a drain electrode connected to the first output node, and a drain electrode to which the gate low voltage is applied. The method of claim 3, wherein The second pull-down transistor, And a fifth TFT including a gate electrode connected to the QB node, a drain electrode connected to the second output node, and a drain electrode to which the gate low voltage is applied. A display panel including a plurality of pixels in which data lines intersect the scan lines and are arranged in a matrix; A data driving circuit supplying a data voltage to the data lines; And A scan driving circuit for sequentially supplying scan pulses to the scan lines; The scan driving circuit uses a shift register including a plurality of gate shift clocks sequentially delayed, a gate start pulse, a gate high voltage, and a plurality of stages to which a gate low voltage lower than the gate high voltage is input and cascaded. Outputting the scan pulse sequentially The nth (n is a positive integer) stage of the shift register, A first output node connected to the nth scan line and outputting an nth scan pulse; A second output node for outputting an n-th carry signal to be input to the reset terminal of the n-2th stage and the start terminal of the n + 1th stage; A first pull-up transistor turned on according to a voltage of a first Q node to supply an n-th gate shift clock to the first output node to charge the first output node; A second pull-up transistor turned on according to a voltage of a second Q node to supply the n-th gate shift clock to the second output node to charge the second output node; A first pull-down transistor turned on according to a voltage of a QB node to which an n + 1 gate shift clock is applied to supply the gate low voltage to a first output node to discharge the first output node; A second pull-down transistor turned on according to the voltage of the QB node to supply the gate low voltage to a second output node to discharge the second output node; And The Q nodes are charged in response to an n-1 gate shift clock and an n-1 carry signal input from an n-1th stage, and are input from an n + 1 gate shift clock and an n + 2 stage. And a switch circuit for discharging the Q nodes in response to an n-2th carry signal. The method of claim 11, The display panel may be any one of a liquid crystal display (LCD), an organic light emitting diode display (OLED), and an electrophoretic display (EPD).

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