KR20120117120A - Pulse output circuit and organic light emitting diode display device using the same - Google Patents

Abstract

PURPOSE: A pulse output circuit and an organic light emitting diode display device using the same are provided to reduce the number of clock lines by successively outputting a signal whose phase is delayed by one horizontal period. CONSTITUTION: A first AND gate(AND1) discharges a Q node by responding a clock inputted through a first clock terminal and a start terminal. A second AND gate(AND2) charges the Q node. A third AND gate(AND3) charges a QB node. A fourth AND gate(AND4) discharges the QB node. An output unit outputs a clock inputted through a second clock terminal according to the voltage of the Q node and QB node.

Description

Pulse output circuit and organic light emitting diode display using the same {PULSE OUTPUT CIRCUIT AND ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE USING THE SAME}

The present invention relates to a pulse output circuit and an organic light emitting diode display using the same.

As the information society develops, the demand for a display device for displaying an image is increasing in various forms. Accordingly, recently, various flat panel displays such as a liquid crystal display (LCD), a plasma display panel (PDP), and an organic light emitting diode (OLED) display have been utilized. . Among these flat panel display devices, organic light emitting diode display devices are capable of low voltage driving, are thin, have excellent viewing angles, and have fast response speeds. An active matrix type organic light emitting diode display device in which a plurality of pixels are arranged in a matrix form to display an image is widely used in organic light emitting diode display devices.

A display panel of an active matrix type organic light emitting diode display device includes a plurality of pixels defined by scan lines and data lines. The pixel array is generally implemented by a scan transistor for supplying a data voltage in response to a scan pulse of a scan line and a drive transistor for controlling the amount of current supplied to the organic light emitting diode OLED according to a data voltage supplied to the gate electrode . At this time, the drain-source current Ids of the driving transistor can be expressed by Equation (1).

In Equation 1, β denotes a proportional coefficient determined by the structure and physical characteristics of the transistor, Vgs denotes a gate-source voltage, and Vth denotes a threshold voltage. At this time, since the threshold voltage Vth of the driving transistor is different for each pixel, even when the same data voltage is supplied to the pixels, the drain-source current Ids of the driving transistor is different for each pixel. Therefore, even when the same data voltage is supplied to each of the pixels, a problem arises in that the luminance of light emitted from each of the pixels is changed. In order to solve this problem, various types of pixel structures for compensating threshold voltages of driving transistors have been proposed.

However, in the case of the pixel compensating the threshold voltage of the driving transistor, a larger number of transistors are required than in the related art, and thus the signal lines for controlling the transistors also increase. As a result, an output circuit for supplying signals to the signal lines is increased, thereby increasing the number of clock lines input to the output circuit. When the clock lines increase, the line load increases due to overlap between the clock lines. When the line load is increased, the clock signals input to the output circuit are delayed and the signals output from the output circuit are also delayed, which causes a problem in driving the display panel. In addition, when the clock lines increase, slimming of the display device is difficult due to an increase in the bezel.

The present invention provides an organic light emitting diode display that can reduce the line load.

The pulse output circuit of the present invention includes a first clock terminal which receives one of three phase clocks of which the phase is sequentially delayed, and a second clock terminal which receives a clock whose phase is delayed by one of the clock input to the first clock terminal. And a third clock terminal for receiving a clock delayed in phase from the clock input to the second clock terminal, and a start terminal for receiving a start signal, the plurality of stages being cascaded and connected to k (k Is a natural number). The stage outputs a k-th pulse signal synchronized with a clock input to the second clock terminal.

An organic light emitting diode display according to an embodiment of the present invention comprises: a display panel including data lines and pulse lines intersecting the data lines; A data driving circuit for supplying a data voltage to the data lines; And a gate driving circuit sequentially supplying a pulse signal to the pulse lines, wherein the gate driving circuit comprises: a first clock terminal receiving any one of three phase clocks whose phases are sequentially delayed; A second clock terminal receiving a clock delayed in phase by a clock input to the clock terminal; a third clock terminal receiving a clock delayed in phase by a clock input to the second clock terminal; and a start terminal receiving a start signal. And at least one pulse output circuit including dependently connected stages, wherein the k (k is a natural number) stage outputs a k th pulse signal synchronized with a clock input to the second clock terminal. It is characterized by.

The present invention receives a three-phase clock signal, and sequentially outputs a signal having a pulse width of two horizontal periods and delayed in phase by one horizontal period. As a result, the present invention can reduce the number of clock lines, thereby reducing the line load due to overlap between clock lines. In addition, the present invention can reduce the bezel, so that the display device can be made slim.

Furthermore, the present invention samples the threshold voltage of the driving transistor for two horizontal periods. As a result, the present invention can secure sufficient time to compensate for the threshold voltage of the driving transistor even when the display device is driven at high speed to implement a stereoscopic image.

1 is an equivalent circuit diagram of a pixel of a display panel according to an exemplary embodiment of the present invention.
FIG. 2 is a waveform diagram illustrating signals input to the pixel of FIG. 1.
3 is a block diagram illustrating a sensing pulse output circuit according to an exemplary embodiment of the present invention.
4 is a waveform diagram illustrating an output of a sensing pulse output circuit according to an exemplary embodiment of the present invention.
5 is an example illustrating a circuit configuration of the stage of FIG. 3.
FIG. 6 is a waveform diagram illustrating signals input and output to the stage of FIG. 5.
7 is a table comparing the overlapping clock lines of the prior art and the present invention.
8 is a block diagram schematically illustrating an organic light emitting diode display according to an exemplary embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, when it is determined that a detailed description of known functions or configurations related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

The names of components used in the following description are selected in consideration of ease of specification, and may be different from actual product names.

1 is an equivalent circuit diagram of a pixel of a display panel according to an exemplary embodiment of the present invention. Referring to FIG. 1, the pixel P of the display panel 10 according to the exemplary embodiment of the present invention is defined as a pulse line and a data line DL that cross each other. In addition, the pulse line includes a scan line SL, a control line CL, a light emitting line EL, a first initialization line IL1, a second initialization line IL2, a sensing line SENL, and the like. The pixel P includes a driving transistor Td, an organic light emitting diode OLED, and a control circuit.

The control circuit includes first to sixth transistors T1, T2, T3, T4, T5, and T6. The first transistor T1 is turned on in response to the light emission pulse EM of the light emission line EL to connect the third node N3 to the organic light emitting diode OLED. The gate electrode of the first transistor T1 is connected to the light emitting line EL, the source electrode is connected to the third node N3, and the drain electrode is connected to the anode electrode of the organic light emitting diode OLED.

The second transistor T2 is turned on in response to the scan pulse SP of the scan line SL to supply the data voltage Vdata of the data line DL to the second node N2. The gate electrode of the second transistor T2 is connected to the scan line SL, the source electrode is connected to the data line DL, and the drain electrode is connected to the second node N2.

The third transistor T3 is turned on in response to the first initialization pulse INI1 of the first initialization line IL1 to supply the scan pulse SP to the second node N2. The gate electrode of the third transistor T3 is connected to the first initialization line IL1, the source electrode is connected to the scan line SL, and the drain electrode is connected to the second node N2.

The fourth transistor T4 is turned on in response to the second initialization pulse INI2 of the second initialization line IL2 to initialize the first node N1 to the voltage of the reference voltage source V _REF . The gate electrode of the fourth transistor T4 is connected to the second initialization line IL2, the source electrode is connected to the first node N1, and the drain electrode is connected to the reference voltage source V _REF .

The fifth transistor T5 is turned on in response to the sensing pulse SEN of the sensing line SENL to connect the first node N1 and the third node N3. The gate electrode of the fifth transistor T5 is connected to the sensing line SENL, the source electrode is connected to the third node N3, and the drain electrode is connected to the first node N1.

The sixth transistor T6 is turned on in response to the control pulse CTRL of the control line CL to initialize the second node N2 to the voltage of the reference voltage source V _REF . The gate electrode of the sixth transistor T6 is connected to the control line CL, the source electrode is connected to the second node N2, and the drain electrode is connected to the reference voltage source V _REF .

The gate electrode of the driving transistor Td is connected to the first node N1, the source electrode is connected to the high potential voltage source VDD, and the drain electrode is connected to the third node N3. The driving transistor Td adjusts the amount of the drain-source current Ids differently depending on the amount of voltage applied to the gate electrode.

The first to sixth transistors T1, T2, T3, T4, T5, and T6, and the driving transistor Td of the pixel P according to the first embodiment of the present invention are formed of thin film transistors. Can be. The semiconductor layers of the first to sixth transistors T1, T2, T3, T4, T5, and T6 and the driving transistor Td may be formed of any one of a-Si, Poly-Si, and oxide semiconductor. In addition, although the first to sixth transistors T1, T2, T3, T4, T5, and T6 and the driving transistor Td are described with reference to FIG. 1, the present disclosure is not limited thereto. It can also be implemented as an N-type MOS-FET.

The anode electrode of the organic light emitting diode OLED is connected to the drain electrode of the first transistor T1, and the cathode electrode is connected to the low potential voltage source VSS. The organic light emitting diode OLED emits light in accordance with the drain-source current Ids of the driving transistor Td. The first capacitor C1 is connected between the first node N1 and the second node N2 and stores the difference voltage between the first node N1 and the second node N2. The second capacitor C2 is connected between the first node N1 and the high potential voltage source VDD and stores the difference voltage between the first node N1 and the high potential voltage source VDD.

The high potential voltage source VDD may be set to supply a DC voltage in consideration of characteristics of the driving transistor Td, characteristics of the organic light emitting diode OLED, and the like. The high potential voltage source VDD may be set to the gate high voltage VGH, and the low potential voltage source VSS may be set to the gate low voltage VGL or the ground voltage GND. The reference voltage V _REF is a voltage for initializing the first node N1 and the second node N2.

The first node N1 is a contact between the gate electrode of the driving transistor Td, the source electrode of the fourth transistor T4, and the drain electrode of the fifth transistor T5. The second node N2 is a contact point between the drain electrode of the second transistor T2, the drain electrode of the third transistor T3, and the source electrode of the sixth transistor T6. The third node N3 is a contact point between the drain electrode of the driving transistor Td, the source electrode of the first transistor T1, and the source electrode of the fifth transistor T5.

FIG. 2 is a waveform diagram illustrating signals input to the pixel of FIG. 1. 2 illustrates a control pulse CTRL, a first initialization pulse INI1, a second initialization pulse INI2, a sensing pulse SEN, and a scan pulse SP input to one pixel P of the display panel 10. ), And light emission pulses EM are shown. The control pulse CTRL, the first initialization pulse INI1, the second initialization pulse INI2, the sensing pulse SEN, the scan pulse SP, and the light emission pulse EM are the first to the first pixels of the pixel P. The signals for controlling the six transistors T1, T2, T3, T4, T5, and T6. The control pulse CTRL, the first initialization pulse INI1, the second initialization pulse INI2, the sensing pulse SEN, the scan pulse SP, and the light emission pulse EM are repeated in one frame period.

The control pulse CTRL has a pulse width of approximately 4 horizontal periods 4H, the first initialization pulse INI1 has a pulse width of approximately 2 horizontal periods 2H, and the second initialization pulse INI2 has approximately a zero width. It has a pulse width of one horizontal period (1H). Further, the sensing pulse SEN has a pulse width of approximately 2 horizontal periods 2H, the scan pulse SP has a pulse width of approximately 1 horizontal period 1H, and the emission pulse EM has approximately 4 horizontal periods. It has a pulse width of (4H). One horizontal period 1H means one line scanning time in which data is written in one line of pixels in the display panel 10.

In addition, the control pulse CTRL and the emission pulse EM may be designed to have a pulse width of approximately 3 horizontal periods 3H. In this case, the control pulse CTRL and the emission pulse EM may occur during the t1, t2, and t3 periods.

The first initialization pulse INI1, the second initialization pulse INI2, the sensing pulse SEN, and the scan pulse SP are generated with the gate high voltage VGH. In contrast, the control pulse CTRL and the emission pulse EM are generated with the gate low voltage VGL. The gate high voltage VGH is set to a voltage smaller than the threshold voltages of the first to sixth transistors T1, T2, T3, T4, T5, and T6, and the gate low voltage VGL is set to the first to sixth transistors ( T1, T2, T3, T4, T5, and T6) are set to voltages above the threshold voltage. The gate high voltage VGH may be set between approximately 14V and 20V, and the gate low voltage VGL may be set between approximately −12V and −5V.

Hereinafter, the operation of the pixel P during the t1 to t4 periods will be briefly described with reference to FIGS. 1 and 2. The period t1 to t3 is a period for compensating the threshold voltage of the driving transistor Td, and the period t4 is a period during which the organic light emitting diode OLED emits light.

During the t1 period, the first initialization pulse INI1 and the second initialization pulse INI2 of the gate low voltage VGL are generated. In addition, the control pulse CRTL of the gate high voltage VGH and the light emission pulse EM are generated. The period t1 is a period corresponding to approximately one horizontal period 1H.

The third transistor T3 is turned on in response to the first initialization pulse INI1 of the gate low voltage VGL to supply the scan pulse SP to the second node N2. Therefore, the second node N2 is charged to the gate high voltage VGH. The fourth transistor T4 is turned on in response to the second initialization pulse INI2 of the gate low voltage VGL to initialize the first node N1 to the voltage of the reference voltage source V _REF . The first transistor T1 is turned off by the light emission pulse EM of the gate high voltage VGH, and the sixth transistor T6 is turned off by the control pulse CTRL of the gate high voltage VGH. do.

During the t2 period, the sensing pulse SEN of the gate low voltage VGL is generated. In addition, the first initialization pulse INI1 maintains the gate low voltage VGL, and the control pulse CTRL and the emission pulse EM maintain the gate high voltage VGH. On the other hand, the second initialization pulse INI2 is inverted to the gate high voltage VGH. The period t2 is a period corresponding to approximately one horizontal period 1H.

The third transistor T3 is turned on by the first initialization pulse INI1 of the gate low voltage VGL. Therefore, the second node N2 maintains a state charged with the gate high voltage VGH. The first transistor T1 remains turned off by the light emission pulse EM of the gate high voltage VGH, and the sixth transistor T6 is applied to the control pulse CTRL of the gate high voltage VGH. To be turned off.

The fourth transistor T4 is turned off by the second initialization pulse INI2 of the gate high voltage VGH. The fifth transistor T5 is turned on in response to the sensing pulse SEN of the gate low voltage VGL to connect the first node N1 and the third node N3. Due to the turn-on of the fifth transistor T5, the gate electrode and the drain electrode of the driving transistor Td are connected to each other. In other words, the driving transistor Td is operated as a diode. At this time, since the voltage difference between the gate-drain electrode and the source electrode of the driving transistor Td is larger than the threshold voltage Vth, the voltage of the gate-drain electrode rises to (VDD-Vth). Therefore, the voltages of the first node N1 and the third node N3 rise to (VDD-Vth). That is, the period t2 is a period during which the threshold voltage Vth of the driving transistor Td is sampled.

During the period t3, the scan pulse SP of the gate low voltage VGL is generated. In addition, the sensing pulse SEN maintains the gate low voltage VGL, and the control pulse CTRL and the emission pulse EM maintain the gate high voltage VGH. On the other hand, the first initialization pulse INI1 is inverted to the gate high voltage VGH. The period t3 is a period corresponding to approximately one horizontal period 1H.

The fifth transistor T5 remains turned on by the sensing pulse SEN1 of the gate low voltage VGL. That is, the driving transistor Td maintains the diode connected state. Therefore, the sampling of the threshold voltage Vth of the driving transistor Td continues even in the period t3. As a result, the first node N1 and the third node N3 have sufficient time to rise up to (VDD-Vth). The first transistor T1 remains turned off by the light emission pulse EM of the gate high voltage VGH, and the sixth transistor T6 is applied to the control pulse CTRL of the gate high voltage VGH. To be turned off.

The third transistor T3 is turned off by the first initialization pulse INI1 of the gate high voltage VGH. The second transistor T2 is turned on in response to the scan pulse SP of the gate low voltage VGL to supply the data voltage Vdata of the data line DL to the second node N2. Therefore, the second node N2 has a data voltage Vdata.

During the t4 period, the control pulse CTRL and the light emission pulse EM of the gate low voltage VGL are generated. Meanwhile, the sensing pulse SEN and the scan pulse SP are inverted to the gate high voltage VGH.

The second transistor T2 is turned off by the scan pulse SP of the gate high voltage VGH. The sixth transistor T6 is turned on in response to the control pulse CTRL of the gate low voltage VGL to initialize the voltage of the second node N2 to the voltage of the reference voltage source V _REF . Therefore, the voltage of the second node N2 is changed from the data voltage Vdata to the voltage of the reference voltage source V _REF .

Meanwhile, since the fifth transistor T5 is turned off by the sensing pulse SEN of the gate high voltage VGH, the first node N1 is floated. Therefore, since the voltage change amount Vdata-V _REF of the second node N2 is reflected in the first node N1 by the first capacitor C1, the voltage of the first node N1 is equal to {VDD-Vth−. (Vdata-V _REF )}. Therefore, the drain-source current of the driving transistor Td is expressed by Equation 2 below.

In Equation 2, β denotes a proportional coefficient determined by the structure and physical characteristics of the transistor, Vgs denotes a gate-source voltage, and Vth denotes a threshold voltage of the driving transistor. As a result, the drain-source current Ids of the driving transistor does not depend on the threshold voltage Vth of the driving transistor Td as in Equation 2. In other words, the threshold voltage Vth of the driving transistor Td is compensated.

The first transistor T1 is turned on in response to the light emission pulse EM of the gate low voltage VGL to supply the drain-source current Ids of the driving transistor Td to the organic light emitting diode OLED. . Therefore, the organic light emitting diode OLED emits light for the period t4.

As described above, when the sensing pulse SEN has a pulse width of approximately 2 horizontal periods 2H, since the period for sampling the threshold voltage Vth of the driving transistor Td is sufficient, the driving transistor Td Threshold voltage (Vth) can be properly compensated. In particular, when the organic light emitting diode display is implemented as a stereoscopic image display device that time-divisionally displays a left eye image and a right eye image, it is essential to drive the display at a frame frequency of 240 Hz or higher (based on NTSC). However, if the period for sampling the threshold voltage Vth of the driving transistor Td is shorter than two horizontal periods 2H, a problem may occur in that the threshold voltage Vth of the driving transistor Td cannot be compensated properly.

In order to output the sensing pulse SEN having a pulse width of approximately 2 horizontal periods 2H, at least a 5-phase clock signal had to be input to the conventional sensing pulse output circuit. However, the gate driving circuit supplying pulses to the pixel P of the display panel 10 may include a control pulse output circuit supplying a control pulse CTRL and a first initialization pulse INI1. 1 an initialization pulse output circuit, a second initialization pulse output circuit for outputting a second initialization pulse INI2, a scan pulse output circuit for supplying a scan pulse SP, and a light emission pulse output circuit for outputting a light emission pulse EM. It includes more. As more clock signals are input to these pulse output circuits, line load increases due to overlap between clock lines. In this case, not only the clock signals input to the pulse output circuits are delayed, but also the pulses output from the pulse output circuits are delayed, thereby causing a problem in driving the display panel. In addition, when the clock lines increase, slimming of the display device is difficult due to an increase in the bezel. Hereinafter, a pulse output circuit according to an exemplary embodiment of the present invention will be described in detail by reducing the number of clock lines by using three-phase clock signals. The pulse output circuit according to the embodiment of the present invention may be implemented as a sensing pulse output circuit and a first initialization pulse output circuit. Hereinafter, for convenience of description, the pulse output circuit of the present invention will be described based on the sensing pulse output circuit.

3 is a block diagram illustrating a sensing pulse output circuit according to an exemplary embodiment of the present invention. 4 is a waveform diagram illustrating an output of a sensing pulse output circuit according to an exemplary embodiment of the present invention. Referring to FIG. 3, a sensing pulse output circuit according to an exemplary embodiment of the present invention includes a plurality of stages (ST (1) to ST (n) where n is a natural number of stages) connected in a cascade manner. In FIG. 3, only the first to third stages ST (1) to ST (3) are illustrated for convenience of description.

In the following description, the "shear stage" refers to being located on top of the stage to be a reference. For example, on the basis of kth (1 <k <n, k, k are two or more natural numbers) stages ST (k), the front end stages are the first stage ST (1) to the k-1st stage ST. (k-1)). The "back stage" refers to being located at the lower part of the stage used as a reference. For example, based on the k-th stage ST (k), the rear stage indicates any one of the k + 1th stage ST (k + 1) to the nth stage ST (n).

The start voltage VST is applied to the start voltage line VSTL, and the first clock C1 is applied to the first clock line CL1. In addition, a second clock C2 is applied to the second clock line CL2, and a third clock C3 is applied to the third clock line CL3.

Each of the stages ST (1) to ST (n) has a start terminal START, a first clock terminal CLK1, a second clock terminal CLK2, a third clock terminal CLK3, and an output terminal. do. The start voltage START or the carry signal of the previous stage is input to the start terminal START of each of the stages ST (1) to ST (n). The start voltage VST is applied to the start terminal START of the first stage ST (1), and the start terminal START of each of the second to nth stages ST (2) to ST (n). The carry signal of the front stage is input to the front stage.

A three-phase clock in which phases are sequentially delayed in each of the first clock terminal CLK1, the second clock terminal CLK2, and the third clock terminal CLK3 of each of the stages ST (1) to ST (n). One of the clocks C1, C2 and C3 is input. That is, one of the three-phase clocks C1, C2, and C3 is input to the first clock terminal CLK1, and the phase is higher than the clock input to the first clock terminal CLK1 to the second clock terminal CLK2. One delayed clock is input, and a clock delayed by one phase from a clock input to the second clock terminal CLK2 is input to the third clock terminal CLK3. For example, when the first clock C1 is input to the first clock terminal CLK1, the second clock C2 delayed by one phase than the first clock C1 is input to the second clock terminal CLK2. The third clock C3, which is delayed in phase from the second clock C2, is input to the third clock terminal CLK3.

The three-phase clocks C1, C2, and C3 have a pulse width for a predetermined time, and the phases are sequentially delayed. For example, the three-phase clocks C1, C2, and C3 have a pulse width of approximately 2 horizontal periods 2H, as shown in FIG. 6, and the phases may be sequentially delayed by one horizontal period 1H. The three-phase clocks C1, C2, and C3 input to the sensing pulse output circuit swing between the gate high voltage VGH and the gate low voltage VGL, and a pulse is generated at the gate low voltage VGL.

Each of the stages ST (1) to ST (n) has one output terminal. The outputs Sout (1) to Sout (n) of each of the stages ST (1) to ST (n) are supplied to the sensing lines SENL of the display panel 10 as a sensing pulse SEN. The signal is input to the start terminal START of the rear stage as a carry signal. Referring to FIG. 4, the outputs Sout (1) to Sout (n) of each of the stages ST (1) to ST (n) are the first stage ST (1) to the nth stage ST ( n)) is output sequentially. The output terminal of the k-th stage ST (k) is connected to the k-th sensing line SENL (k), and the output Sout (k) of the k-th stage ST (k) is k-th sensing. The k-th sensing pulse SEN (k) is output to the line SENL (k). The k-th sensing pulse SEN (k), which is the output Sout (k) of the k-th stage ST (k), has a pulse width of approximately 2 horizontal periods 2H, and the k-th sensing pulse SEN (k-1)) and one horizontal period overlap each other, and the k + 1th sensing pulse SEN (k + 1) and one horizontal period overlap each other.

Since each of the stages ST (1) to ST (n) is cascaded, the outputs Sout (1) to Sout (n) of each of the stages ST (1) to ST (n) are rear stages. It serves as a carry signal input to the start terminal (START) of. Therefore, the sensing pulse SEN is sequentially supplied to the sensing lines SENL only when the start voltage VST is supplied to the first stage ST (1). When the start voltage VST is not supplied to the first stage ST (1), the sensing pulse SEN is not supplied to the sensing lines SENL.

Each of the stages ST (1) to ST (n) is supplied with the voltage of the high potential voltage source VDD and the voltage of the low potential voltage source VSS. A detailed description of the internal circuit of each of the stages ST (1) to ST (n) will be described later with reference to FIG. 5.

5 is an example illustrating a circuit configuration of the stage of FIG. 3. Referring to FIG. 5, each of the stages ST (1) to ST (n) discharges a Q node in response to a clock input through the start terminal START and the first clock terminal CLK1. The second AND gate AND2, the start terminal START, and the first clock that charge the Q node in response to a clock input through the gate AND1, the first clock terminal CLK1, and the third clock terminal CLK3. QB node in response to a clock input through a third AND gate AND3, a first clock terminal CLK1, and a third clock terminal CLK3, which charge a QB node in response to a clock input through the terminal CLK1. And an output unit configured to output a clock input through the second clock terminal CLK2 according to the voltages of the fourth AND gate AND4 and the Q and QB nodes Q and QB. Therefore, the k-th stage ST (k) generates an output synchronized with a clock input through the second clock terminal CLK2.

The first AND gate AND1 includes the eleventh and twelfth transistors T11 and T12. The gate electrode of the eleventh transistor T11 is connected to the start terminal START, the source electrode is connected to the drain electrode of the twelfth transistor T12, and the drain electrode is connected to the low potential voltage source VSS. The gate electrode of the twelfth transistor T12 is connected to the first clock terminal CLK1, the source electrode is connected to the Q node Q, and the drain electrode is connected to the source electrode of the eleventh transistor T11. Accordingly, the eleventh transistor T11 is turned on in response to a signal input through the start terminal START, and the twelfth transistor T12 is turned in response to a signal input through the first clock terminal CLK1. Only when it is turned on, the Q node Q is discharged to the voltage of the low potential voltage source VSS.

The second AND gate AND2 includes the thirteenth and fourteenth transistors T13 and T14. The gate electrode of the thirteenth transistor T13 is connected to the first clock terminal CLK1, the source electrode is connected to the drain electrode of the fourteenth transistor T14, and the drain electrode is connected to the Q node Q. The gate electrode of the fourteenth transistor T14 is connected to the third clock terminal CLK3, the source electrode is connected to the high potential voltage source VDD, and the drain electrode is connected to the source electrode of the thirteenth transistor T13. Accordingly, the thirteenth transistor T13 is turned on in response to a signal input through the first clock terminal CLK1, and the fourteenth transistor T14 is in response to a signal input through the third clock terminal CLK3. Only when turned on, the Q node Q is charged to the voltage of the high potential voltage source VDD.

The third AND gate AND3 includes the fifteenth and sixteenth transistors T15 and T16. The gate electrode of the fifteenth transistor T15 is connected to the start terminal START, the source electrode is connected to the high potential voltage source VDD, and the drain electrode is connected to the source electrode of the sixteenth transistor T16. The gate electrode of the sixteenth transistor T16 is connected to the first clock terminal CLK1, the source electrode is connected to the drain electrode of the fifteenth transistor T15, and the drain electrode is connected to the QB node QB. Accordingly, the fifteenth transistor T15 is turned on in response to a signal input through the start terminal START, and the sixteenth transistor T16 is turned in response to a signal input through the first clock terminal CLK1. Only when it is turned on, the QB node QB is charged to the voltage of the high potential voltage source VDD.

The fourth AND gate AND4 includes the seventeenth and eighteenth transistors T17 and T18. The gate electrode of the seventeenth transistor T17 is connected to the first clock terminal CLK1, the source electrode is connected to the QB node QB, and the drain electrode is connected to the source electrode of the eighteenth transistor T18. The gate electrode of the eighteenth transistor T18 is connected to the third clock terminal CLK3, the source electrode is connected to the drain electrode of the seventeenth transistor T17, and the drain electrode is connected to the low potential voltage source VSS. Therefore, the seventeenth transistor T17 is turned on in response to a signal input through the first clock terminal CLK1, and the eighteenth transistor T18 is in response to a signal input through the third clock terminal CLK3. Only when turned on, the QB node QB is discharged to the voltage of the low potential voltage source VSS.

The output unit is turned on according to the voltage of the Q node Q to discharge the output node NO to a clock input through the second clock terminal CLK2, and to the voltage of the QB node. Accordingly, the first and second pull-down transistors TD1 and TD2 are turned on to charge the output node NO to the voltage of the high potential voltage source VDD. The pull-up transistor TU is turned on due to the bootstrapping of the Q node Q, thereby discharging the output node NO with a clock input through the second clock terminal CLK2 to output the stage Sout. Generates. The gate electrode of the pull-up transistor TU is connected to the Q node Q, the source electrode is connected to the second clock terminal CLK2, and the drain electrode is connected to the output node NO. The first and second pull-down transistors TD1 and TD2 may move the output node NO to the high potential voltage source VDD according to the voltage of the QB node QB so that the output of the stage is maintained at the voltage of the high potential voltage source VDD. Charge at voltage). The gate electrode of the first pull-down transistor TD1 is connected to the QB node QB, the source electrode is connected to the drain electrode of the second pull-down transistor TD2, and the drain electrode is connected to the output node NO. Connected. The gate electrode of the second pull-down transistor TD2 is connected to the QB node QB, the source electrode is connected to the high potential voltage source VDD, and the drain electrode is the source electrode of the first pull-down transistor TD1. Is connected to.

The eleventh through eighteenth transistors T11, T12, T13, T14, T15, T16, T17, and T18, the pull-up transistor TU, and the first and second pull-down transistors TD1 and TD2 are thin films. It may be formed of a transistor (Thin Film Transistor). Semiconductors of the eleventh through eighteenth transistors T11, T12, T13, T14, T15, T16, T17, and T18, pull-up transistors TU, and first and second pull-down transistors TD1 and TD2. The layer may be formed of any one of a-Si, Poly-Si, and oxide semiconductor. In addition, in FIG. 5, the eleventh through eighteenth transistors T11, T12, T13, T14, T15, T16, T17, and T18, the pull-up transistor TU, and the first and second pull-down transistors TD1. Although TD2) has been described based on the P type MOS-FET, the present invention is not limited thereto and may be implemented as an N type MOS-FET.

FIG. 6 is a waveform diagram illustrating signals input and output to the stage of FIG. 5. 5 and 6, the start voltage VST or the output Sout (k-1) of the preceding stage is input to the start terminal START of each of the stages ST (1) to ST (n). do. In addition, each of the first clock terminal CLK1, the second clock terminal CLK2, and the third clock terminal CLK3 of each of the stages ST (1) to ST (n) has three-phase clocks CLK1, CLK2 and CLK3) are sequentially input.

The start voltage VST occurs once at the beginning of one frame period. The start voltage VST and the three phase clocks CLK1, CLK2, and CLK3 have a pulse width of two horizontal periods 2H. In addition, the pulses of the three-phase clocks CLK1, CLK2, and CLK3 overlap one horizontal period 1H. That is, one horizontal period 1H among the pulses of the first clock C1 overlaps the pulse of the third clock C3, and the other one horizontal period 1H overlaps the pulse of the second horizontal period CLK2. . The pulses of the three-phase clocks CLK1, CLK2, and CLK3 are generated with the gate low voltage VGL.

Hereinafter, the operation of the k-th stage ST (k) during the t1 to t4 periods will be described in detail with reference to FIGS. 5 and 6. The first clock C1 is input to the first clock terminal CLK1, the second clock C2 is input to the second clock terminal CLK2, and the third clock C3 is input to the third clock terminal CLK3. It demonstrates centering on what is input.

During the t1 period, the start voltage VST of the gate low voltage VGL (or the output Sout (k-1) of the k-1st stage ST (k-1)) is passed through the start terminal START. Is entered. The first clock C1 of the gate low voltage VGL is input through the first clock terminal CLK1. The third clock C3 of the gate low voltage VGL is input through the third clock terminal CLK3.

The eleventh and fifteenth transistors T11 and T15 are turned on in response to the start voltage VST of the gate low voltage VGL. The twelfth, thirteenth, sixteenth, and seventeenth transistors T12, T13, T16, and T17 are turned on in response to the first clock C1 of the gate low voltage VGL. The fourteenth and eighteenth transistors T14 and T18 are turned on in response to the third clock C3 of the gate low voltage VGL.

That is, due to the turn-on of the eleventh and twelfth transistors T11 and T12 of the first AND gate AND1, the Q node Q is connected to the low potential voltage source VSS. In addition, due to the turn-on of the thirteenth and fourteenth transistors T13 and T14 of the second AND gate AND2, the Q node Q is also connected to the high potential voltage source VDD. Accordingly, the Q node Q has a voltage at an intermediate level between the low potential voltage source VSS and the high potential voltage source VDD voltage.

Due to the turn-on of the fifteenth and sixteenth transistors T15 and T16 of the third AND gate AND3, the QB node QB is connected to the high potential voltage source VDD. In addition, due to the turn-on of the seventeenth and eighteenth transistors T17 and T18 of the fourth AND gate AND4, the QB node QB is also connected to the low potential voltage source VSS. Accordingly, the QB node QB has a voltage at an intermediate level between the low potential voltage source VSS and the high potential voltage source VDD voltage.

During the t2 period, the start voltage VST (or the output Sout (k-1) of the k-1st stage ST (k-1)) input through the start terminal START and the first clock terminal ( The first clock C1 input through the CLK1 maintains the gate low voltage VGL. The third clock C3 input through the third clock terminal CLK3 is inverted to the gate high voltage VGH. The second clock C2 of the gate low voltage VGL is input through the second clock terminal CLK2.

The eleventh and fifteenth transistors T11 and T15 remain turned on by the start voltage VST of the gate low voltage VGL. The twelfth, thirteenth, sixteenth, and seventeenth transistors T12, T13, T16, and T17 remain turned on in response to the first clock C1 of the gate low voltage VGL. The fourteenth and eighteenth transistors T14 and T18 are turned off by the third clock C3 of the gate high voltage VGH. Therefore, the Q node Q is discharged to the voltage of the low potential voltage source VSS, and the QB node QB is charged to the voltage of the high potential voltage source VDD.

The second clock C2 of the gate low voltage VGL is input to the source electrode of the pull-up transistor TU. The voltage at the Q node Q is bootstrapping by the second capacitor C2 between the gate-drain electrodes of the pull-up transistor TU to drop to a voltage level lower than the gate low voltage VGL. The up transistor TU is turned on. Therefore, the voltage of the output node NO drops to the gate low voltage VGL, and the k-th stage ST (k) outputs the gate low voltage VGL.

During the t3 period, the start voltage VST (or the output Sout (k-1) of the k-1st stage ST (k-1)) input through the start terminal START and the first clock terminal ( The first clock C1 input through the CLK1 is inverted to the gate high voltage VGH. The second clock C2 input through the second clock terminal CLK2 maintains the gate low voltage VGL. In addition, the third clock C3 of the gate low voltage VGL is input through the third clock terminal CLK3.

The eleventh and fifteenth transistors T11 and T15 are turned off by the start voltage VST of the gate high voltage VGH. The twelfth, thirteenth, sixteenth, and seventeenth transistors T12, T13, T16, and T17 are turned off by the first clock C1 of the gate high voltage VGH. The fourteenth and eighteenth transistors T14 and T18 are turned on in response to the third clock C3 of the gate low voltage VGL.

Due to the turn-off of the eleventh and twelfth transistors T11 and T12 of the first AND gate AND1, the Q node Q is disconnected from the low potential voltage source VSS. In addition, since the fourteenth transistor T14 is turned on at the second AND gate AND2, but the thirteenth transistor T13 is turned off, the Q node Q is disconnected from the high potential voltage source VDD. do.

The second clock C2 of the gate low voltage VGL is input to the source electrode of the pull-up transistor TU. The voltage of the Q node Q is maintained at a voltage level lower than the gate low voltage VGL by the first capacitor C1, and the pull-up transistor TU is kept turned on. Therefore, the voltage of the output node NO drops to the gate low voltage VGL, and the k-th stage ST (k) outputs the gate low voltage VGL.

Due to the turn-off of the fifteenth and sixteenth transistors T15 and T16 of the third AND gate AND3, the QB node QB is disconnected from the high potential voltage source VDD. In addition, since the eighteenth transistor T18 is turned on at the fourth AND gate AND4, but the seventeenth transistor T17 is turned off, the QB node QB is disconnected from the low potential voltage source VSS. do. The QB node QB maintains the voltage of the high potential voltage source VDD by the third capacitor C3.

During the t4 time, the second clock C2 input through the second clock terminal CLK2 is inverted to the gate high voltage VGH. The third clock C3 input through the third clock terminal CLK3 maintains the gate low voltage VGL. In addition, the first clock C1 of the gate low voltage VGL is input through the first clock terminal CLK1.

The twelfth, thirteenth, sixteenth, and seventeenth transistors T12, T13, T16, and T17 are turned on in response to the first clock C1 of the gate low voltage VGL. The fourteenth and eighteenth transistors T14 and T18 remain turned on in response to the third clock C3 of the gate low voltage VGL. The eleventh and fifteenth transistors T11 and T15 remain turned off by the start voltage VST of the gate high voltage VGH.

Since the twelfth transistor T12 of the first AND gate AND1 is turned on but the eleventh transistor T11 is turned off, the Q node Q is disconnected from the low potential voltage source VSS. Since the thirteenth and fourteenth transistors T13 and T14 of the second AND gate AND2 are turned on, the Q node Q is connected to the high potential voltage source VDD. Therefore, the Q node Q is charged to the voltage of the high potential voltage source VDD, and the pull-up transistor TU is turned off.

Since the sixteenth transistor T16 of the third AND gate AND3 is turned on but the fifteenth transistor T15 is turned off, the QB node QB is disconnected from the high potential voltage source VDD. Since the seventeenth and eighteenth transistors T17 and T18 of the fourth AND gate AND4 are turned on, the QB node QB is connected to the low potential voltage source VSS. Therefore, the QB node QB is discharged to the voltage of the low potential voltage source VSS. The first and second pull-down transistors TD1 and TD2 are turned on in response to the voltage of the low potential voltage source VSS of the QB node QB to charge the output node NO to the voltage of the high potential voltage source VDD. Let's do it. As a result, the voltage of the output node NO rises to the gate high voltage VGH, and the k-th stage ST (k) outputs the gate high voltage VGH.

7 is a table comparing the overlapping clock lines of the prior art and the present invention. Referring to FIG. 7, overlapping numbers of clock lines are compared according to the number of output units of one line of the display panel 10. In addition, the prior art is a case using five clock lines, the present invention is a case using three clock lines as described above.

When there is one pulse output circuit in one line of the display panel 10, the conventional technique has 2.4 overlapping numbers of clock lines, whereas the present invention has two overlapping numbers of clock lines. The present invention can save approximately 17% overlap between clock lines compared to the prior art. When there are two pulse output circuits on one line of the display panel 10, the prior art has 5.4 overlapping clock lines, whereas the present invention has four overlapping clock lines. The present invention can save approximately 26% overlap between clock lines compared to the prior art. When there are three pulse output circuits on one line of the display panel 10, the conventional technique has 8.4 overlapping numbers of clock lines, whereas the present invention has six overlapping numbers of clock lines. The present invention can save approximately 30% overlap between clock lines compared to the prior art. As a result, as more pulse output circuits exist on one line of the display panel 10, the overlapping effect between the clock lines of the present invention becomes larger than in the prior art.

As described above, the gate driving circuit of the present invention includes a control pulse output circuit, a first initialization pulse output circuit, a second initialization pulse output circuit, a sensing pulse output circuit, a scan pulse output circuit, and a light emission pulse output circuit. That is, six pulse output circuits are required for one line of the display panel 10. When using five clock lines as in the prior art, the line load will be further deepened due to the overlap between the clock lines. In this case, not only the clock signals input to the pulse output circuits are delayed, but also the pulses output from the pulse output circuits are delayed, which may cause a problem in driving the display panel. In addition, when the clock lines increase, slimming of the display device is difficult due to an increase in the bezel.

When three clock lines are used as in the present invention, overlap between clock lines can be minimized. Accordingly, the present invention can reduce line load due to overlap between clock lines, and can prevent delay of clock signals. In addition, since the present invention can reduce the clock lines, the bezel area can be reduced to reduce the size of the display device.

8 is a block diagram schematically illustrating an organic light emitting diode display according to an exemplary embodiment of the present invention. Referring to FIG. 8, an organic light emitting diode display according to an exemplary embodiment of the present invention includes a display panel 10, a data driving circuit, a gate driving circuit 14, a timing controller 11, and the like.

The display panel 10 is formed such that the data lines DL and the scan lines SL cross each other. In addition, the display panel 10 includes the control lines CTRL, the first initialization lines IL1, the second initialization lines IL2, the sensing lines SEL, and light emission in parallel with the scan lines SL. Lines EL are formed. The display panel 10 includes a pixel array PIXEL ARRAY in which pixels are arranged in a matrix in cell regions defined by data lines DL and scan lines SL. Each pixel P of the pixel array PIXEL ARRAY of the display panel 10 has been described above with reference to FIG. 1.

The data drive circuit includes a plurality of source drive ICs 12. [ The source drive ICs 12 receive the digital video data RGB from the timing controller 11. [ The source driver ICs 12 convert the digital video data RGB to a gamma compensation voltage in response to a source timing control signal from the timing controller 11 to generate a data voltage, To the data lines (DL) of the display panel 10 so as to be synchronized with each other. The source drive ICs 12 may be connected to the data lines DL of the display panel 10 by a COG (Chip On Glass) process or a TAB (Tape Automated Bonding) process.

The level shifter 13 level shifts the TTL (Logic-Transistor-Logic) logic level voltage of the clocks CLKs input from the timing controller 11 to the gate high voltage VGH and the gate low voltage VGL. The level-shifted clocks (CLKs) are input to the gate drive circuit (14).

The gate driving circuit 14 includes a scan pulse output circuit, first and second initialization pulse output circuits, a control pulse output circuit, a sensing pulse output circuit, and a light emitting pulse output circuit. The scan pulse output circuit is connected to the scan lines GL of the display panel 10 to sequentially output the scan pulses SP to the scan lines SL. The first initialization pulse output circuit is connected to the first initialization lines IL1 of the display panel 10 to sequentially output the first initialization pulse INI1. The second initialization pulse output circuit is connected to the second initialization lines IL2 of the display panel 10 to sequentially output the second initialization pulse INI2. The control pulse output circuit is connected to the control lines CL of the display panel 10 and sequentially outputs the control pulse CTRL. The sensing pulse output circuit is connected to the sensing line SEL of the display panel 10 to sequentially output the sensing pulse SEN. The light emitting pulse output circuit is connected to the light emitting lines EL and outputs a light emitting pulse EM that controls light emission of the organic light emitting diode OLED. This has been described above with reference to FIGS. 1 and 2.

The gate drive circuit 14 is formed directly on the lower substrate of the display panel 10 by a GIP (Gate Drive-IC In Panel) method. In the GIP scheme, the level shifter 13 is mounted on a printed circuit board 15, and the gate drive circuit 14 is formed on a lower substrate of the display panel 10. Further, the gate drive circuit 14 may be connected between the display panel 10 and the timing controller 11 in a TAB manner.

The timing controller 11 receives digital video data RGB from an external host system through an interface such as a Low Voltage Differential Signaling (LVDS) interface or a Transition Minimized Differential Signaling (TMDS) interface. The timing controller 11 transmits digital video data (RGB) input from the host system to the source drive ICs 12.

The timing controller 11 receives timing signals such as a vertical synchronizing signal Vsync, a horizontal synchronizing signal Hsync, a data enable signal DE and a main clock MCLK from the host system through an LVDS or TMDS interface receiving circuit And receives a signal. The timing controller 11 generates timing control signals for controlling the operation timing of the data driving circuit and the gate driving circuit 14 based on the timing signal from the host system. The timing control signals include a gate timing control signal for controlling the operation timing of the gate drive circuit 14, a data timing control signal for controlling the operation timing of the source drive ICs 12 and the polarity of the data voltage.

The gate timing control signal includes a start voltage VST and clocks CLKs sequentially generated in three phases. The start voltage VST is input to the gate driving circuit 14 to shift the shift start timing of the scan pulse output circuit, the first and second initialization pulse output circuits, the control pulse output circuit, the sensing pulse output circuit, and the light emission pulse output circuit. To control. The clocks CLKs are input to the level shifter 13, level-shifted and then input to the gate drive circuit 14, and used as a clock signal for shifting the start voltage VST.

The data timing control signal includes a source start pulse (SSP), a source sampling clock (SSC), a polarity control signal (POL), and a source output enable signal (SOE) . The source start pulse SSP controls the shift start timing of the source drive ICs 12. [ The source sampling clock SSC is a clock signal that controls the sampling timing of data in the source drive ICs 12 based on the rising or falling edge. The polarity control signal POL controls the polarity of the data voltage output from the source drive ICs. If the data transfer interface between the timing controller 11 and the source drive ICs 12 is a mini LVDS interface, the source start pulse SSP and the source sampling clock SSC may be omitted.

As described above, the present invention provides an organic light emitting diode display device including a pulse output circuit which receives a three-phase clock signal and sequentially outputs a pulse signal having a pulse width of two horizontal periods and a phase delay of one horizontal period. It is about. Although the pulse output circuit of the embodiment of the present invention has been described with reference to the implementation of the sensing pulse output circuit, it should be noted that the present invention is not limited thereto. That is, like the sensing pulse SEN, the first initialization pulse output circuit generating the first initialization pulse INI1 having a pulse width of two horizontal periods and the phase delayed by one horizontal period may also be implemented as the pulse output circuit of the present invention. Can be.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: Display panel 11: Timing controller
12: Source drive IC 13: Level shifter
14: gate drive circuit 15: printed circuit board

Claims (14)

A first clock terminal which receives one of three phase clocks of which phase is sequentially delayed, a second clock terminal which receives a clock whose phase is delayed by one than a clock input to the first clock terminal, and a second clock terminal A third clock terminal for receiving a clock delayed in phase from the clocked clock and a start terminal for receiving a start signal, and comprising a plurality of stages connected in a cascade manner;
And the k th (k is a natural number) stage outputs a k th pulse signal synchronized with a clock input to the second clock terminal. The method of claim 1,
The three-phase clock has a pulse width of two horizontal periods, the pulse output circuit, characterized in that the phase is delayed sequentially by one horizontal period. The method of claim 2,
And the k th pulse signal has a pulse width of two horizontal periods, and overlaps the k-1 th pulse signal and one horizontal period, and the k + 1 th pulse signal and one horizontal period overlap each other. The method of claim 1,
The k-th stage is,
A first AND which discharges the Q node to a voltage of a low potential voltage source using an eleventh transistor turned on in response to the start signal and a twelfth transistor turned on in response to a clock input to the first clock terminal; gate;
Charging the Q node to a voltage of a high potential voltage source using a thirteenth transistor turned on in response to the first clock terminal and a fourteenth transistor turned on in response to a clock input to the third clock terminal. A second AND gate;
A third battery charging the QB node to the voltage of the high potential voltage source by using a fifteenth transistor turned on in response to the start signal and a sixteenth transistor turned on in response to a clock input to the first clock terminal; AND gate;
The QB node is discharged to the voltage of the low potential voltage source by using a seventeenth transistor turned on in response to the first clock terminal and an eighteenth transistor turned on in response to a clock input to the third clock terminal. A fourth AND gate; And
And an output unit configured to output a clock input to the second clock terminal according to voltages of the Q node and the QB node. The method of claim 4, wherein
A gate electrode of the eleventh transistor is connected to the start terminal, a source electrode is connected to a drain electrode of the twelfth transistor, a drain electrode is connected to a low potential voltage source,
A gate electrode of the twelfth transistor is connected to the first clock terminal, a source electrode is connected to the Q node, a drain electrode is connected to a source electrode of the eleventh transistor,
A gate electrode of the thirteenth transistor is connected to the first clock terminal, a source electrode is connected to a drain electrode of the first transistor, a drain electrode is connected to the Q node,
A gate electrode of the fourteenth transistor is connected to the third clock terminal, a source electrode is connected to the high potential voltage source, a drain electrode is connected to a source electrode of the thirteenth transistor,
A gate electrode of the fifteenth transistor is connected to the start terminal, a source electrode is connected to the high potential voltage source, a drain electrode is connected to a source electrode of the sixteenth transistor,
A gate electrode of the sixteenth transistor is connected to the first clock terminal, a source electrode is connected to a drain electrode of the fifteenth transistor, a drain electrode is connected to the QB node,
A gate electrode of the seventeenth transistor is connected to the first clock terminal, a source electrode is connected to the QB node, a drain electrode is connected to a source electrode of the eighteenth transistor,
And the gate electrode of the eighteenth transistor is connected to the third clock terminal, the source electrode is connected to the drain electrode of the seventeenth transistor, and the drain electrode is connected to the low potential voltage source. The method of claim 4, wherein
The output unit includes:
A pull-up transistor that is turned on according to the voltage of the Q node and discharges an output node to a clock input to the second clock terminal, and is turned on according to the voltage of the QB node to turn the output node into the high potential And a first pull-down transistor charging with a voltage of a voltage source. The method according to claim 6,
A gate electrode of the pull-up transistor is connected to the Q node, a source electrode is connected to the second clock terminal, a drain electrode is connected to the output node,
A gate electrode of the first pull-down transistor is connected to the QB node, a source electrode is connected to a drain electrode of the second pull-down transistor, a drain electrode is connected to the output node,
A gate electrode of the second pull-down transistor is connected to the QB node, a source electrode is connected to the high potential voltage source, and a drain electrode is connected to the source electrode of the first pull-down transistor Output circuit. A display panel on which data lines and pulse lines intersecting the data lines are formed;
A data driving circuit for supplying a data voltage to the data lines; And
A gate driving circuit sequentially supplying pulse signals to the pulse lines,
The gate driving circuit,
A first clock terminal which receives one of three phase clocks of which phase is sequentially delayed, a second clock terminal which receives a clock whose phase is delayed by one than a clock input to the first clock terminal, and a second clock terminal At least one pulse output circuit having a third clock terminal receiving a clock delayed in phase from the clocked clock and a start terminal receiving a start signal, the at least one pulse output circuit including stages connected to each other;
And the k-th (k is a natural number) stage outputs a k-th pulse signal synchronized with a clock input to the second clock terminal. The method of claim 8,
And the three-phase clocks have a pulse width of two horizontal periods, and the phases are sequentially delayed by one horizontal period. The method of claim 9,
The k th pulse signal has a pulse width of 2 horizontal periods, and the k-1 th pulse signal and the 1 horizontal period overlap each other, and the k + 1 pulse signal and the 1 horizontal period overlap each other. Device. The method of claim 8,
The k-th stage is,
A first AND which discharges the Q node to a voltage of a low potential voltage source using an eleventh transistor turned on in response to the start signal and a twelfth transistor turned on in response to a clock input to the first clock terminal; gate;
Charging the Q node to a voltage of a high potential voltage source using a thirteenth transistor turned on in response to the first clock terminal and a fourteenth transistor turned on in response to a clock input to the third clock terminal. A second AND gate;
A third battery charging the QB node to the voltage of the high potential voltage source by using a fifteenth transistor turned on in response to the start signal and a sixteenth transistor turned on in response to a clock input to the first clock terminal; AND gate;
The QB node is discharged to the voltage of the low potential voltage source by using a seventeenth transistor turned on in response to the first clock terminal and an eighteenth transistor turned on in response to a clock input to the third clock terminal. A fourth AND gate; And
And an output unit configured to output a clock inputted to the second clock terminal according to the voltages of the Q node and the QB node. The method of claim 11,
A gate electrode of the eleventh transistor is connected to the start terminal, a source electrode is connected to a drain electrode of the twelfth transistor, a drain electrode is connected to a low potential voltage source,
A gate electrode of the twelfth transistor is connected to the first clock terminal, a source electrode is connected to the Q node, a drain electrode is connected to a source electrode of the eleventh transistor,
A gate electrode of the thirteenth transistor is connected to the first clock terminal, a source electrode is connected to a drain electrode of the first transistor, a drain electrode is connected to the Q node,
A gate electrode of the fourteenth transistor is connected to the third clock terminal, a source electrode is connected to the high potential voltage source, a drain electrode is connected to a source electrode of the thirteenth transistor,
A gate electrode of the fifteenth transistor is connected to the start terminal, a source electrode is connected to the high potential voltage source, a drain electrode is connected to a source electrode of the sixteenth transistor,
A gate electrode of the sixteenth transistor is connected to the first clock terminal, a source electrode is connected to a drain electrode of the fifteenth transistor, a drain electrode is connected to the QB node,
A gate electrode of the seventeenth transistor is connected to the first clock terminal, a source electrode is connected to the QB node, a drain electrode is connected to a source electrode of the eighteenth transistor,
An organic light emitting diode display of which the gate electrode of the eighteenth transistor is connected to the third clock terminal, the source electrode is connected to the drain electrode of the seventeenth transistor, and the drain electrode is connected to the low potential voltage source . The method of claim 11,
The output unit includes:
A pull-up transistor that is turned on according to the voltage of the Q node and discharges an output node to a clock input to the second clock terminal, and is turned on according to the voltage of the QB node to turn the output node into the high potential An organic light emitting diode display device comprising: first and second pull-down transistors charged at a voltage of a voltage source. The method of claim 13,
A gate electrode of the pull-up transistor is connected to the Q node, a source electrode is connected to the second clock terminal, a drain electrode is connected to the output node,
A gate electrode of the first pull-down transistor is connected to the QB node, a source electrode is connected to a drain electrode of the second pull-down transistor, a drain electrode is connected to the output node,
The gate electrode of the second pull-down transistor is connected to the QB node, the source electrode is connected to the high potential voltage source, and the drain electrode is connected to the source electrode of the first pull-down transistor. Light emitting diode display device.

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