KR20100081158A - Plasma display apparatus - Google Patents

Abstract

PURPOSE: A plasma display device is provided to control the increase of black brightness by highly setting the set down lowest voltage of a pre-reset period than the set down lowest voltage of a reset period. CONSTITUTION: A plurality of scan electrodes are formed on an upper plate(10). A plurality of address electrodes are formed in sustain electrodes(12) and lower plates(20). A driving part supplies a driving signal to a plurality of electrodes. A reset signal is supplied to the reset period of at least one subfield among a plurality of subfields. A pulse signal and a second set-down signal are sequentially supplied to a scan electrode(11) in the pre reset period before a reset period.

Description

Plasma display apparatus

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display device, and more particularly, to a plasma display device in which high temperature flashing misdischarge is improved without increasing black luminance.

The plasma display panel (hereinafter referred to as PDP) displays an image by excitation and emitting phosphors by vacuum ultraviolet rays (VUV) generated when the inert gas is discharged.

Such a PDP is not only large in size and thin in thickness, but also has a simple structure and is easy to manufacture, and has a high luminance and high luminous efficiency compared to other flat display devices. In particular, the AC surface-discharge type 3-electrode plasma display panel has advantages of low voltage driving and long life because wall charges are accumulated on the surface during discharge to protect the electrodes from sputtering caused by the discharge.

The plasma display panel is time-division driven by a reset period for initializing all cells, an address period for selecting cells, and a sustain period for causing display discharge in the selected cells in order to realize gray levels of an image. do.

Meanwhile, various efforts have been made to improve misdischarges when the plasma display panel is driven.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a plasma display device in which a high temperature flashing misdischarge is improved without increasing the black brightness in order to solve the above problems in the plasma display device.

According to an embodiment of the present invention, a plasma display apparatus includes a plurality of scan electrodes formed on an upper substrate, and sustain electrodes and a plurality of address electrodes formed on a lower substrate. And a driving unit supplying a driving signal to the plurality of electrodes, wherein a reset signal including a set down signal is supplied to the scan electrode in a reset period of at least one subfield of the plurality of subfields, and before the reset period. In the pre-reset period, the pulse signal and the second set-down signal are sequentially supplied to the scan electrode, and the lowest voltage of the second set-down signal in the pre-reset period is smaller than the minimum voltage of the set-down signal in the reset period.

According to the present invention configured as described above, since the setdown minimum voltage in the pre-reset period is set higher than the setdown minimum voltage in the reset period, an increase in black brightness is suppressed.

On the other hand, by supplying a bias voltage to the sustain electrode when the set down signal is supplied to the scan electrode in the pre-reset period, the high temperature mis-discharge and flicker improvement are significantly performed.

Hereinafter, a plasma display device and a driving method thereof according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a perspective view illustrating an embodiment of a structure of a plasma display panel.

As shown in FIG. 1, the plasma display panel includes a scan electrode 11, a sustain electrode 12, a sustain electrode pair formed on the upper substrate 10, and an address electrode 22 formed on the lower substrate 20. It includes.

The sustain electrode pairs 11 and 12 generally include transparent electrodes 11a and 12a and bus electrodes 11b and 12b formed of indium tin oxide (ITO), and the bus electrodes 11b and 12b. 12b) may be formed of a metal such as silver (Ag) or chromium (Cr) or a stack of chromium / copper / chromium (Cr / Cu / Cr) or a stack of chromium / aluminum / chromium (Cr / Al / Cr). . The bus electrodes 11b and 12b are formed on the transparent electrodes 11a and 12a to serve to reduce voltage drop caused by the transparent electrodes 11a and 12a having high resistance.

Meanwhile, according to the exemplary embodiment of the present invention, the sustain electrode pairs 11 and 12 may not only have a structure in which the transparent electrodes 11a 12a and the bus electrodes 11b and 12b are stacked, but also the buses without the transparent electrodes 11a and 12a. Only the electrodes 11b and 12b may be configured. This structure does not use the transparent electrodes (11a, 12a), there is an advantage that can lower the cost of manufacturing the panel. The bus electrodes 11b and 12b used in this structure may be various materials such as photosensitive materials in addition to the materials listed above.

Light between the scan electrodes 11 and the sustain electrodes 12 between the transparent electrodes 11a and 12a and the bus electrodes 11b and 11c to absorb external light generated outside the upper substrate 10 to reduce reflection. A black matrix (BM, 15) is arranged that functions to block and to improve the purity and contrast of the upper substrate 10.

The black matrix 15 according to the exemplary embodiment of the present invention is formed on the upper substrate 10, the first black matrix 15 and the transparent electrodes 11a and 12a formed at positions overlapping the partition wall 21. And the second black matrices 11c and 12c formed between the bus electrodes 11b and 12b. Here, the first black matrix 15 and the second black matrices 11c and 12c, also referred to as black layers or black electrode layers, may be simultaneously formed and physically connected in the formation process, or may not be simultaneously formed and thus not physically connected. .

In addition, when physically connected and formed, the first black matrix 15 and the second black matrix 11c and 12c may be formed of the same material, but may be formed of different materials when they are formed separately.

The upper dielectric layer 13 and the passivation layer 14 are stacked on the upper substrate 10 having the scan electrode 11 and the sustain electrode 12 side by side. Charged particles generated by the discharge are accumulated in the upper dielectric layer 13, and the protective electrode pairs 11 and 12 may be protected. The protective film 14 protects the upper dielectric layer 13 from sputtering of charged particles generated during gas discharge, and increases emission efficiency of secondary electrons.

In addition, the address electrode 22 is formed in a direction crossing the scan electrode 11 and the sustain electrode 12. In addition, the lower dielectric layer 23 and the partition wall 21 are formed on the lower substrate 20 on which the address electrode 22 is formed.

In addition, the phosphor layer 23 is formed on the surfaces of the lower dielectric layer 24 and the partition wall 21. The partition wall 21 has a vertical partition wall 21a and a horizontal partition wall 21b formed in a closed shape, and physically distinguishes discharge cells, and prevents ultraviolet rays and visible light generated by the discharge from leaking into adjacent discharge cells.

In an embodiment of the present invention, not only the structure of the partition wall 21 illustrated in FIG. 1, but also the structure of the partition wall 21 having various shapes may be possible. For example, a channel in which a channel usable as an exhaust passage is formed in at least one of the differential partition structure, the vertical partition 21a, or the horizontal partition 21b having different heights of the vertical partition 21a and the horizontal partition 21b. A grooved partition structure having a groove formed in at least one of the type partition wall structure, the vertical partition wall 21a, or the horizontal partition wall 21b may be possible.

Here, in the case of the differential partition wall structure, the height of the horizontal partition wall 21b is more preferable, and in the case of the channel partition wall structure or the groove partition wall structure, it is preferable that a channel is formed or the groove is formed in the horizontal partition wall 21b. something to do.

Meanwhile, in one embodiment of the present invention, although the R, G and B discharge cells are shown and described as being arranged on the same line, it may be arranged in other shapes. For example, a Delta type arrangement in which R, G, and B discharge cells are arranged in a triangular shape may be possible. In addition, the shape of the discharge cell may be not only rectangular, but also various polygonal shapes such as a pentagon and a hexagon.

In addition, the phosphor layer 23 emits light by ultraviolet rays generated during gas discharge to generate visible light of any one of red (R), green (G), and blue (B). Here, an inert mixed gas such as He + Xe, Ne + Xe, and He + Ne + Xe for discharging may be injected into the discharge space provided between the upper / lower substrates 10 and 20 and the partition wall 21.

FIG. 2 illustrates an embodiment of an electrode arrangement of a plasma display panel, and a plurality of discharge cells constituting the plasma display panel are preferably arranged in a matrix form as shown in FIG. 2. The plurality of discharge cells are provided at the intersections of the scan electrode lines Y1 to Ym, the sustain electrode lines Z1 to Zm, and the address electrode lines X1 to Xn, respectively. The scan electrode lines Y1 to Ym may be driven sequentially or simultaneously, and the sustain electrode lines Z1 to Zm may be driven simultaneously. The address electrode lines X1 to Xn may be driven by being divided into odd-numbered lines and even-numbered lines, or sequentially driven.

Since the electrode arrangement shown in FIG. 2 is only an embodiment of the electrode arrangement of the plasma panel according to the present invention, the present invention is not limited to the electrode arrangement and driving method of the plasma display panel shown in FIG. 2. For example, a dual scan method in which two scan electrode lines among the scan electrode lines Y1 to Ym are simultaneously scanned is possible. In addition, the address electrode lines X1 to Xn may be driven by being divided up and down or left and right in the center portion of the panel.

3 is a timing diagram illustrating an embodiment of a time division driving method by dividing a frame into a plurality of subfields. The unit frame may be divided into a predetermined number, for example, eight subfields SF1, ..., SF8 to realize time division gray scale display. Each subfield SF1, ... SF8 is divided into a reset section (not shown), an address section A1, ..., A8 and a sustain section S1, ..., S8.

Here, according to an embodiment of the present invention, the reset period may be omitted in at least one of the plurality of subfields. For example, the reset period may exist only in the first subfield or may exist only in a subfield about halfway between the first subfield and all the subfields.

In each address section A1, ..., A8, a display data signal is applied to the address electrode X, and scan pulses corresponding to each scan electrode Y are sequentially applied.

In each of the sustain periods S1, ..., S8, a sustain pulse is alternately applied to the scan electrode Y and the sustain electrode Z to form wall charges in the address periods A1, ..., A8. Sustain discharge occurs in the discharge cells.

The luminance of the plasma display panel is proportional to the number of sustain discharge pulses in the sustain discharge periods S1, ..., S8 occupied in the unit frame. When one frame forming one image is represented by eight subfields and 256 gradations, each subfield in turn has different sustains at a ratio of 1, 2, 4, 8, 16, 32, 64, and 128. The number of pulses can be assigned. In order to obtain luminance of 133 gradations, cells may be sustained by addressing the cells during the subfield 1 section, the subfield 3 section, and the subfield 8 section.

The number of sustain discharges allocated to each subfield may be variably determined according to weights of the subfields according to the APC (Automatic Power Control) step. That is, in FIG. 3, a case in which one frame is divided into eight subfields has been described as an example. However, the present invention is not limited thereto, and the number of subfields forming one frame may be variously modified according to design specifications. Do. For example, a plasma display panel may be driven by dividing one frame into eight or more subfields, such as 12 or 16 subfields.

The number of sustain discharges allocated to each subfield can be variously modified in consideration of gamma characteristics and panel characteristics. For example, the gray level assigned to subfield 4 may be lowered from 8 to 6, and the gray level assigned to subfield 6 may be increased from 32 to 34.

4 is a timing diagram illustrating an embodiment of a drive signal for driving a plasma display panel.

The subfield is a wall formed by a pre-reset section and a pre-reset section for forming positive wall charges on the scan electrodes Y and negative wall charges on the sustain electrodes Z. It may include a reset section for initializing the discharge cells of the entire screen by using the charge distribution, an address section for selecting the discharge cells, and a sustain section for maintaining the discharge of the selected discharge cells. have.

The reset section is composed of a setup section and a setdown section. In the setup section, rising ramp waveforms (Ramp-up) are simultaneously applied to all scan electrodes to generate fine discharge in all discharge cells. Wall charges are generated. In the three down periods, a falling ramp waveform (Ramp-down) falling at a positive voltage lower than the peak voltage of the rising ramp waveform (Ramp-up) is simultaneously applied to all scan electrodes (Y), thereby erasing discharge in all discharge cells. Is generated, thereby eliminating unnecessary charges during wall charges and space charges generated by the setup discharges.

In the address period, a scan signal having a negative scan voltage Vsc is sequentially supplied to the scan electrode, and a positive data signal is applied to the address electrode X at the same time. The address discharge is generated by the voltage difference between the scan signal and the data signal and the wall voltage generated during the reset period, thereby selecting the cell. On the other hand, in order to increase the efficiency of the address discharge, a sustain bias voltage Vzb is applied to the sustain electrode during the address period.

During the address period, the plurality of scan electrodes Y may be divided into two or more groups, and scan signals may be sequentially supplied to each group, and each of the divided groups may be further divided into two or more subgroups and sequentially by the subgroups. Scan signals can be supplied. For example, the plurality of scan electrodes Y is divided into a first group and a second group, and scan signals are sequentially supplied to scan electrodes belonging to the first group, and then scan electrodes belonging to the second group Scan signals may be supplied sequentially.

According to an embodiment of the present invention, the plurality of scan electrodes Y may be divided into a first group located at an even number and a second group located at an odd number according to a position formed on a panel. In another embodiment, the panel may be divided into a first group positioned above and a second group positioned below the center of the panel.

The scan electrodes belonging to the first group divided by the above method are further divided into a first subgroup located at an even number and a second subgroup located at an odd number, or the first group. The first subgroup positioned above and the second group positioned below may be divided based on the center of the.

In the sustain period, a sustain pulse having a sustain voltage Vs is alternately applied to the scan electrode and the sustain electrode to generate sustain discharge in the form of surface discharge between the scan electrode and the sustain electrode.

The width of the first sustain signal or the last sustain signal among the plurality of sustain signals alternately supplied to the scan electrode and the sustain electrode in the sustain period may be greater than the width of the remaining sustain pulses.

The present invention is not limited by the waveforms shown in FIG. 4. For example, the polarity and voltage level of the driving signals shown in FIG. 4 may be changed as necessary. In addition, the single sustain driving may be performed by applying the sustain signal to only one of the scan electrode (Y) and the sustain (Z) electrode to generate a sustain discharge.

5 to 7 are timing diagrams showing embodiments of waveforms of a panel driving signal according to the present invention.

First, referring to FIG. 5, FIG. 5 briefly illustrates only the scan electrode Y and the sustain electrode Z of the plasma display panel.

In the figure, although (n-1) subfield ((n-1) SF) and n subfield (nSF) are started in succession, both subfields are shown to belong to an isolation frame, but not limited thereto, and (n -1) The subfield and the n subfield may be between a single frame having a plurality of subfields.

First, a pre-reset period Tf is disposed between the last sustain pulse signal of the (n-1) subfield and the reset period of the n subfield.

First, in the reset period, as described above with reference to FIG. 4, the setdown signal is supplied to the scan electrode Y. On the other hand, it is also possible to supply the setup signal before the set down signal. Discharge is initiated by the setup signal, and wall charges begin to accumulate on the scan electrode Y, and weak discharge is generated by the setdown signal, thereby eliminating unnecessary wall charges.

On the other hand, a positive bias voltage V3 is applied to the sustain electrode Z. The bias voltage V3 may be supplied in accordance with the setdown signal, but is not limited thereto, and may be supplied while the setup signal is supplied. On the other hand, while the set down signal is supplied, the sustain electrode Z may be floated. Thus, unnecessary wall charge cancellation can be performed more efficiently. When the sustain electrode Z is floated as described above, the voltage drop slope of the sustain electrode Z may be the same as the voltage drop slope caused by the set down signal of the scan electrode Y. FIG.

On the other hand, the pre-reset period Tf is arranged to form positive wall charges on the scan electrode Y and to form negative wall charges on the sustain electrode Z. During the pre-reset period Tf, the lower the lowest voltage of the set-down signal supplied to the scan electrode Y, the higher the possibility of flashing mis-discharge and black brightness rise between the scan electrode Y and the sustain electrode Z.

Accordingly, in FIG. 5, the lowest voltage V1 of the second setdown signal supplied to the scan electrode Y during the pre-reset period Tf is the lowest voltage of the setdown signal supplied to the scan electrode Y during the reset period. Set higher than V2). In this case, in order for the positive wall charges to accumulate on the scan electrode Y by the lowest voltage V1 of the second setdown signal, the lowest voltage V1 of the second setdown signal preferably has a negative potential. .

Meanwhile, as shown in the figure, the lowest voltage V1 of the second set-down signal may be lower than the high level of the scan signal in the address period.

On the other hand, the positive bias voltage V3 is supplied to the sustain electrode Z in order to accumulate negative wall charges on the sustain electrode Z during the pre-reset period Tf. This bias voltage V3 is preferably supplied while the second set down signal is supplied.

The voltage difference (| V3-V1 |) between the lowest voltage V1 and the bias voltage V3 of the second set down signal is preferably 260 to 300V. If the difference (| V3-V1 |) is less than 260 V, proper wall charges do not accumulate between the scan electrode (Y) and the sustain electrode (Z) in the pre-reset period (Tf), so that the reset discharge in the subsequent reset period is prevented. If the difference (| V3-V1 |) is more than 300V, the possibility of flickering and discharging between the scan electrode (Y) and the sustain electrode (Z) becomes high.

Meanwhile, the bias voltage V3 supplied to the sustain electrode Z during the pre-reset period Tf is preferably larger than the bias voltage supplied to the sustain electrode Z during the reset period. This takes into account that the lowest voltage V1 of the second setdown signal during the pre-reset period Tf is higher than the lowest voltage V2 of the setdown signal during the reset period.

Meanwhile, the bias voltage V3 supplied to the sustain electrode Z during the pre-reset period Tf may be a sustain voltage Vs which is a voltage of the sustain pulse signal. In this case, the driving circuit can be simplified.

On the other hand, it is also possible to supply the positive pulse signal to the scan electrode Y before the second set down signal is supplied during the pre-reset period Tf. The pulse signal may have a voltage Vs of the sustain pulse signal, and may be implemented as a single sustain pulse signal. This pulse signal makes it possible to appropriately remove the wall charges in the discharge cells due to the sustain discharge in the previous subfield or the previous frame.

In order to facilitate wall charge cancellation, the pulse width T3 of the supplied pulse signal during the pre-reset period Tf is larger than the pulse width of the last sustain pulse signal of the previous subfield ((n-1) SF). It is preferable.

Meanwhile, the second set down signal during the pre-reset period Tf may include a first period T1 that falls to the lowest voltage V1 and a second period T2 that maintains the lowest voltage V1. . The longer the length of the second section T2 is, the lower the possibility of blinking and discharging during the pre-reset section Tf becomes. However, if the second section T2 becomes too long, the section margin in the subsequent reset section, the address section and the sustain section becomes small. Therefore, the pre-reset period Tf according to the embodiment of the present invention is preferably set within 100 ~ 500us.

In FIG. 5, the bias voltage section T4 during the pre-reset section Tf is longer than the pulse signal section T3 during the pre-reset section Tf.

Next, as illustrated in FIG. 5, during the pre-reset period Tf1, a pulse signal and a second set down signal are supplied to the scan electrode Y, and a positive bias voltage V3 is supplied to the sustain electrode Z. do. As described above, the lowest voltage V1 of the second setdown signal in the pre-reset period Tf1 is higher than the lowest voltage V2 of the setdown signal in the reset period.

Since the driving waveform of FIG. 6 is almost the same as the driving waveform of FIG. 5, the following description will focus on the difference.

In FIG. 5, the length of the first section T1 and the second section T2 in the second setdown signal is longer (T1> T2), but in FIG. 6, the first section T1 in the second setdown signal is longer. The second section T12 is longer than the section T11 (T11 <T12).

Since the second period T12 maintains the lowest voltage V1 of the second set-down signal, the longer the possibility of preventing mis-discharge is increased. However, if it is too long, the section margin in the subsequent reset section, address section and sustain section becomes small. Therefore, the preset period Tf1 according to the embodiment of the present invention is preferably set within 100 to 500 us.

Next, as shown in FIG. 5, during the pre-reset period Tf2, a pulse signal and a second set down signal are supplied to the scan electrode Y, and a positive bias voltage V3 is supplied to the sustain electrode Z. do. As described above, the lowest voltage V1 of the second setdown signal is higher than the lowest voltage V2 of the setdown signal of the reset period.

Since the driving waveform of FIG. 7 is almost the same as the driving waveform of FIG. 5, the following description will focus on the difference.

In FIG. 5, the bias voltage section T4 during the pre-reset section Tf is longer than the pulse signal section T3 during the pre-reset section T3 <T4. In FIG. 7, the pre-set section Tf2 is shown. The pulse signal section T23 during the pre-reset section Tf2 is longer (T23> T24) than the bias voltage section T24. That is, the pulse signal section T23 during the pre-reset section Tf2 is shown to be longer than the second set down signal section T21 + T22.

The longer the pulse signal section T23 is, the more smoothly the wall charge erase remaining by the discharge of the previous subfield ((n-1) SF) is performed during the pre-reset section Tf2. After that, the pulse electrode and the second set-down signal are supplied to the scan electrode Y, and the positive bias voltage V3 is supplied to the sustain electrode Z, whereby the scan electrode Y and the sustain electrode Z are stable. It builds up wall charges.

Although a preferred embodiment of the present invention has been described in detail above, those skilled in the art to which the present invention pertains can make various changes without departing from the spirit and scope of the invention as defined in the appended claims. It will be appreciated that modifications or variations may be made. Accordingly, modifications of the embodiments of the present invention will not depart from the scope of the present invention.

1 is a perspective view illustrating an embodiment of a structure of a plasma display panel.

2 is a cross-sectional view illustrating an embodiment of an electrode arrangement of a plasma display panel.

3 is a timing diagram illustrating an embodiment of a method of time-divisionally driving a plasma display panel by dividing one frame into a plurality of subfields.

4 is a timing diagram illustrating an embodiment of driving signals for driving a plasma display panel.

5 to 7 are timing diagrams illustrating waveforms of panel driving signals according to an exemplary embodiment of the present invention.

Claims (13)

A plasma display panel including a plurality of scan electrodes formed on the upper substrate, and sustain electrodes and a plurality of address electrodes formed on the lower substrate; And a driving unit supplying a driving signal to the plurality of electrodes. A reset signal including a set down signal is supplied to the scan electrode in a reset period of at least one of the plurality of subfields, In the pre-reset period before the reset period, a pulse signal and a second set down signal are sequentially supplied to the scan electrode, And the lowest voltage of the second set down signal in the pre reset period is higher than the lowest voltage of the set down signal in the reset period. The method of claim 1, And a positive bias voltage is supplied to the sustain electrode when the second setdown signal is supplied in the pre-reset period. The method of claim 2, And the bias voltage in the pre-reset period is greater than a positive bias voltage supplied to the sustain electrode in an address period. The method of claim 1, The second set down signal, And a second section for gradually decreasing to the lowest voltage and a second section for maintaining the lowest voltage. The method of claim 4, wherein And the second section is longer than the first section. The method of claim 1, Within the pre-reset interval, And the pulse signal section is longer than the second set down signal section. The method of claim 1, And the sustain electrode is floated when the set down signal is supplied within the reset period. The method of claim 1, And the pre-reset period is disposed between the last sustain pulse signal of the previous subfield and the reset signal. The method of claim 1, And a pulse width of the pulse signal in the pre-reset period is larger than a pulse width of the last sustain pulse signal of the previous subfield. The method of claim 1, And the pre-reset period is disposed between unit frames including a plurality of subfields. The method of claim 1, And the pre-reset period is 100 to 500us. The method of claim 2, And a voltage difference between the bias voltage and the lowest voltage of the second set-down signal within the pre-reset period is 260 to 300V. The method of claim 1, And the pulse signal in the pre-reset period comprises one sustain pulse signal.

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