KR20090118647A - Plasma display device - Google Patents

Abstract

PURPOSE: A plasma display device is provided to improve image quality by preventing flicker mis-discharge by accumulating the wall charge. CONSTITUTION: A first signal includes a first section(P1), a second section(P2), and a third section(P3) successively. In the first section, a positive first voltage(V1) is maintained in a scan electrode(Y) before a reset section. In the second section, the voltage is dropped from the first voltage to the second voltage. In the third section, the voltage is dropped from the second voltage to the third voltage gradually. The first signal is supplied to the scan electrode. The second signal is supplied to the sustain electrode. The second signal maintains a positive forth voltage and is supplied after the first signal. The second signal is overlapped with the second and third sections.

Description

Plasma display device

The present invention relates to a plasma display device, and more particularly, to an apparatus for driving a plasma display panel.

The plasma display panel (hereinafter referred to as PDP) displays an image by excitation and emitting phosphors by vacuum ultraviolet rays (VUV) generated when the inert gas is discharged.

Such a PDP is not only large in size and thin in thickness, but also has a simple structure and is easy to manufacture, and has a high luminance and high luminous efficiency compared to other flat display devices. In particular, the AC surface-discharge type 3-electrode plasma display panel has advantages of low voltage driving and long life because wall charges are accumulated on the surface during discharge to protect the electrodes from sputtering caused by the discharge.

The plasma display panel is time-division driven by a reset period for initializing all cells, an address period for selecting cells, and a sustain period for causing display discharge in the selected cells in order to realize gray levels of an image. do.

The PDP accumulates wall charges and uses them for discharging, and there is a problem in that the blinking and discharging phenomenon may occur due to the lack of wall charges, thereby degrading the image quality of the display image.

An object of the present invention is to provide a plasma display device which can prevent the flashing discharge due to the lack of wall charge and improve the gray scale expression.

According to an aspect of the present invention, there is provided a plasma display apparatus including: a plasma display panel including a scan electrode and a sustain electrode formed on an upper substrate; And a driving unit configured to supply a driving signal to the electrodes, and before the reset period of at least one of the plurality of subfields constituting one frame, a first period in which a positive first voltage is maintained; A second period gradually descending from the first voltage to the second voltage; And a first signal sequentially including a third section gradually descending from the second voltage to the third voltage to the scan electrode, and a second signal to maintain the fourth positive voltage is supplied to the sustain electrode. The second signal is supplied later than the first signal by a predetermined time, and the second signal is at least partially overlapped with the second and third sections.

The present invention can improve the gray scale expressive power, and can efficiently accumulate wall charges and lower the maximum voltage of the reset signal to prevent blinking and discharging. In particular, when sustain discharge is not generated in some subfields, the flashing erroneous discharge due to insufficient wall charges is prevented in the next subfield, thereby improving the image quality of the plasma display apparatus.

Hereinafter, a plasma display device according to the present invention will be described in detail with reference to the accompanying drawings. 1 is a perspective view illustrating an embodiment of a structure of a plasma display panel.

As shown in FIG. 1, the plasma display panel includes a scan electrode 11, a sustain electrode 12, a sustain electrode pair formed on the upper substrate 10, and an address electrode 22 formed on the lower substrate 20. It includes.

The sustain electrode pairs 11 and 12 generally include transparent electrodes 11a and 12a and bus electrodes 11b and 12b formed of indium tin oxide (ITO), and the bus electrodes 11b and 12b. 12b) may be formed of a metal such as silver (Ag) or chromium (Cr) or a stack of chromium / copper / chromium (Cr / Cu / Cr) or a stack of chromium / aluminum / chromium (Cr / Al / Cr). . The bus electrodes 11b and 12b are formed on the transparent electrodes 11a and 12a to serve to reduce voltage drop caused by the transparent electrodes 11a and 12a having high resistance.

Meanwhile, according to the exemplary embodiment of the present invention, the sustain electrode pairs 11 and 12 may not only have a structure in which the transparent electrodes 11a 12a and the bus electrodes 11b and 12b are stacked, but also the buses without the transparent electrodes 11a and 12a. Only the electrodes 11b and 12b may be configured. This structure does not use the transparent electrodes (11a, 12a), there is an advantage that can lower the cost of manufacturing the panel. The bus electrodes 11b and 12b used in this structure may be various materials such as photosensitive materials in addition to the materials listed above.

Between the transparent electrodes 11a and 12a of the scan electrode 11 and the sustain electrode 12 and the bus electrodes 11b and 11c, external light generated from the outside of the upper substrate 10 is absorbed to reduce reflection. Black matrixes (BMs, 15) are arranged that function to block light and to improve the purity and contrast of the upper substrate 10.

The black matrix 15 according to the exemplary embodiment of the present invention is formed on the upper substrate 10, the first black matrix 15 and the transparent electrodes 11a and 12a formed at positions overlapping the partition wall 21. And the second black matrices 11c and 12c formed between the bus electrodes 11b and 12b. Here, the first black matrix 15 and the second black matrices 11c and 12c, also referred to as black layers or black electrode layers, may be simultaneously formed and physically connected in the formation process, or may not be simultaneously formed and thus not physically connected. .

In addition, when physically connected and formed, the first black matrix 15 and the second black matrix 11c and 12c may be formed of the same material, but may be formed of different materials when they are formed separately.

The upper dielectric layer 13 and the passivation layer 14 are stacked on the upper substrate 10 having the scan electrode 11 and the sustain electrode 12 side by side. Charged particles generated by the discharge are accumulated in the upper dielectric layer 13, and the protective electrode pairs 11 and 12 may be protected. The protective film 14 protects the upper dielectric layer 13 from sputtering of charged particles generated during gas discharge, and increases emission efficiency of secondary electrons.

In addition, the address electrode 22 is formed in a direction crossing the scan electrode 11 and the sustain electrode 12. In addition, a lower dielectric layer 24 and a partition wall 21 are formed on the lower substrate 20 on which the address electrode 22 is formed.

In addition, the phosphor layer 23 is formed on the surfaces of the lower dielectric layer 24 and the partition wall 21. The partition wall 21 has a vertical partition wall 21a and a horizontal partition wall 21b formed in a closed shape, and physically distinguishes discharge cells, and prevents ultraviolet rays and visible light generated by the discharge from leaking into adjacent discharge cells.

In an embodiment of the present invention, not only the structure of the partition wall 21 illustrated in FIG. 1, but also the structure of the partition wall 21 having various shapes may be possible. For example, a channel in which a channel usable as an exhaust passage is formed in at least one of the differential partition structure, the vertical partition 21a, or the horizontal partition 21b having different heights of the vertical partition 21a and the horizontal partition 21b. A grooved partition structure having a groove formed in at least one of the type partition wall structure, the vertical partition wall 21a, or the horizontal partition wall 21b may be possible.

Here, in the case of the differential partition wall structure, the height of the horizontal partition wall 21b is more preferable, and in the case of the channel partition wall structure or the groove partition wall structure, it is preferable that a channel is formed or the groove is formed in the horizontal partition wall 21b. something to do.

Meanwhile, in one embodiment of the present invention, although the R, G and B discharge cells are shown and described as being arranged on the same line, it may be arranged in other shapes. For example, a Delta type arrangement in which R, G, and B discharge cells are arranged in a triangular shape may be possible. In addition, the shape of the discharge cell may be not only rectangular, but also various polygonal shapes such as a pentagon and a hexagon.

In addition, the phosphor layer 23 emits light by ultraviolet rays generated during gas discharge to generate visible light of any one of red (R), green (G), and blue (B). Here, an inert mixed gas such as He + Xe, Ne + Xe and He + Ne + Xe for discharging is injected into the discharge space provided between the upper / lower substrates 10 and 20 and the partition wall 21.

FIG. 2 illustrates an embodiment of an electrode arrangement of a plasma display panel, and a plurality of discharge cells constituting the plasma display panel are preferably arranged in a matrix form as shown in FIG. 2. The plurality of discharge cells are provided at the intersections of the scan electrode lines Y1 to Ym, the sustain electrode lines Z1 to Zm, and the address electrode lines X1 to Xn, respectively. The scan electrode lines Y1 to Ym may be driven sequentially or simultaneously, and the sustain electrode lines Z1 to Zm may be driven simultaneously. The address electrode lines X1 to Xn may be driven by being divided into odd-numbered lines and even-numbered lines, or sequentially driven.

Since the electrode arrangement shown in FIG. 2 is only an embodiment of the electrode arrangement of the plasma panel according to the present invention, the present invention is not limited to the electrode arrangement and driving method of the plasma display panel shown in FIG. 2. For example, a dual scan method in which two scan electrode lines among the scan electrode lines Y1 to Ym are simultaneously scanned is possible. In addition, the address electrode lines X1 to Xn may be driven by being divided up and down in the center portion of the panel.

3 is a timing diagram illustrating an embodiment of a time division driving method by dividing a frame into a plurality of subfields. The unit frame may be divided into a predetermined number, for example, eight subfields SF1, ..., SF8 to realize time division gray scale display. Each subfield SF1, ... SF8 is divided into a reset section (not shown), an address section A1, ..., A8 and a sustain section S1, ..., S8.

Here, according to an embodiment of the present invention, the reset period may be omitted in at least one of the plurality of subfields. For example, the reset period may exist only in the first subfield or may exist only in a subfield about halfway between the first subfield and all the subfields.

In each address section A1, ..., A8, a display data signal is applied to the address electrode X, and scan pulses corresponding to each scan electrode Y are sequentially applied.

In each of the sustain periods S1, ..., S8, a sustain pulse is alternately applied to the scan electrode Y and the sustain electrode Z to form wall charges in the address periods A1, ..., A8. Sustain discharge occurs in the discharge cells.

The luminance of the plasma display panel is proportional to the number of sustain discharge pulses in the sustain discharge periods S1, ..., S8 occupied in the unit frame. When one frame forming one image is represented by eight subfields and 256 gradations, each subfield in turn has different sustains at a ratio of 1, 2, 4, 8, 16, 32, 64, and 128. The number of pulses can be assigned. In order to obtain luminance of 133 gradations, cells may be sustained by addressing the cells during the subfield 1 section, the subfield 3 section, and the subfield 8 section.

The number of sustain discharges allocated to each subfield may be variably determined according to weights of the subfields according to the APC (Automatic Power Control) step. That is, in FIG. 3, a case in which one frame is divided into eight subfields has been described as an example. However, the present invention is not limited thereto, and the number of subfields forming one frame may be variously modified according to design specifications. . For example, a plasma display panel may be driven by dividing one frame into eight or more subfields, such as 12 or 16 subfields.

The number of sustain discharges allocated to each subfield can be variously modified in consideration of gamma characteristics and panel characteristics. For example, the gray level assigned to subfield 4 may be lowered from 8 to 6, and the gray level assigned to subfield 6 may be increased from 32 to 34.

4 is a timing diagram illustrating an embodiment of driving signals for driving a plasma display panel with respect to the divided subfield.

The subfield is a wall formed by a pre-reset section and a pre-reset section for forming positive wall charges on the scan electrodes Y and negative wall charges on the sustain electrodes Z. A reset section for initializing the discharge cells of the entire screen using the charge distribution, an address section for selecting the discharge cells, and a sustain section for maintaining the discharge of the selected discharge cells.

The reset section includes a setup section and a setdown section. In the setup section, rising ramp waveforms (Ramp-up) are simultaneously applied to all scan electrodes to generate fine discharges in all discharge cells. Thus, wall charges are generated. In the set-down period, a falling ramp waveform (Ramp-down) falling at a positive voltage lower than the peak voltage of the rising ramp waveform (Ramp-up) is simultaneously applied to all the scan electrodes (Y), thereby eliminating discharge discharge in all the discharge cells. Generated, thereby eliminating unnecessary charges during wall charges and space charges generated by the setup discharges.

In the address period, a negative scan signal scan is sequentially applied to the scan electrode, and at the same time, a data signal data having a positive address voltage Va is applied to the address electrode X. The address discharge is generated by the voltage difference between the scan signal and the data signal and the wall voltage generated during the reset period, thereby selecting the cell. Meanwhile, a signal for maintaining a sustain voltage is applied to the sustain electrode during the set down period and the address period.

In the sustain period, a sustain pulse having a sustain voltage Vs is alternately applied to the scan electrode and the sustain electrode to generate sustain discharge in the form of surface discharge between the scan electrode and the sustain electrode.

The driving waveforms shown in FIG. 4 are exemplary embodiments of signals for driving the plasma display panel according to the present invention, and the present invention is not limited to the waveforms shown in FIG. 4. For example, the pre-reset period may be omitted, and the polarity and the voltage level of the driving signals illustrated in FIG. 4 may be changed as necessary. After the sustain discharge is completed, an erase signal for erasing wall charge may be applied to the sustain electrode. May be authorized. In addition, the single sustain driving may be performed by applying the sustain signal to only one of the scan electrode (Y) and the sustain (Z) electrode to generate a sustain discharge.

The present invention provides a plasma display panel including a scan electrode and a sustain electrode formed on an upper substrate; And a driving unit supplying a driving signal to the electrodes.

A first period in which a first positive voltage is maintained before a reset period of at least one of the plurality of subfields constituting one frame; A second period gradually descending from the first voltage to a second voltage; And a first signal sequentially including a third section gradually descending from the second voltage to the third voltage, to the scan electrode, and a second signal to maintain the positive fourth voltage to the sustain electrode. ,

The second signal is supplied later than the first signal by a predetermined time, and the second signal is configured to overlap at least partially with the second and third sections.

In addition, a sustain signal is not supplied to the scan electrode and the sustain electrode in the first subfield of the plurality of subfields.

The first signal may be configured to be supplied between the reset period of the first subfield and the second subfield.

More preferably, the predetermined time may be configured to be 1 ms to 9 ms.

In addition, the amount of light generated in the first section may be configured to be 0.4 to 0.6 times the amount of light generated when a pair of sustain signals are supplied to the scan electrode and the sustain electrode, and the first voltage or the fourth voltage is a sustain voltage. It can be characterized by.

5 is a timing diagram illustrating a driving waveform according to an embodiment of the present invention.

Referring to FIG. 5, a first period P1 in which a first positive voltage V1 of the positive polarity is maintained on the scan electrode Y before a reset period; A second period P2 gradually descending to the second voltage V2; And a first signal sequentially including a third section P3 gradually descending to a third voltage V3, and maintaining a fourth positive voltage V4 with the sustain electrode Z. The signal is supplied. Before the supply of the second signal, the sustain electrode maintains a ground (GND) voltage. The second signal is supplied later than the first signal by a predetermined time, and the second signal at least partially overlaps the second and third sections.

As shown in FIG. 5, since the second signal is supplied later than the first signal by a predetermined time, at least a portion of a period for maintaining the voltage of the first period P1 and the sustain electrode as the ground GND voltage is at least partially. There is an overlapping section W1. The section W1 is equal to the predetermined time. The sustain electrode controls the wall charge amount of the scan electrode by supplying the first voltage of the positive polarity to the scan electrode while maintaining the ground (GND) voltage, thereby preventing the flashing misdischarge due to the lack of wall charge in the subsequent subfield. have.

The first voltage or the fourth voltage may be configured to be substantially the same as the sustain voltage in consideration of ease of circuit configuration and cost.

6 is a view showing another embodiment of the present invention.

Referring to FIG. 6, the period in which the positive fourth voltage V4 is applied to the sustain electrode Z is supplied later than the first signal by a predetermined time, and starts in the first period P1 and partially between P1 and P1. It has a period W1 overlapping. In addition, the sustain period of the fourth voltage may be configured to partially overlap the second period P2 and the third period P3. During the period W1 in which the potential difference between the scan electrode Y and the sustain electrode Z is maintained, the wall charges due to the applied voltage can be efficiently controlled to prevent the flashing erroneous discharge due to the wall charge shortage.

More preferably, the overlapping section W1 or the predetermined time is more preferably 1 ms to 9 ms. If the predetermined time is 1 ms or more, the interval where the potential difference between the sustain electrode Z and the scan electrode Y is maintained is sufficient because sufficient time is secured so that weak discharge can stably occur. In addition, if the predetermined time exceeds 9 ms, the driving signal becomes longer than necessary, which is disadvantageous for high-speed driving, and strong discharge may occur, thereby reducing the effect of enabling fine expression of gray scales.

When the reset period is set down, a bias voltage V5 may be applied to the sustain electrode to help erase unnecessary wall charges. If the bias voltage is too high, the entire position with the scan electrode Y may be so large that mis-discharge may occur, the bias voltage V5 may be configured to be smaller than the voltage V4.

When the sustain signal is supplied to the sustain electrode Z, the discharge cell selected by the address discharge is added with the wall voltage in the discharge cell and the voltage of the sustain signal, thereby causing a sustain discharge, that is, a display discharge, between the scan electrode and the sustain electrode. Accordingly, in the low gradation subfield, the light due to the discharge generated between the scan signal and the data signal in the address period and the light due to the sustain signal supplied to the sustain electrode Z in the sustain period are summed to implement the gray scale of the image. Here, assuming that the gray scale of the light implemented by the pair of sustain signals is one gray scale, one or less gray scales cannot be expressed, and thus detailed gray scale expression is difficult.

        Since light is generated by the weak discharge in the first section, in particular, the W1 section, it can be used for gray scale expression. The amount of light generated in the first section may be 0.4 to 0.6 times the amount of light generated when a pair of sustain signals are applied to the scan electrode and the sustain electrode.

        The address discharge generated between the scan signal and the data signal in the address period is generated between the scan electrode Y and the address electrode X in the discharge cell, and the gray level of the light generated by the address discharge is applied to the sustain signal. It is relatively small compared to the gradation of light realized by Therefore, the gray scale of light generated by the address discharge can be expressed with a gray scale smaller than one.

       Therefore, as shown in FIG. 7, the sustain signal is not supplied to both the scan electrode Y and the sustain electrode Z in the sustain period, so that the sum of the total gray levels can be implemented as light having a gray level less than 1 in the low gray level subfield. Accordingly, it is possible to implement more detailed gradation compared to the conventional method of supplying one or more pairs of sustain signals in all subfields.

       However, if the sustain discharge is omitted in any subfield, the wall charges formed by the sustain discharge cannot be taken to the next subfield. Therefore, if the reset discharge is not sufficiently large, the risk of blinking and false discharge increases. Therefore, when the sustain signal is not applied in the previous subfield, the first and second signals may be supplied before the next subfield reset period, thereby preventing flickering and erroneous discharge. It is also added to the light generated by the address room display, allowing for more detailed gradation expression.

        In addition, since the first subfield has the lowest sustain discharge, the first signal may be supplied between the reset period of the first subfield and the second subfield.

        Referring to FIG. 5, the positive voltage V4 is applied to the sustain electrodes Z, the voltage is lowered to V2 at the scan electrodes Y (P2), and then lowered to the negative voltage V3. The ground (P3) ramp waveform is applied. The voltage V2 may be a ground voltage and the second period P2 may include a period for maintaining the voltage V2 after reaching the voltage V2. During this period, 0V is applied to the address electrodes.

        The negative voltage and the V2 voltage cause dark discharge between the scan electrode Y and the sustain electrode Z in all discharge cells. As a result of this discharge, positive wall charges are accumulated on the scan electrode Y in all the discharge cells, and a large amount of negative wall charges are accumulated on the sustain electrode Z. Due to the wall charge distribution, a sufficiently large positive gap voltage is formed between the scan electrode Y and the sustain electrode Z in the internal discharge gas space of all the discharge cells, and the sustain electrode Z is formed from the scan electrode Y in each discharge cell. Electric field is formed toward). In the setup period of the electric field and the subsequent reset period, the positive discharge voltage applied to the scan electrode is added to perform a reset discharge. Therefore, if the wall charge is sufficiently accumulated before the reset period, the reset discharge can be stably performed even when the maximum voltage of the reset signal is lowered, and the power efficiency can be improved.

        Although a preferred embodiment of the present invention has been described in detail above, those skilled in the art to which the present invention pertains can make various changes without departing from the spirit and scope of the invention as defined in the appended claims. It will be appreciated that modifications or variations may be made. Accordingly, modifications to future embodiments of the present invention will not depart from the technology of the present invention.

1 is a perspective view showing an embodiment of the structure of a plasma display panel according to the present invention.

2 is a diagram illustrating an embodiment of an electrode arrangement of a plasma display panel.

FIG. 3 is a timing diagram illustrating an embodiment of a method of time-divisionally driving a plasma display panel by dividing one frame into a plurality of subfields.

4 is a timing diagram illustrating an embodiment of a waveform of a driving signal for driving a plasma display panel.

5 to 7 are timing diagrams illustrating embodiments of waveforms of driving signals for driving a plasma display panel according to the present invention.

Claims (5)

A plasma display panel including a scan electrode and a sustain electrode formed on the upper substrate; And a driving unit supplying a driving signal to the electrodes. A first period in which a first positive voltage is maintained before a reset period of at least one of the plurality of subfields constituting one frame; A second period gradually descending from the first voltage to a second voltage; And a first signal sequentially including a third section gradually descending from the second voltage to the third voltage, to the scan electrode, and a second signal to maintain the positive fourth voltage to the sustain electrode. , And the second signal is supplied later than the first signal by a predetermined time, and the second signal is at least partially overlapped with the second and third sections. The method of claim 1, In the first subfield of the plurality of subfields, a sustain signal is not supplied to the scan electrode and the sustain electrode. And the first signal is supplied between the reset period of the first subfield and the second subfield. The method of claim 1, And said predetermined time is 1 ms to 9 ms. The method of claim 1, The amount of light generated in the first section is 0.4 to 0.6 times the amount of light generated when a pair of sustain signals are supplied to the scan electrode and the sustain electrode. The method of claim 1, Wherein the first voltage or the fourth voltage is a sustain voltage.

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