KR100806311B1 - Plasma display panel device - Google Patents

Abstract

A plasma display apparatus is provided to improve black brightness by preventing the erroneous discharge of wall charges accumulated in discharge cells before applying address signals. A plasma display apparatus includes a front panel having first and second electrodes, a rear panel having third electrodes opposite to the first and second electrodes, and plural discharge cells disposed between the first and second electrodes and third electrodes. A first signal is applied to the first electrodes during a reset period including a sustain interval while a first voltage level(V1) is maintained and a shutdown interval while a voltage level is gradually decreased. A second signal, which is equal to the first voltage level, having a second voltage level(V2) is supplied to the second electrodes at a start time or before the start time of the shutdown interval during the sustain period. The second signal has a third voltage level(V3) smaller than the second voltage level after the termination of the supplement of the second voltage level.

Description

Plasma display panel device

1 is a perspective view showing a first embodiment of a plasma display panel according to the present invention.

2 is an electrode arrangement diagram showing a first embodiment of the electrode arrangement of the plasma display panel according to the present invention.

3 is a timing diagram illustrating a first embodiment of a method of time-division driving by dividing a frame into a plurality of subfields.

4 is a timing diagram showing a first embodiment of a drive signal for driving a plasma display panel according to the present invention;

5 is a timing diagram showing a second embodiment of a drive signal for driving a plasma display panel according to the present invention;

<Explanation of symbols on main parts of the drawings>

10: upper substrate 11: scan electrode

12: sustain electrode 11a, 12a: transparent electrode

11b and 12b: metal bus electrodes 11c and 12c: second black matrix

13: upper dielectric layer 14: protective film

15: first black matrix 20: lower substrate

21: bulkhead 21a: vertical bulkhead

21b: transverse bulkhead 22: address electrode

23 phosphor layer 24 lower dielectric layer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display device, and more particularly, to a plasma display device for preventing erroneous discharge due to discharge imbalance during initial discharge of a discharge cell and reducing black brightness.

Plasma display devices are not only easy to enlarge and thin, but also have a simple structure, which makes them easy to manufacture and has a higher luminance and higher luminous efficiency than other flat panel displays.

Conventionally, a plasma display apparatus includes a front panel on which first electrodes and second electrodes are formed, and a plasma display panel bonded to a back panel on which third electrodes facing the first electrodes and the second electrodes are formed; And a driving circuit for configuring a display screen of the plasma display panel.

Here, discharge cells are formed at the intersections of the first, second, and third powers. In addition, the discharge cells accumulate charge according to a reset signal including a first signal that rises rapidly up to a first voltage applied from the driving circuit and a second signal that gradually rises up to a second signal.

However, the conventional plasma display apparatus has a problem in that a false discharge occurs and the black brightness decreases in the reset period due to an imbalance of charges accumulated in the discharge cells during the initial discharge.

SUMMARY OF THE INVENTION The present invention has been made to improve the above-mentioned problems of the prior art, and provides a plasma display device which prevents discharge due to imbalance of accumulated charge by applying a first signal rising to a first voltage to a discharge cell in a reset period. Its purpose is to.

According to an aspect of the present invention, there is provided a plasma display device including: a front panel on which first and second electrodes are formed; a back panel on which third electrodes facing the first and second electrodes are formed; And a plurality of discharge cells disposed at the intersections of the first and second electrodes and the third electrode, and providing a first signal having a first voltage level to the first electrode for initial discharge of the discharge cells in a reset period. Supply.

In addition, a plasma display device according to the present invention includes a front panel on which first and second electrodes are formed, a back panel on which third electrodes opposing the first and second electrodes are formed, and the first and second electrodes. And a plurality of discharge cells disposed at an intersection of the third electrode and the third electrode, and supplying a first signal having a first voltage level to the first electrode for initial discharge of the discharge cell in a reset period, The second electrode is supplied with a second signal having a second voltage level.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. 1 is a perspective view showing a first embodiment of a plasma display panel according to the present invention.

Referring to FIG. 1, the plasma display panel 30 according to the present invention is provided on the first electrode 11, the second electrode 12, and the rear panel 20, which are pairs of storage electrodes formed on the front panel 10. The third electrode 22 is formed.

The sustain electrode pairs 11 and 12 generally include transparent electrodes 11a and 12a and bus electrodes 11b and 12b formed of indium tin oxide (ITO), and bus electrodes 11b and 12b. Silver may be formed of a metal such as silver (Ag), chromium (Cr), or a lamination of chromium / copper / chromium (Cr / Cu / Cr) or a lamination of chromium / aluminum / chromium (Cr / Al / Cr). The bus electrodes 11b and 12b are formed on the transparent electrodes 11a and 12a to serve to reduce voltage drop caused by the transparent electrodes 11a and 12a having high resistance.

Meanwhile, according to the first embodiment of the present invention, the sustain electrode pairs 11 and 12 have a structure in which the transparent electrodes 11a 12a and the bus electrodes 11b and 12b are stacked, and the bus electrodes 11b and 12b are disposed on the top. In addition to the listed materials, various materials such as photosensitive silver (Ag) may be possible.

Between the transparent electrodes 11a and 12a of the first electrode 11 and the second electrode 12 and the bus electrodes 11b and 11c, external light generated from the outside of the front panel 10 is absorbed to reduce reflection. The main is arranged a black matrix (BM, 15) that functions to block the light and to improve the purity (purity) and contrast of the front substrate (10).

The black matrix 15 according to the first embodiment of the present invention is formed on the front panel 10. The first black matrix 15 and the transparent electrodes 11a, which are formed at positions overlapping the partition wall 21 are formed. The second black matrices 11c and 12c formed between 12a and the bus electrodes 11b and 12b may be formed. Here, the first black matrix 15 and the second black matrices 11c and 12c referred to as black layers may be simultaneously formed and physically connected in the formation process, and may not be simultaneously formed so as not to be physically connected. The black matrix 15 may not be formed, and the black matrix 15 may be integral with only the second black matrices 11c and 12c.

In addition, when physically connected and formed, the first black matrix 15 and the second black matrix 11c and 12c may be formed of the same material, but may be formed of different materials when they are formed separately.

Here, the bus electrodes 11b and 12b are stacked with the stacked second black matrices 11c and 12c and the transparent electrodes 11a and 12a. In other words, the bus electrodes 11b and 12b are stacked at predetermined distances from one edges of the second black matrices 11c and 12c and stacked with the transparent electrodes 11a and 12a by the predetermined distance.

Accordingly, the bus electrodes 11b and 12b are integrally formed by being stacked by being separated by the predetermined distance from one edges of the second black matrices 11c and 12c, but may be formed as a separate type instead of an integral type.

An upper dielectric layer 13 and a passivation layer 14 are stacked on the front panel 10 having the first electrode 11 and the second electrode 12 side by side. Charged particles generated by the discharge are accumulated in the upper dielectric layer 13, and may function to protect the sustain electrode pairs 11 and 12. The protective film 14 protects the upper dielectric layer 13 from sputtering of charged particles generated during gas discharge, and increases emission efficiency of secondary electrons. In addition, magnesium oxide (MgO) may be generally used for the protective film 14, and Si-MgO to which silicon (Si) is added may be used. Here, the content of silicon (Si) added to the protective film 14 may be 50PPM to 200PPM based on the weight percent (wt%).

Meanwhile, the third electrode 22 is formed in the direction crossing the first electrode 11 and the second electrode 12. In addition, the lower dielectric layer 24 and the partition wall 21 are formed on the rear panel 20 on which the third electrode 22 is formed.

In addition, the phosphor layer 23 is formed on the surfaces of the lower dielectric layer 24 and the partition wall 21. The partition wall 21 has a vertical partition wall 21a and a horizontal partition wall 21b formed in a closed shape, and physically distinguishes discharge cells, and prevents ultraviolet rays and visible light generated by the discharge from leaking into adjacent discharge cells.

In the first embodiment of the present invention, not only the structure of the partition wall 21 illustrated in FIG. 1, but also the structure of the partition wall 21 having various shapes may be possible. For example, a channel type having a channel that can be used as an exhaust passage in at least one of a differential partition structure, a vertical partition 21a, or a horizontal partition 21b having different heights of the vertical partition 21a and the horizontal partition 21b. The barrier rib structure having a groove formed in at least one of the barrier rib structure, the vertical barrier rib 21a or the horizontal barrier rib 21b may be possible.

Here, in the case of the differential partition wall structure, the height of the horizontal partition wall 21b is more preferable, and in the case of the channel partition wall structure or the groove partition wall structure, it is preferable that a channel is formed or the groove is formed in the horizontal partition wall 21b. something to do.

On the other hand, in the first embodiment of the present invention is shown and described that each of the R, G and B discharge cells are arranged on the same line, it may be arranged in a different shape. For example, a Delta type arrangement in which R, G, and B discharge cells are arranged in a triangular shape may be possible. In addition, the shape of the discharge cell may be not only rectangular, but also various polygonal shapes such as a pentagon and a hexagon.

In addition, the phosphor layer 23 emits light by ultraviolet rays generated during gas discharge to generate visible light of any one of red (R), green (G), and blue (B). Here, an inert mixed gas such as He + Xe, Ne + Xe and He + Ne + Xe for discharging is injected into the discharge space provided between the upper / lower substrates 10 and 20 and the partition wall 21.

FIG. 2 is a diagram showing a first embodiment of the electrode arrangement structure of the plasma display panel.

Referring to FIG. 2, the plurality of discharge cells constituting the plasma display panel 30 may be arranged in a matrix form. The plurality of discharge cells are provided at the intersections of the first electrode lines Y1 to Ym, the second electrode lines Z1 to Zm, and the third electrode lines X1 to Xn, respectively. The first electrode lines Y1 to Ym may be driven sequentially or simultaneously, and the second electrode lines Z1 to Zm may be driven simultaneously. The third electrode lines X1 to Xn may be divided into odd-numbered lines and even-numbered lines to be driven or sequentially driven.

Here, the electrode arrangement shown in FIG. 2 is only a first embodiment of the electrode arrangement structure of the plasma display panel 30 according to the present invention, and thus the present invention is an electrode of the plasma display panel 30 shown in FIG. It is not limited to the arrangement and driving method. For example, a dual scan method in which two first electrode lines among the first electrode lines Y1 to Ym are simultaneously scanned is also possible. In addition, the third electrode lines X1 to Xn may be driven by being divided up and down in the center portion of the panel.

3 is a timing diagram illustrating a first embodiment of a method of time-division driving by dividing one frame into a plurality of subfields.

Referring to FIG. 3, a unit frame may be divided into a predetermined number, for example, eight subfields SF1,..., SF8 to realize time division gray scale display. Each subfield SF1, ... SF8 is divided into a reset section (not shown), an address section A1, ..., A8 and a sustain section S1, ..., S8.

Here, according to the first embodiment of the present invention, the reset period may be omitted in at least one of the plurality of subfields. For example, the reset period may exist only in the first subfield or may exist only in a subfield about halfway between the first subfield and all the subfields.

In each address section A1, ..., A8, a display data signal is applied to the address electrode X, and scan pulses corresponding to each scan electrode Y are sequentially applied.

In each of the sustain periods S1, ..., S8, a sustain pulse is alternately applied to the scan electrode Y and the sustain electrode Z to form wall charges in the address periods A1, ..., A8. Sustain discharge occurs in the discharge cells.

The luminance of the plasma display panel is proportional to the number of sustain discharge pulses in the sustain discharge periods S1, ..., S8 occupied in the unit frame. When one frame forming one image is represented by eight subfields and 256 gradations, each subfield in turn has different sustains at a ratio of 1, 2, 4, 8, 16, 32, 64, and 128. The number of pulses can be assigned. In order to obtain luminance of 133 gradations, cells may be sustained by addressing the cells during the subfield 1 section, the subfield 3 section, and the subfield 8 section.

The number of sustain discharges allocated to each subfield may be variably determined according to weights of the subfields according to the APC (Automatic Power Control) step. That is, in FIG. 8, a case in which one frame is divided into eight subfields has been described as an example. However, the present invention is not limited thereto, and the number of subfields forming one frame may be variously modified according to design specifications. . For example, a plasma display panel may be driven by dividing one frame into eight or more subfields, such as 12 or 16 subfields.

The number of sustain discharges allocated to each subfield can be variously modified in consideration of gamma characteristics and panel characteristics. For example, the gray level assigned to subfield 4 may be lowered from 8 to 6, and the gray level assigned to subfield 6 may be increased from 32 to 34.

4 is a timing diagram showing a first embodiment of a drive signal for driving a plasma display panel according to the present invention.

Referring to FIG. 4, a driving signal applied during one subfield among a plurality of divided subfields is shown.

The driving signal is used to form positive wall charges on the first electrode 11, negative wall charges on the second electrode 12, and to initialize discharge cells of the entire screen of the plasma display panel 30. A reset period, an address period for selecting the discharge cells, and a sustain period for maintaining discharge of the selected discharge cells.

The reset period is a sustain period and a set-down (setdown) made of a period, the sustain period, the first signal having a first voltage (V1) to the first electrode 11 is applied to the micro-discharge is generated in the discharge cells the wall charge Is generated. In the set down period, a set down signal gradually decreasing at a positive voltage equal to or lower than the first voltage V1 is applied to the first electrode to generate an erase discharge in the discharge cell, and is generated by the fine discharge in the sustain period. Eliminate unnecessary charges among wall charges and space charges.

Here, the first signal rises by the first voltage V1 to maintain the voltage level for the first predetermined time T1. At this time, the first voltage V1 is the sustain voltage Vs, and preferably, is 180V to 200V. The first voltage V1 uses a voltage supplied from a first electrode driving circuit (not shown).

In addition, the first predetermined time T1 of the first signal is preferably 140us to 160us, and the first voltage V1 is supplied for the first predetermined time T1 to balance the wall charge imbalance inside the discharge cell. Can be adjusted.

In the address period, the negative scan signal scan is sequentially applied to the first electrode 11, and at the same time, the positive data signal data is applied to the third electrode 21. The address discharge is generated by the voltage difference between the scan signal and the data signal and the wall charge generated during the reset period to select the discharge cell.

Meanwhile, during the set down period and the address period, a sustain signal is applied to the second electrode 12 to generate sustain discharge in the form of surface discharge between the first electrode 11 and the second electrode 12.

The driving signals shown in FIG. 4 are first embodiments of signals for driving the plasma display panel according to the present invention, and the present invention is not limited by the signals shown in FIG. For example, among the signals shown in FIG. 4, a pre-reset section may be included. The polarity and the voltage level of the driving signals shown in FIG. 4 may be changed as necessary, and after the sustain discharge is completed, the wall charge erase may be performed. An erase signal may be applied to the second electrode 12. In addition, the single sustain driving may be performed by applying the sustain signal to only one of the first electrode 11 and the second electrode 12 to generate a sustain discharge.

5 is a timing diagram illustrating a second embodiment of a drive signal for driving a plasma display panel according to the present invention.

Referring to FIG. 5, a driving signal applied during one subfield among a plurality of divided subfields is illustrated.

The driving signal is used to form positive wall charges on the first electrode 11, negative wall charges on the second electrode 12, and to initialize discharge cells of the entire screen of the plasma display panel 30. A reset period, an address period for selecting the discharge cells, and a sustain period for maintaining discharge of the selected discharge cells.

The reset period is a sustain period and a set-down (setdown) made of a period, the sustain period, the first signal having a first voltage (V1) to the first electrode 11 is applied to the micro-discharge is generated in the discharge cells the wall charge Is generated. In the set down period, a set down signal gradually decreasing at a positive voltage equal to or lower than the first voltage V1 is applied to the first electrode 11 to generate an erase discharge in a discharge cell, and The unnecessary charges among the wall charges and the space charges generated by the same are erased.

Here, the first signal applied to the first electrode 11 in the sustain period is increased by the first voltage V1 to maintain the voltage level for the first predetermined time T1. At this time, the first voltage V1 is the sustain voltage Vs, and preferably, is 180V to 200V. The first voltage V1 uses a voltage supplied from a first electrode driving circuit (not shown).

In addition, the first predetermined time T1 of the first signal is preferably 140us to 160us, and the first voltage V1 is supplied for the first predetermined time T1 to balance the wall charge imbalance inside the discharge cell. Can be adjusted.

The second signal applied to the second electrode 12 in the sustain period is increased by the second voltage V2 after a second predetermined time T2 has elapsed at the time of applying the first signal, and the first signal is increased. At the end of, the voltage drops to the third voltage V3 before the third predetermined time T3.

Here, the second voltage V2 of the second signal is lower than or equal to the sustain voltage Vs, greater than the Z-bias voltage Vzb, and preferably 100V to 200V. That is, the wall charges generated in the discharge cell are fine discharges of the wall charges generated by the first signal applied to the first electrode 11 and the wall charges generated by the second signal applied to the second electrode 12. To keep the balance.

In addition, the second predetermined time T2 of the second signal is a time when the second signal is applied after the application time point of the first signal, preferably 140us to 160us. That is, discharging due to the first signal applied to the first electrode 11 and the second signal applied to the second electrode 12 is prevented, and erroneous discharge due to wall charge in the discharge cell is prevented.

In addition, the third voltage V3 of the second signal is a Z-bias voltage Vzb and is lower than the second voltage V2. In addition, the third predetermined time T3 of the second signal is preferably about 8us to 12us faster than the falling time of the first signal.

In the address period, the negative scan signal scan is sequentially applied to the first electrode 11, and at the same time, the positive data signal data is applied to the third electrode 21. The address discharge is generated by the voltage difference between the scan signal and the data signal and the wall charge generated during the reset period to select the discharge cell.

Meanwhile, during the set down period and the address period, a sustain signal is applied to the second electrode 12 to generate sustain discharge in the form of surface discharge between the first electrode 11 and the second electrode 12.

In the conventional plasma display device, the wall charges are accumulated in the discharge cells formed of the plurality of electrodes in the plasma display panel, and the black luminance is lowered due to misdischarge due to the ramp waveform gradually rising to the first electrode during the initial reset period. The plasma display device of the present invention can prevent the black luminance from being lowered by preventing discharge of wall charges accumulated by the first and second signals applied to the first and second electrodes during the initial reset period. have.

In addition, the plasma display apparatus of the present invention may also be a case where the first signal and the second signal are applied to any one of the first electrode and the second electrode.

Although a preferred embodiment of the present invention has been described in detail above, those skilled in the art to which the present invention pertains can make various changes without departing from the spirit and scope of the invention as defined in the appended claims. It will be appreciated that modifications or variations may be made. Accordingly, modifications to future embodiments of the present invention will not depart from the technology of the present invention.

In the plasma display device according to the present invention, a discharge signal is applied to a sustain period during an initial reset period by applying a first signal having a constant first voltage to the first electrode or applying a second signal having a second voltage to the second electrode. By preventing the accumulated wall charges from being discharged before the address signal is applied, the black brightness is improved, thereby improving the merchandise and efficiency of the product.

Claims (6)

A front panel on which a first electrode and a second electrode are formed; A rear panel on which third electrodes facing the first and second electrodes are formed; A plurality of discharge cells disposed at an intersection of the first and second electrodes and the third electrode, The first signal is applied to the first electrode in a reset period including a sustain period maintained at the first voltage level and a set-down period in which the voltage level gradually decreases. The second electrode is applied with a second signal having a second voltage level substantially equal to the first voltage level during the sustain period and before or at the start of the set-down period. The second signal is, And a third voltage level smaller than the second voltage level after termination of supply of the second voltage level. delete delete The method of claim 1, And the second signal of the third voltage level is applied to the second electrode while the first signal is applied to the first electrode in the set down period. The method of claim 1, wherein the first and second voltage levels, And a voltage level substantially equal to a voltage level of a signal having a positive voltage applied to the first and second electrodes in a sustain period in which the discharge cells are selected to display an image. The method of claim 1, And the first and second signals are supplied to the first and second electrodes only during a predetermined time period when the power is supplied again while the power is not supplied to the front panel.

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