KR20070053602A - Electric current sampling circuit - Google Patents

Abstract

The present invention is not affected by fluctuations in the drain voltage of the current-output MOS transistors or changes in the load characteristics at the time of writing and reading, and also when the output current range is wide. It is an object of the present invention to provide a current sampling circuit without this.

As a solution to the above, the present invention provides a current output MOS transistor M1 having a source connected to a power supply line, a voltage buffer 1 having an output connected to a gate of a current output MOS transistor M1, an input of a voltage buffer and a power supply. The data holding capacitor Cs provided between the lines, the second switch SW2 provided between the drain of the current output MOS transistor M1 and the input of the voltage buffer 1, the input terminal Tin and the current output MOS transistor. In parallel with the third switch SW3 provided between the drains of M1, the fourth switch SW4 provided between the output terminal Tout and the drain of the current output MOS transistor M1, and the data holding capacitor Cs. And a reference current generating circuit 4 connected to the input terminal Tin.

Description

Current Sampling Circuit {ELECTRIC CURRENT SAMPLING CIRCUIT}

1 is a circuit diagram showing a first embodiment of a current sampling circuit according to the present invention.

2 is a timing chart of the current sampling circuit shown in FIG. 1;

FIG. 3 is a circuit diagram showing a state at the time of holding the current sampling circuit shown in FIG.

4 is a circuit diagram showing a second embodiment of the current sampling circuit according to the present invention;

5 is a timing chart of the current sampling circuit shown in FIG. 4;

FIG. 6 is a circuit diagram showing a state when the current sampling circuit shown in FIG. 4 is held. FIG.

FIG. 7 is a circuit diagram showing a concrete embodiment of the current sampling circuit shown in FIG. 1. FIG.

8 is a timing chart of the current sampling circuit shown in FIG. 7;

FIG. 9 is a circuit diagram showing a concrete embodiment of the current sampling circuit shown in FIG. 4. FIG.

FIG. 10 is an explanatory diagram showing parasitic capacitance of each transistor provided in the charge path of the current sampling circuit shown in FIG. 9; FIG.

11 is a circuit diagram showing a third embodiment of the current sampling circuit according to the present invention.

12 is a timing chart of the current sampling circuit shown in FIG. 11;

13 is a circuit diagram showing a configuration of a reference current generation circuit.

14 is a circuit diagram showing another configuration of the reference current generation circuit.

Fig. 15 is a circuit diagram showing the structure of a conventional drive circuit using a current mirror circuit.

16 is a circuit diagram of a current sampling circuit without a voltage buffer.

17 is a timing chart of the current sampling circuit shown in FIG. 16;

FIG. 18 is a circuit diagram showing a state when the current sampling circuit shown in FIG. 16 is held; FIG.

<Explanation of symbols for the main parts of the drawings>

1: voltage buffer 2, 3: inverter

4: reference current generating circuits M1 to M12: MOS transistors

Cs: data holding capacity SW1 to SW5: switch

The present invention relates, for example, to a current sampling circuit which can be suitably used for a current output type driving circuit for driving an organic EL light emitting device of a passive matrix method or an active matrix method.

The current-voltage characteristic of the organic EL element exhibits nonlinear diode characteristics, and the current-luminance characteristic of the copper element exhibits linear characteristics. Thus, there is a threshold voltage in this type of display element. This threshold voltage is variable. Thus, for example, in the organic EL display panel, not a driving circuit of voltage control like a liquid crystal display, but a driving circuit of current control having a proportional relationship with luminance is used.

Patent document 1 discloses the data drive circuit comprised so that constant current drive of the organic electroluminescent element of a passive matrix type organic electroluminescent display device, and patent document 2 discloses the specific structure of the said data drive circuit.

Fig. 15 shows a configuration example of a conventional drive circuit using a current mirror circuit. This drive circuit has the structure which replaced the bipolar transistor which is a component of the data drive circuit of patent document 2 with the MOS transistor substantially, and is comprised by the output PMOS transistor and the PMOS / NMOS transistor for ON / OFF control.

<Patent Document 1>

Japanese Patent Publication No. 2002-108284

<Patent Document 2>

Japanese Patent Publication No. 2004-302273

In Fig. 15, the output MOS transistors M1, M2, ..., MN constitute a current mirror for the transistor MO, and each outputs a current corresponding to the reference current Iref flowing through the transistor MO. . This current mirror circuit assumes that all of the MOS transistors MO, M1, M2, ..., MN have the same transistor characteristics. However, the MOS transistors MO, M1, M2, ..., MN formed in the IC chip have variations in characteristics (for example, variations in the threshold voltage Vth), so that each output terminal OUT0 to OUTN-1 is present. It causes variation in the current value output from

As described above, since the organic EL element is a current-driven light emitting element, the light emission luminance is proportional to the current density flowing through the EL element. Thus, if there is a variation in the output current from the drive circuit, luminance unevenness occurs on the display. In particular, variations in output current between adjacent output terminals appear as linear luminance smears on the display. As is well known, since the human eye perceives a luminance difference of about 2%, this linear luminance unevenness is highly perceptible. Since the luminance difference of 2% corresponds to 2% of the variation of the output current between adjacent output terminals of the driving circuit, the current output driving circuit requires a technique for suppressing the variation of this output current.

The output current Ids flowing through the transistor Mi (i = 1, 2, 3 ... N) is expressed as follows.

Where K 'is the transconductance coefficient determined by the mobility of the carrier and the gate oxide film capacity per unit area, W is the channel width, L is the channel length, and Vgs is the gate-source voltage of the transistor Mi.

The output current Ids is varied by each parameter K ', W, L, and Vth. If the variation of the output current Ids due to the variation of each parameter is ΔIds, the ratio of this variation ΔIds to the output current Ids is expressed as follows.

The right side claim 1 of the formula (2) relates to the variation in size, and the second term relates to the process variation. The fluctuation in size can be neglected by sufficiently increasing the channel width W and the channel length L (10 m or more) and lowering the sensitivity to the fluctuation in this size. On the other hand, the variation in the transconductance coefficient K 'is negligible because the variation in the transconductance coefficient K' is smaller than the variation in the threshold voltage Vth. Thus, Equation (2) can be expressed as follows.

Here, ΔVth is a variation of the threshold voltage Vth.

Equation (3) shows that the influence of the variation ΔVth of the threshold voltage Vth is large on the variation of the output current Ids of the transistor Mi.

As one countermeasure for suppressing the variation of the output current Ids, it is conceivable to increase the gate-source voltage Vgs. However, increasing the gate-source voltage Vgs increases the start voltage of the saturation region, which is the constant current region of the MOS transistor. That is, the operating conditions in the saturated region of the MOS transistor are

Vds> Vgs-Vth

For this reason, when the gate-source voltage Vgs increases, the drain-source voltage Vds for operating in the saturation region increases.

Normally, transistors MO, M1, M2, ..., MN are used in the saturation region. For this reason, an increase in the drain-source voltage Vds of these transistors MO, M1, M2, ..., MN increases the power consumption Vds x Ids in the current mirror circuit and generates heat in the IC. Cause problems. In addition, the increase of the drain-source voltage Vds increases the required power supply voltage. In other words, the power supply voltage is preferably lower from the viewpoint of current consumption, cost of power supply, breakdown voltage, ease of design, and the like. Therefore, there is a limitation in the method of increasing the gate-source voltage Vgs to increase the variation of the output current Ids of the transistors MO, M1, M2, ..., MN.

In the case where the range of the output current Ids is wide, the fluctuation can be suppressed by using a place where the output current Ids is large. However, even when this method is used, the drain-source voltage Vds for operating in the saturation region is increased, and the power consumption of the current mirror circuit is increased. On the other hand, when a small output current is used, since the drain-source voltage Vds is lowered, the power consumption of the current mirror circuit is reduced, but it is impossible to suppress variations in the output current.

Therefore, as a means of solving the above problem, a current sampling circuit having a configuration as illustrated in FIG. 16 has been proposed.

The current sampling circuit includes a MOS transistor M1 having a source connected to a power supply line, a data holding capacitor Cs provided between the gate and the power supply line of the MOS transistor M1, and a drain of the MOS transistor M1. A switch SW3 provided between the gates, a switch SW3 provided between the input terminal Tin and the drain of the MOS transistor M1, and a switch provided between the output terminal Tout and the drain of the MOS transistor M1 ( SW4) and a switch SW1 provided in parallel with the data holding capacitor Cs. The switch SW1 is for discharging the electric charge of the data holding capacitor Cs as necessary (for example, initialization), and is usually turned OFF.

On the other hand, since this current sampling circuit is for one output terminal, it is actually arranged in the IC chip by the number corresponding to the number of output terminals required for the display panel.

17 is a timing chart showing the basic operation of the current sampling circuit. As shown in this timing chart, at the time of current writing, the switch SW2 and the switch SW3 are turned on, and the switch SW4 is turned off. Therefore, since the MOS transistor M1 is in a diode-connected state to flow the reference current Iref, the drain voltage (= gate voltage) of the transistor M1 corresponding to the reference current Iref is applied to the switch SW2. Through the data holding capacity (Cs) is charged (memorized). Thereafter, the switch SW2 is turned OFF, and then the switch SW3 is turned OFF to be in a hold state.

In the read (output) period, the switch SW4 is turned on while the switches SW2 and SW3 are turned off. Therefore, the MOS transistor M1 outputs a current Iout determined by the gate voltage stored in the data holding capacitor Cs. Since the stored gate voltage is a voltage determined according to the reference current Iref, the relationship of Iout = Iref holds.

According to this current sampling circuit, even if the threshold voltage Vth of the MOS transistor M1 fluctuates by ΔVth from the threshold voltage of the MOS transistor M1 of the adjacent non-illustrated current sampling circuit, this variation ΔVth This is compensated. This is because the voltage held in the data holding capacitor Cs in the writing period is a voltage determined according to the reference current Iref. Specifically, when the voltage stored in the data storage capacitor Cs is Vs when the MOS transistor M1 having the threshold voltage is Vth, the data is stored when the MOS transistor M1 having the threshold voltage Vth + ΔVth is used. The voltage stored in the holding capacitor Cs is Vs + ΔVth. Therefore, the variation ΔVth of the threshold voltage does not affect the output current Iout.

By the way, when a current output type drive circuit is constructed using the above-described current sampling circuit, the capacity value of the data holding capacitor Cs cannot be made very large because the writing period cannot be set very long. In addition, the current sampling circuit has a problem that, when used in a driving circuit of a high gradation display, a change of about several mV of the voltage held in the data holding capacitor Cs is perceived as a change in luminance.

In the current sampling circuit, the drain voltage and the gate voltage of the MOS transistor M1 are the same at the time of writing. However, the difference occurs between the drain voltage and the gate voltage at the time of current reading (output). This is because the drain voltage of the MOS transistor M1 is determined based on the power supply voltage at the time of writing, but at the time of current reading the power supply voltage or the load characteristics of the load circuit (the circuit on the display panel side) of the output terminal Tout side ( 1 V characteristics). Therefore, the drain voltage of the MOS transistor M1 may be several volts or different at the time of current writing and current reading.

For example, even if the drain voltage at a certain output voltage is set at the time of writing and reading, if the range of the output current Iout is wide, the drain voltage at the time of current reading changes according to the output current. As a result, the drain voltage at the time of current writing and the current reading is different. In addition, the drain voltage at the time of a current read may fluctuate largely by the change of the load (organic EL element or TFT) on the display panel side.

18 shows a state in the hold operation of the current sampling circuit. In this state, the gate of the MOS transistor M1 is electrically floating, and the MOS transistor M1 is formed by the drain-gate capacitance Cgd originally owned by the MOS transistor M1 itself. The gate and the drain are in a capacitively coupled state.

Therefore, as described above, if the drain voltage of the MOS transistor M1 is different at the time of writing the current and the reading of the current, the charge charged in the data holding capacitor Cs is redistributed between the capacitor Cs and the capacitor Cdg. The holding voltage due to the capacitance Cs is varied. This change in sustain voltage results in an error in the current at the time of writing and the current at the time of reading. For this reason, when reading adjacent current sampling circuits, fluctuations in the drain voltages of the MOS transistors M1 of these current sampling circuits are affected, and the output currents of the respective current sampling circuits are varied.

Therefore, an object of the present invention is to influence the variation of the drain voltage of the current output MOS transistor at the time of writing and reading, the characteristic of the load (organic EL element or TFT), or the variation of the threshold voltage of the current output MOS transistor. In addition, the present invention provides a current sampling circuit that is not affected even when the output current range is wide.

In order to achieve the above object, the present invention provides a current output MOS transistor having a source connected to a power supply line, a voltage buffer having an output connected to a gate of the current output MOS transistor, and an input between the input of the voltage buffer and a power supply line. A first switch provided between the provided data holding capacitor, a drain of the current output MOS transistor and an input of the voltage buffer, a second switch provided between an input terminal and a drain of the current output MOS transistor, an output terminal and the current. And a third switch provided between the drains of the output MOS transistors, and a reference current generating circuit connected to the input terminal Tin, and generated by the reference current generating circuit by turning on the first switch and the second switch. The supplied reference current flows to the current output MOS transistor, and the current output MOS Charge the input voltage of the voltage buffer necessary for the voltage buffer to output the gate voltage flowing the reference current to the transistor in the data holding capacitor Cs, and after the charging, the first switch and the second switch Is turned off and the third switch is turned on to output a current corresponding to the reference current from the drain of the current output MOS transistor.

In a specific embodiment, the first switch to the third switch is composed of a MOS transistor. The voltage buffer is configured by connecting an input PMOS transistor and a current source PMOS transistor in series.

Between the first switch composed of the MOS transistor and the input of the voltage buffer, a fourth switch composed of a MOS transistor having a drain and a source shorted is interposed in series, so that the first switch and the fourth switch are in the reversed form. It may be configured to control on / off.

According to this configuration, the variation of the input voltage of the voltage buffer due to the parasitic capacitance of the first switch and the variation of the input voltage due to the parasitic capacitance of the fourth switch cancel each other out. In order to enhance the effect of the cancellation, the gate width of the MOS transistors constituting the fourth switch is formed to be 1/2 of the gate width of the MOS transistors constituting the first switch SW2.

The current sampling circuit according to the present invention can be provided, for example, as data line driving means for driving a data line of the organic EL light emitting device. The organic EL light emitting device may be either a passive matrix system or an active matrix system.

The reference current generating circuit includes a diode-connected first MOS transistor through which a first constant current flows and a gate voltage of the gate voltage of the first MOS transistor, and generates a current of A times the constant current as the reference current. The second MOS transistor can be configured.

The reference current generating circuit further includes a diode-connected first MOS transistor, through which a first constant current flows, and a gate voltage of the gate voltage of the first MOS transistor, thereby controlling a current of A times the constant current to the reference current. And a second MOS transistor to be generated as a second current, and a current mirror circuit for inputting a second constant current and outputting the first constant current.

1 shows a first embodiment of a current sampling circuit according to the present invention. In FIG. 1, the same reference symbol is attached to the same element as that shown in FIG.

This current sampling circuit has a configuration in which the voltage buffer 1 is added to the current sampling circuit shown in FIG. The voltage buffer 1 has its input connected to the connection point of the switch SW2 and the data holding capacitor Cs, and its output is connected to the gate of the MOS transistor M1.

This current sampling circuit is used as data line driving means for driving data lines of an organic EL light emitting device of a passive matrix type or an active matrix type, for example. However, since this current sampling circuit is for one output terminal, it is actually arranged in the IC chip by the number corresponding to the number of output terminals required for the display panel.

2 is a timing chart of the current sampling circuit according to the first embodiment. As shown in this timing chart, at the time of current writing, the switch SW2 and the switch SW3 are turned on, and the switch SW4 is turned off. Therefore, since the MOS transistor M1 is in a diode-connected state through the voltage buffer 1 and flows the reference current Iref, the drain voltage (= voltage buffer) of the transistor M1 according to the reference current Iref. The input voltage of (1) is charged (stored) in the data holding capacitor Cs via the switch SW2. Thereafter, the switch SW2 is turned OFF, and then the switch SW3 is turned OFF to shift to the hold state.

In the read (output) period, since the switch SW2 and the switch SW3 are turned off and the switch SW4 is turned on, the voltage corresponding to the voltage stored in the data holding capacitor Cs is equal to the voltage buffer 1. Is output from Therefore, the MOS transistor M1 outputs a current Iout determined by the output voltage of the voltage buffer 1. Since the output voltage of the voltage buffer 1 is a voltage determined according to the reference Iref, that is, a storage voltage of the data holding capacitor Cs, the relationship of Iout = Iref holds.

On the other hand, when the switch SW4 is turned OFF after the read period is over, the switch SW1 is turned ON for a predetermined time (not shown in Fig. 5), and the charge accumulated in the data holding capacitor Cs is discharged.

3 shows the state at the time of holding the current sampling circuit according to the first embodiment.

In the current sampling circuit shown in FIG. 16 without the voltage buffer 1, as described above, the gate of the MOS transistor M1 is in an electrically floating state at the time of hold shown in FIG. In contrast, in the current sampling circuit according to the first embodiment, since the voltage buffer 1 drives the gate of the MOS transistor M1 at the time of holding, the gate is the output voltage of the voltage buffer 1, that is, The voltage corresponding to the input voltage of the voltage buffer 1 is fixed. The data storage capacitor Cs and the drain-gate capacitance Cgd of the MOS transistor M1 are separated by this voltage buffer 1.

Therefore, charge redistribution between the capacitors Cs and Cgd due to variations in the drain voltage of the MOS transistor M1 at the time of writing and reading is prevented, so that the variation of the voltage held at the data holding capacitor Cs is prevented. Is prevented. The drain-gate capacitance Cgd is then charged by the voltage buffer 1. As a result, the current sampling circuit according to the first embodiment can prevent variations in the gate potential of the MOS transistor M1 at the time of writing and reading, thereby improving the accuracy of the output current Iout. .

By the way, in the current sampling circuit of this first embodiment, when the transition from the write state to the hold state, the input of the voltage buffer 1 is in an electrically floating state. At this time, the input of the voltage buffer 1 becomes a node with a very high impedance.

As shown in a specific embodiment to be described later, the switch SW2 is composed of a MOS transistor. Since the switch SW2 composed of this MOS transistor has a parasitic capacitance (overlap capacitance) between the gate and the source (or drain), the change in the gate potential due to the parasitic capacitance is a node of the input of the voltage buffer 1. There is a possibility that the input voltage of the voltage buffer 1 is varied by affecting the temperature.

The variation of the input voltage of the voltage buffer causes the output voltage of this voltage buffer 1 to change, i.e., the gate potential of the MOS transistor M1. Variation in the gate potential of the MOS transistor M1 due to the parasitic capacitance of the switch SW2 causes an error in the current during writing and the current during reading.

When the data holding capacity Cs is larger than the parasitic capacitance, it is possible to suppress the error between the current at the time of writing and the current at the time of reading. However, in the case of configuring a current output driving circuit, the capacity value of the capacitor Cs cannot be made very large because the writing period cannot be set so long. Therefore, a countermeasure for suppressing the variation in the gate potential of the MOS transistor M1 due to the parasitic capacitance of the switch SW2 is required without increasing the capacitance Cs.

4 shows a second embodiment of the current sampling circuit according to the present invention in which the above countermeasures are implemented. This current sampling circuit differs from the current sampling circuit shown in FIG. 1 in that a switch SW5 shorted at both ends is inserted between the switch SW2 and the input of the voltage buffer 1.

5 is a timing chart of the current sampling circuit according to the second embodiment. As shown in this timing chart, at the time of current recording, the switch SW2 and the switch SW3 are turned on, and the switch SW4 and the switch SW5 are turned off. Accordingly, since the MOS transistor M1 is in a diode-connected state through the voltage buffer 1 and flows the reference current Iref, the drain voltage (= voltage) of the transistor M1 according to the reference current Iref. The input voltage of the buffer 1) is charged (stored) in the data holding capacitor Cs via SW2. Thereafter, the switch SW2 is turned OFF and the switch SW5 is turned ON, and then the switch SW3 is turned OFF to be in a hold state.

In the current reading (output) period, the switch SW2 and the switch SW3 are kept in an OFF state, and the switch SW4 is turned ON while the switch SW5 is in an ON state. Accordingly, the voltage corresponding to the voltage stored in the data holding capacitor Cs is output from the voltage buffer 1, and as a result, the MOS transistor M1 is determined by the output voltage of the voltage buffer 1 ( Iout).

Since the output voltage of the voltage buffer 1 output in accordance with the voltage stored in the data holding capacitor Cs is a voltage determined in accordance with Iref, the relationship of Iout = Iref holds.

Fig. 6 shows the state at the time of holding the current sampling circuit according to the second embodiment. In the current sampling circuit according to the second embodiment in the hold state, the gate of the MOS transistor M1 is driven by the voltage buffer 1 similarly to the hold time of the current sampling circuit according to the first embodiment. In addition, the capacitors Cs and Cgd are separated by the voltage buffer 1. Therefore, also in this current sampling circuit, the effect of the drain voltage of the MOS transistor M1 fluctuating is eliminated.

As shown in a specific embodiment to be described later, since the switch SW5 is composed of MOS transistors similarly to the switch SW2, the switch SW5 has a parasitic capacitance between the gate and the source (or drain). Thus, in this second embodiment, when the gate voltage of the switch SW2 is turned on / off, the gate voltage of the switch SW5 is turned off / on, that is, the ON / OFF of the gate voltage of the switch SW2 is turned on. The ON / OFF control of these gate voltages is executed so that the ON / OFF of the gate voltage of the switch SW5 is in the reversed form, and the influence caused by the variation of the gate potential of the switch SW2 is canceled out. As a result, the input voltage of the voltage buffer 1 does not change during the transition from the write period to the hold period. As a result, the current Iout can be output with high accuracy without increasing the data holding capacitor Cs. It becomes possible.

(First embodiment)

Fig. 7 shows an example in which the current sampling circuit (Fig. 1) according to the first embodiment is embodied.

In this current sampling circuit, the switch SW1 and the switch SW2 are each composed of PMOS transistors M4 and M5, and the switches SW3 and SW4 are each composed of NMOS transistors M8 and M7. have.

The voltage buffer 1 is comprised by the source-follower circuit which combined PMOS transistors M2 and M3. Since the source-follower circuit needs to have a function capable of completely turning off the MOS transistor M1, a PMOS transistor is used for both the input transistor M3 and the current source transistor M2. Vb is a bias voltage applied to the current source transistor M2.

8 shows a timing chart of the current sampling circuit according to this embodiment. As shown in this timing chart, when the control signal CLCs of the MOS transistor M4 becomes "Lo" in the initial stage of operation, the transistor M4 is turned ON. As a result, since unnecessary charges charged in the data holding capacitor Cs are discharged, the input voltage of the source-follower circuit constituting the voltage buffer 1 becomes the power supply voltage, and the gate voltage of the MOS transistor M1 is also reduced. It becomes the power supply voltage. Therefore, the MOS transistor M10 is completely turned off. When the discharge of the unnecessary charge is completed, since the control signal CLCs of the MOS transistor M4 becomes " Hi ", the transistor M4 is turned off and initialization is completed.

After the initialization is completed, when the control signal Fbcon of the MOS transistor M5 becomes "Lo" and the control signal WE of the MOS transistor M8 becomes "Hi", the MOS transistors M5 and M8. Is turned ON together, the MOS transistor M1 is in a diode-connected state through the source-follower circuit. Accordingly, since the reference current Iref flows through the Tin terminal to the MOS transistor M1, the drain voltage (= input voltage of the source-follower circuit) of the MOS transistor M1 according to the reference current Iref is MOS. The data holding capacitor Cs is charged (stored) through the transistor M5.

When the charge to the data holding capacitor Cs is completed, the control signal Fbcon becomes "Hi" and the MOS transistor M5 is turned off, so that the charge / discharge path to the data holding capacitor Cs is cut off. Data charged (memorized) in the data holding capacity Cs is retained. After that, when the control signal WE becomes "L" and the MOS transistor M5 is turned OFF, the transition to the hold period is performed.

After that, when the control signal OE of the MOS transistor M7 becomes "Hi", since the transistor M7 is turned on, the current Iout corresponding to the voltage stored in the data holding capacitor Cs is It is output from the output terminal Tout. When the output period is completed, the control signal OE becomes "Lo" and the MOS transistor M7 is turned off. For this reason, the current Iout is cut off and the current from the output terminal Tout becomes zero. After that, when the control signal CLCs becomes " Lo " and the MOS transistor M4 is turned ON, the data stored in the data storage capacitor Cs is erased (the charge held in the data storage capacitor Cs is reduced. Discharged) to prepare for the next recording.

(Second embodiment)

Fig. 9 shows an example in which the current sampling circuit (Fig. 4) according to the second embodiment is embodied. In this current sampling circuit, the switches SW1, SW2 and SW5 are each composed of PMOS transistors M4, M5 and M6, and the switches SW3 and SW4 are each NMOS transistors M8. And M7). In addition, the current sampling circuit is provided with an inverter 2 for inverting the control signal Fbcon and applying it to the gate of the PMOS transistor M6.

10 shows a relationship diagram between the PMOS transistors M5 and M6 and the parasitic capacitance Cp. When the write period shown in FIG. 8 is completed, the gate potential of the PM0S transistor M5 constituting the switch SW2 changes from "Lo" to "Hi". At this time, since the gate of the PMOS transistor M5 and the node B (a node having high impedance) are capacitively coupled at the parasitic capacitance (overlap capacitance between the gate and the diffusion region) Cp, the potential of the node B is reduced. Changes with the change in the gate potential of the PMOS transistor M5.

The PMOS transistor M6 is provided as a dummy switch for suppressing fluctuation of the node B. As shown in FIG. Similarly to the PMOS transistor M5, this PMOS transistor M6 has a parasitic capacitance Cp between the node B and the gate, so that the change in the gate potential affects the node B. As shown in FIG.

The gate of the PMOS transistor M6 is ON / OFF controlled in the reverse form of the gate of the PMOS transistor M5 via the inverter 2. Therefore, the write period is completed, the gate potential of the PMOS transistor M5 changes from "Lo" to "Hi", and the gate potential of the PMOS transistor M6 changes from "Hi" to "Lo". At this time, since the PMOS transistor M5 tries to pull up the voltage of the node B, the PMOS transistor M6 tries to pull down the voltage of the node B, so that the potential variation of the node B is reduced. Offset each other.

Here, the parasitic capacitance Cp on the side of the PMOS transistor M5 seen from the node B is 1 × Cpm5. The charge amount Qm5 charged in the parasitic capacitance Cpm5 is assuming that the change width of the gate potential is Vg.

Qm5 = Cpm5 × Vg

It is represented by

On the other hand, the parasitic capacitance Cp on the side of the PMOS transistor M6 seen from the node B is 2 x Cpm6. Therefore, when the charge amount Qm6 charged in the parasitic capacitance Cpm6 is equal to the change width of the gate potential, Vg,

Qm6 = 2 × Cpm6 × Vg

Becomes

In order to completely eliminate the potential variation of the node B, the charge amounts Qm5 and Qm6 must be equal. That is, in order to realize Qm5 = Qm6, the parasitic capacitances Cpm6 and Cpm5 need to satisfy the following relationship.

Cpm6 / Cpm5 = 1/2

Since the parasitic capacitance Cp shown in FIG. 10 is the overlap capacitance of the gate and the diffusion region (the capacitance of the overlapping portion of the gate and the source or the drain), in order to satisfy the relationship of equation (6), the PMOS transistor M5 The gate width Wm5 and the gate width Wm6 of the PMOS transistor M6 may be in the following relationship.

Wm6 / Wm5 = 1/2

Therefore, the gate width Wm6 of the PMOS transistor M6 is formed to be 1/2 of the gate width Wm5 of the PMOS transistor M5.

The voltage buffer 1 is a source-follower circuit composed of PMOS transistors M2 and M3 as in the first embodiment. As described above, since the source-follower circuit needs to have a function of completely turning off the MOS transistor M1, a PMOS transistor is provided to both the input transistor M3 and the current source transistor M2. I use it. Vb is a bias voltage applied to the current source transistor M2.

The timing chart of the current sampling circuit according to the second embodiment is the same as the timing chart of the first embodiment shown in FIG.

According to this second embodiment, since the potential variation of the node B by the PMOS transistor M5 and the potential variation of the node B by the PMOS transistor M6 cancel each other, as a result, the node B The potential fluctuations in a) are prevented.

FIG. 11 shows a third embodiment of the current sampling circuit according to the present invention with a modification of part of the second embodiment, and FIG. 12 shows a timing chart of this embodiment.

This third embodiment differs from the second embodiment in the configuration in which the control signal of the NMOS transistor M8 is inverted by the inverter 3 and the NMOS transistor M7 is controlled by the inverted signal.

According to this third embodiment, the inverter 3 is added, but since the NMOS transistors M7 and M8 can be controlled by one control signal WOE, the control signal line can be reduced by one line.

As shown in Fig. 12, in the current sampling circuit according to the third embodiment, the current Iout is output by setting the control signal Fbcon to "Hi" and then setting the control signal WOE to "Lo". do.

By the way, as is well-known, since organic electroluminescent element has a big internal resistance, in order to flow the electric current required for this organic electroluminescent element, it is necessary to raise the power supply voltage of a display panel. This means that a high breakdown voltage MOS transistor should be used as the MOS transistor M1 constituting the output terminal of the current sampling circuit of each of the above embodiments.

The high breakdown voltage MOS transistor has a tendency for the threshold voltage to be easily changed. The change in the threshold voltage causes luminance unevenness. However, in the current sampling circuits of the above embodiments, since the write current Iref is determined by the reference current generation circuit 4 having the configuration as shown in Fig. 13 connected to the Tin terminal, the MOS transistor M1 The change in the threshold voltage does not affect the write current Iref. The reason for this is as follows.

In the reference current generating circuit 4, the gate voltage is controlled by the diode-connected NMOS transistor M10 through which the constant current Iref 'flows and the gate voltage of the NMOS transistor M10, so that the A of the constant current Iref' is controlled. An NMOS transistor M9 for generating a double current A · Iref 'as the reference current Iref is provided.

The above-mentioned NMOS transistor M9 can be constituted by a normal MOS transistor, that is, a MOS transistor having a small variation in threshold voltage, rather than a high breakdown voltage, for reasons described later.

In addition, the constant current circuit for generating the constant current Iref 'is connected to a power source that outputs a voltage VDD2 having a low voltage compared to the voltage VDD applied to the source of the MOS transistor M1. Since the NMOS transistor M10 is operated by the low voltage VDD2, the NMOS transistor M10 can be constituted by a normal MOS transistor instead of a high breakdown voltage, that is, a MOS transistor having a small variation in threshold voltage.

The reason why the NMOS transistor M9 may not be a high breakdown voltage MOS transistor is that the high breakdown voltage NMOS transistor M8 constituting the switch SW3 is responsible for a high voltage instead of the MMOS transistor M9.

For example, when the power supply voltage VDD of the display panel is 30 V and the gate voltage when the NMOS transistor M8 is on is 3 V (the gate voltage when off is 0 V), the reference flows through the NMOS transistor M9. The current Iref is uniquely determined by the constant current Iref 'flowing through the NMOS transistor M10 (Iref = A · Iref').

On the other hand, in the NMOS transistor M8, the gate-source voltage V _M8SG is adjusted so that the current flowing to itself becomes the reference current Iref. Therefore, the source-drain voltage of the NMOS transistor M9 is 3 VV _M8SG . This indicates that as the NMOS transistor M9, a normal MOS transistor having no high breakdown voltage can be used.

The NMOS transistor M8 operates in the saturation region. Since the current flowing through the NMOS transistor M8 does not depend on the source-drain voltage V _M8SD , the previous V _M8SD is responsible for the high voltage.

In the case where the current sampling circuit of each of the above embodiments having the reference current generating circuit 4 shown in Fig. 13 is applied to an organic EL light emitting device, the generation source (generation circuit) of the constant current Iref 'and the PMOS transistor M10 are There is only one common device for each organic EL display element of the EL light emitting device, and a gate voltage of the PMOS transistor M10 is a gate voltage common to the gate of the PMOS transistor M9 present for each of the EL display elements. Is given. Therefore, each current sampling circuit for each of the EL display elements copies a common constant current Iref 'by a current mirror circuit composed of ordinary MOS transistors M9 and M10 with little variation in threshold voltage, respectively. Generate a constant current (Iref) of.

The reference current generating circuit 4 may be configured as shown in FIG. The reference current generation circuit 4 shown in FIG. 14 copies the constant current Iref0 by a current mirror composed of PMOS transistors M11 and M12, and the constant current Iref in the reference current generation circuit shown in FIG. To generate ').

The MOS transistors M10, M11 and M12 and the constant current circuit which generates the constant current Iref0 are connected between the power supply of the low voltage VDD2 and GND (relative to VDD). Therefore, the MOS transistors M10, M11, and M12 have a low power supply voltage VDD2, and therefore can be constituted by an ordinary MOS transistor, that is, a high MOS transistor, that is, a MOS transistor having a small variation in threshold voltage.

In the case where the current sampling circuit of each of the above embodiments having the reference current generating circuit 4 shown in Fig. 14 is applied to an organic EL light emitting device, the generation source (generation circuit) of the constant current Iref and the PMOS transistor M12 are the EL There is only one common device for each organic EL display element of the light emitting device, and the gate voltage of the PMOS transistor M12 is given as a common gate voltage to the gate of the PMOS transistor M11 that exists for each of the EL display elements. Therefore, each current sampling circuit for each of the EL display elements copies a common constant current Iref0 by a current mirror circuit composed of ordinary MOS transistors M11 and M12 with a small variation in threshold voltages. Generate constant currents Iref 'and Iref.

As described above, since the reference current generating circuits 4 shown in Figs. 13 and 14 can all be constituted by ordinary MOS transistors having a small variation in the threshold voltage, they are not affected by the variation in the threshold voltage. It is possible to generate a reference current Iref that is not a write current. Therefore, according to the current sampling circuits of the above embodiments in which the write current Iref is determined by the reference current generating circuit 4, it is possible to perform appropriate writing regardless of the variation of the threshold voltage of the MOS transistor M1. Do.

According to the current sampling circuit according to the present invention, variations in the drain voltage of the current-output MOS transistors at the time of writing and reading, characteristics of the load (organic EL element or TFT), and threshold voltages of the current-output MOS transistors are attained. It is possible to obtain a high-precision current output which is not affected by the influence, and which is not affected even when the output current range is wide. Therefore, it becomes possible to realize a current output type driving circuit suitable for high gradation organic EL display panels.

In addition, as described above, since it is not affected by fluctuations in the drain voltage of the current output MOS transistor, fluctuations in the load characteristics, or the like, it is possible to reduce the data storage capacity and reduce the layout area.

Claims (9)

A current output MOS transistor M1 having a source connected to the power supply line, A voltage buffer 1 whose output is connected to the gate of the current output MOS transistor M1, A data holding capacitor Cs installed between an input of the voltage buffer and a power line; A first switch SW2 provided between the drain of the current output MOS transistor M1 and the input of the voltage buffer 1; A second switch SW3 provided between an input terminal Tin and a drain of the current output MOS transistor M1; A third switch SW4 provided between the output terminal Tout and the drain of the current output MOS transistor M1; And a reference current generating circuit 4 connected to the input terminal Tin, By turning on the first switch SW2 and the second switch SW3, the reference current Iref generated by the reference current generating circuit 4 flows to the current output MOS transistor M1, and the current The data holding capacitor Cs charges the input voltage of the voltage buffer 1 required for the voltage buffer 1 to output the gate voltage flowing the reference current Iref to the output MOS transistor M1. , After the charging, the first switch SW2 and the second switch SW3 are turned off and the third switch SW4 is turned on, so that the reference current Iref from the drain of the current output MOS transistor M1 is turned off. And a current corresponding to the current output circuit. The current sampling circuit according to claim 1, wherein the first switch (SW2), the second switch (SW3), and the third switch (SW4) are composed of MOS transistors. The current sampling circuit according to claim 1, wherein the voltage buffer (1) has a configuration in which an input PMOS transistor (M3) and a current source PMOS transistor (M2) are connected in series. 4. The fourth switch SW5 according to claim 2, wherein the drain and the source are short-circuited between the first switch SW2 made of the MOS transistor and the input of the voltage buffer 1, and the fourth switch SW5 made of the MOS transistor M6. Interposed in series and configured to control on / off of the first switch (SW2) and the fourth switch (SW5) in a reverse form. The gate width of the MOS transistor M6 constituting the fourth switch SW5 is half the width of the gate width of the MOS transistor M5 constituting the first switch SW2. A current sampling circuit, characterized in that formed. The current sampling circuit according to any one of claims 1 to 5, wherein the current sampling circuit is provided as data line driving means for driving a data line of the organic EL light emitting device. 7. The current sampling circuit according to claim 6, wherein the organic EL light emitting device is a passive matrix type or an active matrix type light emitting device. The method of claim 2, wherein the reference current generating circuit 4, A diode-connected first MOS transistor M10 through which the first constant current Iref 'flows, A second gate voltage is controlled by the gate voltage of the first MOS transistor M10 to generate a current A · Iref 'that is A times the first constant current Iref' as the reference current Iref. A current sampling circuit comprising a MOS transistor M9. The method of claim 2, wherein the reference current generating circuit 4, A diode-connected first MOS transistor M10 through which the first constant current Iref 'flows, A second gate voltage is controlled by the gate voltage of the first MOS transistor M10 to generate a current A · Iref 'that is A times the first constant current Iref' as the reference current Iref. MOS transistor M9, And a current mirror circuit for inputting a second constant current (Iref0) to output the first constant current (Iref ').

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