KR20060024605A - Method of forming contact hole for semiconductor device - Google Patents
Method of forming contact hole for semiconductor device Download PDFInfo
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- KR20060024605A KR20060024605A KR1020040073409A KR20040073409A KR20060024605A KR 20060024605 A KR20060024605 A KR 20060024605A KR 1020040073409 A KR1020040073409 A KR 1020040073409A KR 20040073409 A KR20040073409 A KR 20040073409A KR 20060024605 A KR20060024605 A KR 20060024605A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000000034 method Methods 0.000 title claims description 19
- 150000004767 nitrides Chemical class 0.000 claims abstract description 49
- 230000001681 protective effect Effects 0.000 claims abstract description 30
- 239000000463 material Substances 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 238000005530 etching Methods 0.000 claims abstract description 17
- 239000011229 interlayer Substances 0.000 claims abstract description 11
- 230000004888 barrier function Effects 0.000 claims abstract description 8
- 239000010410 layer Substances 0.000 claims description 14
- 238000001020 plasma etching Methods 0.000 claims description 7
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 4
- 239000011800 void material Substances 0.000 abstract description 6
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 239000012535 impurity Substances 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000035515 penetration Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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Abstract
본 발명의 목적은 콘택홀 형성 시 보이드의 노출을 차단하여 게이트 사이의 브리지 및 단락을 방지하는 것이다.It is an object of the present invention to block the exposure of voids during contact hole formation to prevent bridges and short circuits between gates.
본 발명의 목적은 게이트 및 소오스/드레인 접합영역이 구비된 트랜지스터가 형성된 반도체 기판을 준비하는 단계; 기판 전면 상에 질화막을 형성하는 단계; 질화막 상에 평탄화된 산화막을 형성하는 단계; 질화막을 식각 배리어로하여 산화막을 식각하여 게이트 사이의 질화막을 노출시키는 콘택홀을 형성하는 단계; 콘택홀 저부 및 측부와 층간절연막 상에 질화막의 보호 물질막을 형성하는 단계; 및 층간절연막 상의 보호 물질막과 콘택홀 저부의 질화막 및 보호물질막을 식각하여 콘택홀 측부에 보호막을 형성함과 동시에 콘택홀 저부의 기판을 노출시키는 단계를 포함하는 반도체 소자의 콘택홀 형성방법에 의해 달성될 수 있다.An object of the present invention is to prepare a semiconductor substrate having a transistor having a gate and a source / drain junction region; Forming a nitride film on the entire surface of the substrate; Forming a planarized oxide film on the nitride film; Etching the oxide film using the nitride film as an etch barrier to form a contact hole exposing the nitride film between the gates; Forming a protective material film of a nitride film on the bottom and side of the contact hole and the interlayer insulating film; And etching the protective material film on the interlayer insulating film, the nitride film on the bottom of the contact hole and the protective material film to form a protective film on the contact hole side, and simultaneously exposing the substrate on the bottom of the contact hole. Can be achieved.
콘택홀, 보이드, PMD, 보호막, 질화막, 산화막Contact hole, void, PMD, protective film, nitride film, oxide film
Description
도 1 내지 도 3은 종래 반도체 소자의 PMD막에서 보이드가 발생된 경우를 나타낸 도면.1 to 3 are views illustrating a case where voids are generated in a PMD film of a conventional semiconductor device.
도 4는 종래 반도체 소자의 PMD막에서 발생된 보이드에 플러그 물질이 침투한 경우를 나타낸 도면.4 is a view illustrating a case in which a plug material penetrates into a void generated in a PMD film of a conventional semiconductor device.
도 5a 내지 도 5f는 본 발명의 실시예에 따른 반도체 소자의 콘택홀 형성방법을 설명하기 위한 순차적 공정 단면도.5A through 5F are sequential process cross-sectional views illustrating a method for forming a contact hole in a semiconductor device according to an embodiment of the present invention.
본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 반도체 소자의 콘택홀 형성방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming contact holes in a semiconductor device.
일반적으로, 트랜지스터와 트랜지스터 사이, 트랜지스터와 배선 사이 및 배선과 배선 사이는 층간절연막에 의해 서로 절연되며, 층간절연막에 콘택홀을 형성하고 콘택홀에 금속 등의 도전물질을 채워 배선을 형성하는 것에 의해 전기적으로 서로 연결된다.In general, between transistors and transistors, between transistors and wirings, and between wirings and wirings, they are insulated from each other by an interlayer insulating film, by forming contact holes in the interlayer insulating film and forming wirings by filling conductive materials such as metal in the contact holes. Are electrically connected to each other.
이 중 트랜지스터와 배선 사이를 절연하는 층간절연막, 이른 바 전금속절연(Pre Metal Dielectric; PMD)막은, 플라즈마강화-화학기상증착(Plasma Enhanced -Chemical Vapor Deposition; PECVD)에 의해 트랜지스터를 덮도록 질화막을 증착하고, 고밀도 플라즈마(High Density Plasm; HDP) 산화막, PSG막, BSPG막 등의 산화막을 증착한 후, 산화막의 특성에 따라 적정 온도에서 열처리를 수행한 다음, 화학기계연마(Chemical Mechanical Polishing; CMP)에 의해 평탄화하는 과정으로 형성한다.Among these, an interlayer insulating film that insulates between the transistor and the wiring, a so-called Pre Metal Dielectric (PMD) film, includes a nitride film so as to cover the transistor by Plasma Enhanced-Chemical Vapor Deposition (PECVD). After depositing, depositing an oxide film such as a high density plasma (HDP) oxide film, a PSG film, a BSPG film, and the like, and performing heat treatment at an appropriate temperature according to the characteristics of the oxide film, followed by chemical mechanical polishing (CMP). It is formed by the process of planarization by the
또한, 산화막이 PSG막 또는 BPSG막인 경우에는 평탄화 후 불순물의 확산을 방지하도록 상부에 캡핑층(capping layer)을 추가로 형성한다.In addition, when the oxide film is a PSG film or a BPSG film, a capping layer is further formed on the top to prevent diffusion of impurities after planarization.
그런데, 반도체 소자의 고집적화가 가속화되면서 트랜지스터의 게이트 사이의 간격이 점점 좁아져 간격의 어스펙트비(aspect ratio)가 증가함에 따라, PMD막의 형성 시 충분한 공간 마진(space margin)을 확보하기가 어려워 게이트 사이의 간격이 PMD막에 의해 완전히 매립되지 못하고 보이드(void)가 발생한다(도 1 내지 도 3의 "A", "B", "C" 참조).However, as the integration of semiconductor devices is accelerated, the gap between gates of transistors becomes narrower and the aspect ratio of the gap increases, so that it is difficult to secure sufficient space margin when forming a PMD film. The gap between them is not completely filled by the PMD film and voids are generated (see "A", "B", and "C" in Figs. 1 to 3).
이러한 보이드는 후속 콘택홀 형성 시 노출되어 도 4의 "D"와 같이 텅스텐과 같은 금속 또는 폴리실리콘 등의 플러그 물질의 침투를 유발하여 심한 경우 게이트 사이의 브리지(bridge) 및 단락(short)을 야기시켜 누설전류를 발생함으로써, 결국 소자의 수율 및 신뢰성을 저하시킨다.These voids are exposed during subsequent contact hole formation, causing penetration of a plug material, such as polysilicon or a metal such as tungsten, as shown in " D " of FIG. 4, which, in severe cases, results in bridges and shorts between the gates. By generating a leakage current, the yield and reliability of the device are eventually reduced.
본 발명은 상기와 같은 종래의 문제점을 해결하기 위한 것으로, 콘택홀 형성 시 보이드의 노출을 차단하여 게이트 사이의 브리지 및 단락을 방지하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the conventional problems as described above, and has an object of preventing bridges and short circuits between gates by blocking the exposure of voids when forming contact holes.
상기한 바와 같은 본 발명의 목적은 게이트 및 소오스/드레인 접합영역이 구비된 트랜지스터가 형성된 반도체 기판을 준비하는 단계; 기판 전면 상에 질화막을 형성하는 단계; 질화막 상에 평탄화된 산화막을 형성하는 단계; 질화막을 식각 배리어로하여 산화막을 식각하여 게이트 사이의 질화막을 노출시키는 콘택홀을 형성하는 단계; 콘택홀 저부 및 측부와 층간절연막 상에 질화막의 보호 물질막을 형성하는 단계; 및 층간절연막 상의 보호 물질막과 콘택홀 저부의 질화막 및 보호물질막을 식각하여 콘택홀 측부에 보호막을 형성함과 동시에 콘택홀 저부의 기판을 노출시키는 단계를 포함하는 반도체 소자의 콘택홀 형성방법에 의해 달성될 수 있다.An object of the present invention as described above is to prepare a semiconductor substrate having a transistor provided with a gate and a source / drain junction region; Forming a nitride film on the entire surface of the substrate; Forming a planarized oxide film on the nitride film; Etching the oxide film using the nitride film as an etch barrier to form a contact hole exposing the nitride film between the gates; Forming a protective material film of a nitride film on the bottom and side of the contact hole and the interlayer insulating film; And etching the protective material film on the interlayer insulating film, the nitride film on the bottom of the contact hole and the protective material film to form a protective film on the contact hole side, and simultaneously exposing the substrate on the bottom of the contact hole. Can be achieved.
또한, 본 발명의 목적은 게이트 및 소오스/드레인 접합영역이 구비된 트랜지스터가 형성된 반도체 기판을 준비하는 단계; 기판 전면 상에 질화막을 형성하는 단계; 질화막 상에 평탄화된 산화막을 형성하는 단계; 질화막을 식각 배리어로하여 산화막을 식각하여 게이트 사이의 질화막을 노출시키는 콘택홀을 형성하는 단계; 콘택홀 저부 및 측부와 층간절연막 상에 산화막의 보호 물질막을 형성하는 단계; 질화막이 노출될 때까지 보호 물질막을 에치백하여 콘택홀 측부에 보호막을 형성하는 단계; 및 콘택홀 저부의 질화막을 식각하여 기판을 노출시키는 단계를 포함하는 반도체 소자의 콘택홀 형성방법에 의해 달성될 수 있다.In addition, an object of the present invention is to prepare a semiconductor substrate on which a transistor having a gate and a source / drain junction region is formed; Forming a nitride film on the entire surface of the substrate; Forming a planarized oxide film on the nitride film; Etching the oxide film using the nitride film as an etch barrier to form a contact hole exposing the nitride film between the gates; Forming a protective material film of an oxide film on the bottom and side of the contact hole and the interlayer insulating film; Etching back the protective material film until the nitride film is exposed to form a protective film on the contact hole side; And etching the nitride film at the bottom of the contact hole to expose the substrate.
여기서, 평탄화된 산화막은 HDP 산화막, PSG막, BPSG막 중 선택되는 어느 하 나로 이루어진다.Here, the planarized oxide film is made of any one selected from an HDP oxide film, a PSG film, and a BPSG film.
또한, 보호 물질막은 50 내지 1000Å의 두께로 형성한다.Further, the protective material film is formed to a thickness of 50 to 1000 mm 3.
또한, 기판을 노출시키는 단계에서 식각은 반응성이온식각(RIE)으로 수행한다.In addition, the etching is performed by reactive ion etching (RIE) in the step of exposing the substrate.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예를 설명한다.Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.
도 5a 내지 도 5f를 참조하여 본 발명의 실시예에 따른 반도체 소자의 콘택홀 형성방법을 설명한다.A method of forming a contact hole in a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 5A to 5F.
도 5a를 참조하면, 반도체 기판(10) 상에 게이트 절연막(11)을 형성하고, 게이트 절연막(11) 상에 게이트 물질막을 증착한다. 여기서, 게이트 물질막은 폴리실리콘막, 폴리실리콘막/금속막 또는 폴리실리콘막/금속실리사이드막으로 이루어질 수 있다. Referring to FIG. 5A, a gate
그 다음, 게이트 물질막 상부에 포토리소그라피 공정에 의해 제 1 포토레지스트 패턴(미도시)을 형성하고, 제 1 포토레지스트 패턴을 마스크로하여 게이트 물질막을 식각하여 게이트(12)를 형성한다.Next, a first photoresist pattern (not shown) is formed on the gate material layer by a photolithography process, and the gate material layer is etched using the first photoresist pattern as a mask to form the
그 후, 공지된 방법에 의해 제 1 포토레지스트 패턴을 제거하고, 게이트(12) 양측의 기판(10)으로 저농도 불순물 이온을 주입하여 엘디디(Lightly Doped Drain; LDD) 영역(미도시)을 형성한다. Thereafter, the first photoresist pattern is removed by a known method, and low concentration impurity ions are implanted into the
그 다음, 게이트(12)를 덮도록 기판 전면 상에 스페이서 물질로서 질화막 등의 절연막을 증착하고 기판(10) 표면이 노출되도록 절연막을 에치백(etch-back)하여 게이트(12) 양 측벽에 스페이서(13)를 형성한다. Next, an insulating film, such as a nitride film, is deposited on the entire surface of the substrate to cover the
그 후, 스페이서(13) 양측의 기판(10)으로 고농도 불순물 이온을 주입하여 소오스/드레인 접합영역(미도시)을 형성하여 트랜지스터를 완성한다.Thereafter, a high concentration of impurity ions are implanted into the
도 5b를 참조하면, 게이트(12) 및 스페이서(13)를 덮도록 PECVD에 의해 기판 전면 상에 제 1 질화막(12)을 증착한다. 여기서, 제 1 질화막(12)은 이후 산화막의 식각 시 식각 배리어(barrier)로서 작용한다.Referring to FIG. 5B, the
도 5c를 참조하면, 제 1 질화막(12)이 형성된 게이트(12) 사이의 공간을 매립하도록 제 1 질화막(12) 상에 산화막(15)을 증착한다. 여기서, 산화막(15)은 HDP 산화막, PSG막, BSPG막 중 선택되는 어느 하나로 이루어진다. Referring to FIG. 5C, an
이때, 도시되지는 않았지만, 게이트(12) 사이의 좁은 간격으로 인해 산화막(15)에 보이드가 발생될 수 있다.At this time, although not shown, voids may be generated in the
그 다음, 산화막(15)의 특성에 따라 적정 온도에서 열처리를 수행하고, CMP에 의해 산화막(15)을 평탄화하여, 제 1 질화막(12)과 산화막(15)으로 이루어진 PMD막을 형성한다. 여기서, 산화막(15)이 PSG막 또는 BPSG막인 경우에는 평탄화 후 불순물의 확산을 방지하도록 상부에 캡핑층을 추가로 형성한다.Then, heat treatment is performed at an appropriate temperature according to the characteristics of the
도 5d를 참조하면, 포토리소그라피에 의해 산화막(15) 상부에 게이트(12) 사이의 산화막(15)을 일부 노출시키는 제 2 포토레지스트 패턴(미도시)을 형성하고, 제 2 포토레지스트 패턴을 식각 마스크로 이용하고 제 1 질화막(14)을 식각 배리어로 하여 노출된 산화막(15)을 식각하여 콘택홀(16)을 형성한다. Referring to FIG. 5D, a second photoresist pattern (not shown) for partially exposing the
이때, 도시되지는 않았지만, 콘택홀(16)의 측부로 보이드가 노출될 수 있다. 그 후, 공지된 방법에 의해 포토레지스트 패턴을 제거한다.At this time, although not shown, the void may be exposed to the side of the
도 5e를 참조하면, 콘택홀(16) 저부의 제 1 질화막(14)과 콘택홀(16) 측부 및 산화막(15) 상에 보호 물질막으로 50 내지 1000Å의 두께의 제 2 질화막(17)을 증착한다. Referring to FIG. 5E, a
도 5f를 참조하면, 반응성이온식각(Reactive Ion Etching; RIE)에 의해 산화막(15) 상부의 제 2 질화막(17)과 콘택홀(16) 저부의 제 1 및 제 2 질화막(14, 17)을 식각하여, 콘택홀(16) 측부에 제 2 질화막(17)으로 이루어진 보호막(17a)을 형성함과 동시에 콘택홀(16) 저부의 기판(10)을 완전히 노출시킨다.Referring to FIG. 5F, the
여기서, 보호막(17a)은 콘택홀(16) 측부에서의 보이드 노출을 차단하여 후속 콘택홀(16)에 텅스텐과 같은 금속 또는 폴리실리콘 등의 플러그 물질 증착하는 경우 플러그 물질이 보이드로 침투하는 것을 방지함으로써, 게이트(12) 사이의 브리지 및 단락을 방지한다.Here, the
상기 실시예에서는 보호막(17a)의 물질로 질화막을 이용하였지만 질화막 대신 산화막을 적용할 수도 있는데, 이 경우에는 제 1 질화막(14)이 노출될 때까지 산화막을 에치백하여 콘택홀(16) 측벽에 산화막으로 이루어진 보호막(17a)을 형성한 후, RIE에 의해 제 1 질화막(14)을 식각하여 콘택홀(16) 저부의 기판(10)을 완전히 노출시킨다.In the above embodiment, the nitride film is used as the material of the
또한, 상기 실시예에서는 단일층의 PMD막에 대해서만 설명하였지만, 디램(DRAM)에서와 같은 다층의 PMD막의 경우에도 적용이 가능하다.In the above embodiment, only a single layer of PMD film has been described. However, the present invention can also be applied to a multilayer PMD film such as DRAM.
상술한 바와 같이, 본 발명은 콘택홀 측부에 보호막을 형성하여 콘택홀 측부 로의 보이드 노출을 차단하여 후속 보이드로의 플러그 물질 침투를 방지함으로써, 게이트 사이의 브리지 및 단락을 효과적으로 방지할 수 있으므로 누설전류 발생을 억제할 수 있다.As described above, the present invention forms a protective film on the contact hole side to block the void exposure to the contact hole side to prevent plug material penetration into subsequent voids, thereby effectively preventing bridges and short circuits between the gates and thus leakage current. It can suppress occurrence.
그 결과, 본 발명은 소자의 수율 및 신뢰성을 개선할 수 있다.As a result, the present invention can improve the yield and reliability of the device.
또한, 본 발명은 보호막의 물질로 질화막을 이용하여 식각 배리어로 작용하는 질화막의 식각 시 동시에 식각하므로 비교적 단순한 공정으로 보호막을 형성할 수 있다.In addition, since the present invention simultaneously etches the nitride film acting as an etch barrier using the nitride film as a material of the protective film, the protective film can be formed by a relatively simple process.
이상에서 설명한 본 발명은 전술한 실시예 및 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be apparent to those who have knowledge.
Claims (7)
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| KR1020040073409A KR20060024605A (en) | 2004-09-14 | 2004-09-14 | Method of forming contact hole for semiconductor device |
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| KR1020040073409A KR20060024605A (en) | 2004-09-14 | 2004-09-14 | Method of forming contact hole for semiconductor device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100647468B1 (en) * | 2005-11-04 | 2006-11-23 | 삼성전자주식회사 | Metal wiring structure in semiconductor device and method for forming the same |
| US7732323B2 (en) * | 2007-10-23 | 2010-06-08 | Samsung Electronics Co., Ltd. | Methods of manufacturing semiconductor devices having contact plugs in insulation layers |
-
2004
- 2004-09-14 KR KR1020040073409A patent/KR20060024605A/en not_active Application Discontinuation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100647468B1 (en) * | 2005-11-04 | 2006-11-23 | 삼성전자주식회사 | Metal wiring structure in semiconductor device and method for forming the same |
| US7732323B2 (en) * | 2007-10-23 | 2010-06-08 | Samsung Electronics Co., Ltd. | Methods of manufacturing semiconductor devices having contact plugs in insulation layers |
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