KR100850088B1 - Method for manufacturing a semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, comprising: forming a device isolation film recessed to expose a top surface of a trench by an STI method in a device isolation region of a semiconductor substrate; and forming a gate insulating film on an active region of the semiconductor substrate. Forming a gate through the interposed layer; forming first and second spacers on the gate side and the exposed side surface of the trench; and forming impurities of a conductivity type different from that of the semiconductor substrate in the active region of the semiconductor substrate. Forming an impurity region by doping, forming an interlayer insulating layer on the semiconductor substrate and the interlayer insulating layer, exposing the impurity region, and forming a contact hole; and forming a plug in the contact hole. do. Therefore, even if misalignment occurs during contact hole formation, contact spiking can be prevented and the contact resistance and device characteristics of the plug can be prevented from being lowered.

STI, Contact Hole, Misalignment, Spacer, Contact Spike

Description

METHODS FOR MANUFACTURING A SEMICONDUCTOR DEVICE

1A to 1C are process drawings showing a method of manufacturing a semiconductor device according to the prior art.

2A to 2D are process diagrams showing the manufacturing method of the semiconductor device according to the first embodiment of the present invention.

3A to 3D are process drawings showing the manufacturing method of the semiconductor device according to the second embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

31 semiconductor substrate 32 trench

33: device isolation layer 35: gate insulating film

37: gate 39: first spacer

40: second spacer 41: impurity region

43: interlayer insulating layer 45: contact hole

47: plug 49: metal wiring

51 nitride layer 53 photoresist pattern

55 spacer 57 etch stop film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device which prevents the plug from invading a shallow trench isolation (STI) insulating film due to misalignment of contact holes for bit line contacts. will be.

First, referring to FIGS. 1A to 1C, a process diagram illustrating a method of manufacturing a semiconductor device according to the prior art is shown.

Referring to FIG. 1A, a trench 12 is formed in an isolation region of a semiconductor substrate 11, and the isolation layer 13 is formed by filling the trench 12 with silicon oxide to define an active region.

The gate 17 is formed on the active region of the semiconductor substrate 11 with the gate insulating film 15 interposed therebetween, and a spacer 19 is formed on the side surface of the gate 17. The impurity region 21 used as the source and drain regions is formed by doping the semiconductor substrate 11 with an impurity of a different conductivity type from the semiconductor substrate 11.

Referring to FIG. 1B, the silicon oxide is deposited on the semiconductor substrate 11 to form an interlayer insulating layer 23, and then the impurity region 21 is exposed by photolithography to form the contact hole 25.

Referring to FIG. 1C, a metal such as tungsten is deposited on the interlayer insulating layer 23 to fill the contact hole 25. In addition, the plug 27 may be electrically connected to the impurity region 21 in the contact hole 25 by polishing the metal such as tungsten to expose the interlayer insulating layer 23 by a chemical mechanical polishing (CMP) method. ).

Then, a conductive metal such as aluminum is deposited on the interlayer insulating layer 23 and patterned to be in contact with the plug 27 by a photolithography method to form a metal wiring 29 used as a bit line.

The semiconductor device manufacturing method according to the related art described above may be misaligned during the mask process, and the device isolation layer may be exposed by the contact hole. In this case, an edge portion of the device isolation layer is etched. In this case, the etching rate of the device isolation layer is rapidly etched along the interface of the semiconductor substrate.

Accordingly, when forming a plug in the contact hole, contact spiking occurs in which metal such as tungsten, which forms the plug, diffuses along the interface between the device isolation film and the semiconductor substrate.

Therefore, in the prior art, contact spiking has a problem of lowering the contact resistance and device characteristics of the plug.

Accordingly, it is an object of the present invention to provide a method for manufacturing a semiconductor device which can prevent contact spikes even when misalignment occurs in forming contact holes, thereby preventing the contact resistance and device characteristics of the plug from being lowered.

The semiconductor device manufacturing method according to the first embodiment of the present invention for achieving the above object is a step of forming a device isolation film recessed to expose the upper side of the trench by the STI method in the device isolation region of the semiconductor substrate; Forming a gate through a gate insulating layer on an active region of the semiconductor substrate, forming first and second spacers on the gate side and the exposed side of the trench, respectively, and in the active region of the semiconductor substrate; Forming an impurity region by doping an impurity of a different conductivity type from the semiconductor substrate, forming an interlayer dielectric layer on the semiconductor substrate and the interlayer dielectric layer, and exposing the impurity region to form contact holes; Forming a plug in the contact hole.

A semiconductor device manufacturing method according to a second embodiment of the present invention for achieving the above object is a step of forming a device isolation film in the device isolation region of the semiconductor substrate by the STI method, and a gate insulating film on the active region of the semiconductor substrate Forming a gate through the semiconductor substrate, forming a nitride film on the semiconductor substrate to cover the gate and the device isolation film, and forming a photoresist pattern on the nitride film to cover a portion corresponding to the device isolation film; Forming an etch inhibitor layer on the device isolation layer by etching back to form a spacer on the side of the gate; removing the photoresist pattern; and doping impurities of a conductive type different from that of the semiconductor substrate to an active region of the semiconductor substrate. Forming an impurity region to form an impurity region on the semiconductor substrate and the Forming an interlayer insulating layer and a step of forming a step of forming a contact hole to expose the impurity region, a plug in the contact hole.

Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail as follows with reference to the accompanying drawings.

2A to 2D, a process diagram illustrating a method of manufacturing a semiconductor device according to the first embodiment of the present invention is shown.

First, as shown in FIG. 2A, the device isolation film 33 defining the active region is formed in the device isolation region of the semiconductor substrate 31 using the STI method. More specifically, a pad oxide film (not shown) and a pad nitride film (not shown) are deposited on the semiconductor substrate 31, and a photoresist (not shown) is applied to the pad nitride film by exposure and development. The part corresponding to the device isolation region is exposed. After sequentially patterning the pad nitride film and the pad oxide film using a photoresist as a mask, the semiconductor substrate 31 is subsequently etched by an anisotropic etching method such as reactive ion etching (RIE) to the active region of the semiconductor substrate 31. The trench 32 is formed. Subsequently, the isolation layer 33 is deposited in the trench 32 by depositing the inside of the trench 32 with an insulating material such as silicon oxide on the pad nitride film, and then using chemical mechanical polishing (CMP). Form. In this case, the device isolation layer 33 is formed by recess etching to expose the upper side surface of the trench 32.

Thereafter, as shown in FIG. 2B, the gate 37 is formed on the active region of the semiconductor substrate 31 through the gate insulating film 35.

An insulating material having a different etching selectivity from the device isolation layer 33 and an etching selectivity, for example, silicon nitride, is deposited on the semiconductor substrate 31 so as to cover the gate 37 and the device isolation layer 33. The first spacer 39 is formed on the side of the gate 37 by etching back. In addition, a second spacer 40 is also formed on the side surface of the trench 32 on the device isolation layer 33.

Then, an impurity region 41 used as a source and a drain region is formed by doping the semiconductor substrate 31 with an impurity of a different conductivity type from the active region of the semiconductor substrate 31.

Next, as shown in FIG. 2C, the silicon oxide is deposited on the semiconductor substrate 31 to form the interlayer insulating layer 43, and then the impurity region 41 is exposed by photolithography to expose the contact hole 45. To form. In the first embodiment of the present invention, the silicon nitride forming the second spacer 40 has an etching selectivity different from that of the silicon oxide forming the interlayer insulating layer 43. Thus, even when misalignment occurs when the interlayer insulating layer 43 is etched to form the contact hole 45, the device isolation layer 33 may be prevented from being etched by the second spacer 40.

Referring to FIG. 2D, a metal material such as tungsten is deposited on the interlayer insulating layer 43 to fill the contact hole 45. In this case, since the device isolation layer 33 is not exposed or etched, contact spikes in which a metal such as tungsten is diffused along the interface between the semiconductor substrate 31 and the device isolation layer 33 may be prevented.

The plug 47 may be electrically connected to the impurity region 41 in the contact hole 45 by polishing the metal material such as tungsten to expose the interlayer insulating layer 43 by a chemical mechanical polishing (CMP) method. ).

Then, a conductive metal such as aluminum is deposited on the interlayer insulating layer 43 and patterned to be in contact with the plug 47 by a photolithography method to form a metal wiring 49 used as a bit line.

3A to 3B are process diagrams showing the manufacturing method of the semiconductor device according to the second embodiment of the present invention.

Referring to FIG. 3A, an isolation layer 33 is formed in the isolation region of the semiconductor substrate 31 to fill the trench 32 by the STI method, and the gate is formed on the active region of the semiconductor substrate 31. The gate 37 is formed through the insulating film 35.

An insulating material having a different etching selectivity from the device isolation layer 33 and an etching selectivity, for example, silicon nitride, is deposited on the semiconductor substrate 32 so as to cover the gate 37 and the device isolation layer 33 to form the nitride film 51. . Then, a photoresist is applied on the nitride film 51, and the photoresist pattern 53 is formed in a portion corresponding to the device isolation film 33 by exposure and development.

Thereafter, as illustrated in FIG. 3B, the nitride layer 51 is etched back by using a reactive ion etching (RIE) method to form a spacer 55 on the side of the gate 37. In this case, the nitride film 51 is also left on the isolation layer 33 by the photoresist pattern 53 to form an etch stop layer 57.

After the photoresist pattern 53 is removed, an impurity region 41 used as a source and a drain region is formed by doping the semiconductor substrate 31 with an impurity of a different conductivity type from the active region of the semiconductor substrate 31.

The process proceeding in FIGS. 3C and 3D is then the same as in FIGS. 2C and 2D of the first embodiment described above. In other words, as illustrated in FIG. 3C, the silicon oxide is deposited on the semiconductor substrate 31 to form the interlayer insulating layer 43, and then the impurity region 41 is exposed by photolithography to expose the contact hole ( 45). As in the first embodiment described above, in the second embodiment, the silicon nitride forming the etch stop film 57 is different in etching selectivity from the silicon oxide forming the interlayer insulating layer 43. Thus, even when misalignment occurs when the interlayer insulating layer 43 is etched to form the contact hole 45, the device isolation layer 33 may be prevented from being etched by the etch stop layer 57.

Next, as shown in FIG. 3D, a metal material such as tungsten is deposited on the interlayer insulating layer 43 to fill the contact hole 45. In this case, since the device isolation layer 33 is not exposed or etched, contact spikes in which a metal such as tungsten is diffused along the interface between the semiconductor substrate 31 and the device isolation layer 33 may be prevented.

The plug 47 may be electrically connected to the impurity region 41 in the contact hole 45 by polishing the metal material such as tungsten to expose the interlayer insulating layer 43 by a chemical mechanical polishing (CMP) method. ).

Then, a conductive metal such as aluminum is deposited on the interlayer insulating layer 43 and patterned to be in contact with the plug 47 by a photolithography method to form a metal wiring 49 used as a bit line.

As described above, when the first isolation layer is formed on the side of the gate by recess etching the device isolation layer to expose the upper side of the trench, the second spacer is formed on the upper side of the exposed trench. As a result, even if misalignment occurs during contact hole formation in the interlayer insulating layer, contact spiking that reduces contact resistance and device characteristics during plug formation can be prevented.

Therefore, the present invention has an advantage of preventing contact spiking even when misalignment occurs in forming a contact hole, thereby preventing the contact resistance and device characteristics of the plug from being lowered.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

Claims (6)

delete delete delete Forming an isolation film in the isolation region of the semiconductor substrate by an STI method; Forming a gate through a gate insulating film on an active region of the semiconductor substrate; Forming a nitride film on the semiconductor substrate to cover the gate and the device isolation film, and forming a photoresist pattern covering a portion corresponding to the device isolation film on the nitride film; Etching back the nitride film to form a spacer on the side of the gate and forming an etch inhibiting layer on the isolation layer; Removing the photoresist pattern and doping an active region of the semiconductor substrate with an impurity of a different conductivity type than the semiconductor substrate to form an impurity region; Forming an interlayer insulating layer on the semiconductor substrate and exposing the impurity region to form contact holes; And forming a plug in the contact hole. delete The method according to claim 4, And depositing a conductive metal on the interlayer insulating layer and patterning the conductive metal in contact with the plug to form a metal wiring used as a bit line.

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