KR100349360B1 - Method of forming contacts in semiconductor devices - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact in a semiconductor device. In particular, a gate capping insulation layer and a sidewall spacer insulation layer are formed of a material having a high etching selectivity to form a self-aligned contact portion when forming a bit line and a storage node plug contact hole. By preventing excessive etching of the gate cap insulating film, the possibility of short-circuit of the gate and the plug is eliminated, and an opening for exposing the contact hole for exposing the gate of the core / ferry part and the bit line plug for the cell part is simultaneously formed in a self-aligning manner. A method of forming a self-aligned contact portion of a semiconductor device that simplifies the process, reduces the chip size, and increases the process margin without additional equipment. The method includes a second insulating film formed on a semiconductor substrate having defined device active regions and isolation regions. A cap insulating film, a gate made of a first conductive layer, and a first insulating film Forming a gate pattern formed of a gate insulating film, forming a low concentration impurity diffusion region in the active region below the sidewall of the gate pattern, and etching the second insulating layer on the semiconductor substrate including the gate pattern Forming a third insulating film having a high selectivity to a predetermined thickness, forming a high concentration impurity diffusion region in an active region of the semiconductor substrate using the third insulating film, and forming a first interlayer insulating layer on the third insulating film Forming a contact hole exposing the third insulating film on the impurity diffusion region by removing a predetermined portion of the first interlayer insulating layer, and removing the exposed third insulating film of the contact hole. Exposing a portion of the impurity diffusion region to contact the exposed impurity diffusion region. Forming a conductive plug in the tack hole, forming a second interlayer insulating layer on the first interlayer insulating layer to cover the plug, and removing a predetermined portion of the second interlayer insulating layer to remove the surface of the plug. Exposing.

Description

Method of forming contacts in semiconductor devices

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact in a semiconductor device. In particular, a gate capping insulation layer and a sidewall spacer insulation layer are formed of a material having a high etching selectivity to form a self-aligned contact portion when forming a bit line and a storage node plug contact hole. By preventing excessive etching of the gate cap insulating film, the possibility of short-circuit of the gate and the plug is eliminated, and an opening for exposing the contact hole for exposing the gate of the core / ferry part and the bit line plug for the cell part is simultaneously formed in a self-aligning manner. A method of forming a self-aligning contact portion of a semiconductor device to simplify the process, reduce the chip size and increase the process margin without additional equipment.

The conventional dynamic random access memory (DRAM) in the contact method of forming a device, reactive ion etching (reactive ion etching), to a gas that is used is conducted in a manner using conventional plasma such as a plasma-type mixed, such as Ar, CF _4, CHF ₃ gas In the case of using some high density plasma, only C ₂ F _{6 was} added to the contact hole forming process.

In general, a thick oxide film is deposited on a silicon substrate, and a photoresist pattern for forming a contact hole is formed thereon. The surface of the silicon substrate after the contact hole is also partially etched.

A method of forming a fine contact hole in a cell portion of a DRAM device according to the prior art is as follows.

A contact hole is formed by removing an interlayer insulating layer in the cell part by using a self-aligned contact forming process using a high selectivity ratio between an oxide film and a nitride film. In this case, in order to prevent a short circuit between the word line and the plug formed in the contact hole, a capping nitride film is formed thick on the word line, and a barrier nitride film used as an etch stop film is formed on the substrate surface on the capping nitride film.

One of the difficulties in the next generation of highly integrated device formation process is the problem of patterning holes of 0.2 μm or less. It is difficult to meet the resolution and design overlay margin required by the photo processing equipments currently used.

The method used to overcome this problem is a method of forming a self-aligned contact. By using the etching process with a large etching selectivity of the oxide film / nitride film in the cell contact forming process in which the silicon nitride barrier film is formed, the overlay margin can be increased, and the etch profile is inclined to form a maximum critical dimension of 0.2 μm or less. have.

However, in the self-aligned contact forming method using the barrier nitride film used as the etch stop film on the capping nitride film, the excessive etching is required in the etching process for forming the plug of the cell part, so that the loss of the capping nitride film is inevitable. Short circuit of the plug may occur.

In addition, since the capping insulating film formed on the gate of the core / ferry portion is to be removed after the plug formation, the gate electrode is exposed to expose the gate electrode. Therefore, an opening for exposing the bit line plug must be formed in the upper part of the plug when the nitride film is removed. Therefore, the opening formation margin is small, and it is difficult to form a contact hole forming process for interconnection between the opening portion and the core / ferry portion by a self-aligning method, which is complicated.

1A and 1B are process cross-sectional views illustrating a method for forming a contact of a semiconductor device according to the prior art.

Referring to FIG. 1A, a trench type field oxide layer (not shown) defining a device isolation region and an active region is formed and a silicon substrate 10 is formed on a silicon substrate 10 having a cell portion CE1 and a ferry / core portion PC1 defined therein. It is formed by growing a thermal oxide film for a gate insulating film.

Then, a doped polysilicon layer for gate formation is formed on the thermal oxide film by chemical vapor deposition, and then a nitride film is formed by chemical vapor deposition on a polysilicon layer with a capping insulating film. In this case, the silicide layer may be formed of tungsten or the like on the polysilicon layer.

Next, a photolithography process is performed on the nitride film, the polysilicon layer, and the thermal oxide film to form a first cap insulating film 131 formed of a nitride film on the cell portion CE1 and a first gate insulating film 111 on the bottom. Is formed by patterning the first gate 121, which is a word line interposed therebetween, and at the same time, a second cap insulating film formed of a nitride film remaining on the ferry / core portion PC1 is formed on the upper portion and the second gate insulating film 110 on the lower portion. ) Is formed a second gate (120).

Accordingly, the active region, which is a portion where the source / drain of the substrate 10 is to be formed, is exposed.

Then, a lightly doped drain (LDD) formation impurity ion implantation using the first gate 121 and the second gate 120 as an ion implantation mask is performed on the substrate at a low concentration, and then the pattern of the substrate 10 A nitride film, which is a material such as a capping insulating film, is deposited on the entire surface by chemical vapor deposition to form a nitride film for sidewall formation.

Next, the cell region CE1 is covered with a photoresist or the like, and then the nitride film of the exposed ferry / core portion PC1 is etched back to form a nitride film remaining on the side of the second gate 120 pattern 140. ). At this time, the nitride film 141 of the cell portion CE1 remains as it is.

Then, removing the photoresist, for example by oxygen ashing (O ₂ ashing).

Therefore, the cell portion CE1 is covered with the nitride film 141, and the active region of the substrate on which the high concentration impurity diffusion region of the ferry / core portion PC1 is formed is exposed.

Next, an n-type or p-type transistor is completed in the pair / core portion PC1 by implanting high concentration impurity ions onto the exposed substrate.

After completing the conductive transistors suitable for the cell portion CE1 and the ferry / core portion PC1, the first interlayer insulating layer 15 is thickly deposited on the entire surface of the substrate to fill the valleys between the gate patterns. In this case, BPSG, PETEOS, USG, or the like may be used as the first interlayer insulating layer 15.

Referring to FIG. 1B, after the photoresist is applied on the first interlayer insulating layer 15, a photoresist pattern (not shown) is formed to expose a predetermined portion of the first interlayer insulating layer 15 by exposure and development. do. At this time, the exposed portion of the first interlayer insulating layer 15 by the photoresist pattern is a portion defining the bit line contact plug forming portion of the cell portion CE1 and the doped region of the substrate on which the storage node contact plug of the capacitor is to be formed. to be.

Then, the first interlayer insulating layer 15 made of an oxide film of a portion not protected by the photoresist pattern is removed by anisotropic etching such as dry etching until the surface of the nitride film 141 is exposed, and then nitride etching is continued. Zero exposed nitride layer portions are removed to form contact holes exposing impurity doped regions of the substrate. In this case, a portion of the first cap insulation layer 131 is also removed while the nitride layer for forming the sidewall spacers is removed. This is because excessive etching is performed to completely expose the impurity doped region of the substrate.

Thus, a portion of the first gate 121 may be exposed and may be shorted with subsequent plugs, thereby reducing the gate shorting margin.

Next, a conductive layer is formed on the first interlayer insulating layer 15 to a thickness that sufficiently fills the contact holes. In this case, the conductive layer may form the doped polysilicon by chemical vapor deposition.

Then, the conductive layer is etched back or chemical mechanical polishing so as to expose the surface of the first interlayer insulating layer 15 so that the conductive layer remains only inside the contact hole. Accordingly, the bit line contact plug 161 and the storage node contact plug 160 formed of the remaining conductive layers are formed.

Next, a second interlayer insulating layer 17 is formed by depositing an oxide film on the first interlayer insulating layer 15 including the surfaces of the plugs 161 and 160.

Then, on the second interlayer insulating layer 17, the photoresist is formed on the surface of the second interlayer insulating layer 17 on the bit line contact plug 161 and on the second gate 120 of the ferry / core part PC1. A photoresist pattern (not shown) is formed to expose the surface of the second interlayer insulating layer 17. In this case, the portion exposed by the photoresist pattern should be formed so as to be within the surface area of the upper surface of the bit line contact plug 161 and the second cap insulating layer 130.

Next, the second interlayer insulating layer 17 which is not protected by the photoresist pattern and the first interlayer insulating layer 15 of the ferry / core portion PC1 are removed to form the surface of the bit line contact plug 161 and the nitride film. The surfaces of the second cap insulating films 130 are exposed, respectively. Thus, a part of the first hole BH1 and the second hole IH1 is formed.

An anisotropic etching using a nitride film etchant is performed on the exposed second cap insulation layer 130 to expose the surface of the second gate 120. In this case, since the first cap insulation layer 131 formed of the nitride layer 141 of the cell unit CE1 and the nitride layer disposed under the cell unit CE1 should not be exposed, the alignment margin of the first hole BH1 exposing the bit line contact plug 161 is increased. Decreases.

Then, the photoresist pattern is removed by a method such as oxygen ashing.

Subsequently, although not shown, a general DRAM device manufacturing process, such as filling a space between the first hole BH1 and the second hole IH1 with a conductive material and forming a bit line and a second gate connection wiring, respectively. Proceed.

However, in the above-described conventional method for forming a contact of a semiconductor device, since the cap insulating film and the sidewall spacer of the gate are formed of the same insulating material as a nitride film, the cap insulating film is lost due to excessive etching when the plug contact hole is formed. The bit line forming opening and the bit line contact plug overlap each other because the shoulder margin of the cavities is reduced and the bit line forming opening and the ferry / core connecting opening cannot be formed in a self-aligning manner. As a result, process margins are reduced and there is a disadvantage in that the integration of semiconductor devices is high.

Accordingly, an object of the present invention is to form the gate capping insulating film and the sidewall spacer insulating film of a material having a large etch line tap ratio to form a self-aligned contact portion when forming a bit line and a storage node plug contact hole, thereby preventing excessive etching of the gate cap insulating film. This eliminates the possibility of short-circuit of the gate and plug, and simultaneously forms a contact hole for exposing the gate of the core / ferry part and an opening for exposing the bit line plug of the cell part in a self-aligning manner, thereby simplifying the process and eliminating the need for chips. The present invention provides a method for forming a self-aligned contact portion of a semiconductor device to reduce the size and increase the process margin.

A contact forming method of a semiconductor device according to an embodiment of the present invention for achieving the above object is a cap insulating film made of a second insulating film, a gate made of a first conductive layer on a semiconductor substrate in which a device active region and an isolation region are defined; Forming a gate pattern formed of a gate insulating film formed of a first insulating film, forming a low concentration impurity diffusion region in the active region below the sidewall of the gate pattern, and forming the gate pattern on the semiconductor substrate including the gate pattern; Forming a second insulating film and a third insulating film having a large etching selectivity to a predetermined thickness, forming a high concentration impurity diffusion region in the active region of the semiconductor substrate using the third insulating film, and forming a third insulating film on the third insulating film. Forming an interlayer insulating layer, and removing a predetermined portion of the first interlayer insulating layer Forming a contact hole exposing the third insulating film over the acid region, removing the exposed third insulating film of the contact hole to expose a portion of the impurity diffusion region, and exposing the exposed impurity diffusion region; Forming a conductive plug in the contact hole so as to be in contact, forming a second interlayer insulating layer on the first interlayer insulating layer so as to cover the plug, and removing a predetermined portion of the second interlayer insulating layer; Exposing the surface of the plug.

According to another aspect of the present invention, there is provided a contact forming method of a semiconductor device according to another embodiment of the present invention. And forming a second gate, forming an impurity diffusion region in the active regions of the first gate and the second gate, and covering the cell portion including the first gate with a first insulating film. / Forming a sidewall spacer on the side of the second gate of the core portion, forming a first interlayer insulating layer on the front surface of the semiconductor substrate, and forming an upper portion of the impurity diffusion region under the first gate side of the cell portion. Forming a contact hole exposing a surface of the first insulating film positioned at the second insulating film; and removing the first insulating film exposed by the contact hole. Exposing the impurity diffusion region, forming a conductive plug filling the contact hole to contact the exposed impurity diffusion region, and forming a second interlayer insulating layer on the first interlayer insulating layer including the plug. Forming a layer and removing a predetermined portion of the second interlayer insulating layer and the first interlayer insulating layer to expose the upper surface of the plug and simultaneously expose the cap insulating film of the second gate of the ferry / core portion. And exposing the upper surface of the second gate by removing the exposed cap insulation layer.

1A and 1B are cross-sectional views illustrating a method for forming a contact in a semiconductor device according to the prior art;

2A through 2E are cross-sectional views illustrating a method for forming a contact including a polysilicon plug of a semiconductor device according to the present invention.

The present invention improves the shoulder margin with the gate when forming a bit line contact plug and forms a subsequent hole or opening forming process in a self-aligning method in manufacturing a DRAM of a semiconductor device. That is, in the present invention, the cap insulation layer forming material for protecting the upper part of the gate and the gate sidewall spacer forming material of the ferry / core part are made of different materials, and the holes for forming the bit lines on the bit line contact plug are formed in a self-aligning manner. In addition, the shoulder margin with the gate of the cell portion is improved, and at the same time, the contact formation for wiring connection of the ferry / core portion is also formed by a self-aligning method, thereby reducing chip size and improving process margin.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2A through 2E are cross-sectional views illustrating a method for forming a contact including a polysilicon plug of a semiconductor device according to the present invention.

Referring to FIG. 2A, a trench type field oxide layer (not shown) defining a device isolation region and an active region is formed, and a silicon substrate 20 is formed on a silicon substrate 20, which is a semiconductor substrate in which a cell portion CE2 and a ferry / core portion PC2 are defined. It is formed by growing a thermal oxide film for a gate insulating film.

Then, a doped polysilicon layer for gate formation is formed on the thermal oxide film by chemical vapor deposition, and then an oxide film is formed by chemical vapor deposition on a polysilicon layer with a capping insulating film. In this case, the silicide layer may be formed of tungsten or the like on the polysilicon layer.

Then, a photolithography is performed on the capping oxide film, the gate polysilicon layer, and the thermal insulating film for the gate insulating film, and a first cap insulating film 231 formed of an oxide film is formed on the cell portion CE2, and the lower portion The first gate 221, which is a word line having the first gate insulating film 211 interposed therebetween, is patterned, and at the same time, the second cap insulating film 230 made of the remaining oxide film is formed on the ferry / core portion PC2. The second gate 220 is formed at the lower portion and the second gate insulating layer 210 is interposed therebetween.

As a result of the patterning, the active region, which is a portion where the source / drain of the substrate 20 is to be formed, is exposed.

The first cap insulation layer 231 is formed of an oxide layer in a subsequent process, in which a sidewall spacer is formed of a nitride layer, thereby forming a contact hole for forming a bit line contact plug and a capacitor storage node contact plug. This is to prevent the cap insulating film from being etched from the nitride film removing process covering the surface of the active region when forming the C-type method. Therefore, the cap insulating film and the sidewall spacer forming material are formed of materials having high etching selectivity.

In addition, impurity ion implantation for forming a lightly doped drain (LDD) using the first gate 221, the second gate 220, and the like as an ion implantation mask is performed at a low concentration on the substrate.

Referring to FIG. 2B, a capping insulating film made of an oxide film and a nitride film having a high etching selectivity are deposited by chemical vapor deposition on the entire surface of the substrate 20 on which the patterns are formed to form a nitride film for forming sidewall spacers.

Next, the cell region CE2 is covered with an etch mask such as a photoresist, and then the nitride film of the exposed ferry / core portion PC2 is etched back to form a nitride film remaining on the side of the second gate 220 pattern. The sidewall spacers 240 are formed. At this time, the nitride film 241 of the cell portion CE2 remains as it is.

Then, removing the photoresist, for example by oxygen ashing (O ₂ ashing).

Accordingly, the cell portion CE2 is covered with the remaining nitride film 241, and the ferry / core portion PC2 has sidewall spacers 240 that protect side surfaces of the second gate 220, and a high concentration of impurity diffusion region. The active region of the substrate 20 to be formed is exposed.

Next, an n-type or p-type transistor is completed in the pair / core part PC2 by implanting high concentration impurity ions onto the exposed substrate.

After completing the transistors of the conductive type suitable for the cell portion CE2 and the ferry / core portion PC2, the first interlayer insulating layer 25 is buried between the gate patterns in the entire surface of the substrate 20 on which the structure is formed. Deposit thickly. In this case, BPSG, PETEOS, USG, or the like may be used as the first interlayer insulating layer 25.

Referring to FIG. 2C, after forming a photoresist on the first interlayer insulating layer 25, a photoresist pattern (not shown) is formed to expose a predetermined portion of the first interlayer insulating layer 25 by exposure and development. do. At this time, the exposed portion of the first interlayer insulating layer 25 by the photoresist pattern is a portion defining the bit line contact plug forming portion of the cell portion CE2 and the doped region of the substrate on which the storage node contact plug of the capacitor is to be formed. The ferry / core portion PC2 is covered in its entirety with a photoresist pattern.

The first interlayer insulating layer 25 made of an oxide film of a portion not protected by the photoresist pattern is removed by anisotropic etching such as dry etching until the surface of the nitride film 241 is exposed. At this time, the first interlayer insulating layer positioned between the patterns including the first gate 221 is removed in a manner that is automatically aligned by the remaining nitride film 241 to form the first contact hole BL for forming a bit line contact plug. And a second contact hole SN for forming a capacitor storage node contact plug, and a nitride film 241 remains in the bottom portions of the first and second contact holes BL and SN.

Referring to FIG. 2D, the nitride film portion exposed by the nitride film etchant is removed by anisotropic etching to expose the impurity doped region of the substrate, which is an impurity diffusion region. In this case, even when a portion of the first cap insulation layer 231 is exposed while the nitride layer for forming the sidewall spacers is removed, a short circuit between the first gate 221 and the plugs to be formed later is prevented. The reason for exposing the first cap insulation layer 231 is that the sidewall spacer nitride film 241 is overetched to completely expose the impurity doped region of the substrate.

Therefore, since the exposure of the first gate 221 is prevented, plugs and shorts formed afterwards are prevented, thereby increasing the margin of the first and second contact hole forming processes.

Then, a conductive layer is formed on the first interlayer insulating layer 25 to a thickness sufficiently filling the first contact holes and the second contact holes. In this case, the conductive layer may form the doped polysilicon by chemical vapor deposition.

Then, the conductive layer is subjected to etch back or chemical mechanical polishing to expose the surface of the first interlayer insulating layer 25 so that the conductive layer remains only inside the contact hole. Accordingly, the bit line contact plug 261 and the storage node contact plug 260 formed of the remaining conductive layers are formed.

Referring to FIG. 2E, a second interlayer insulating layer 27 is formed by depositing an oxide layer on the first interlayer insulating layer 25 including the surfaces of the plugs 261 and 260. In this case, the second interlayer insulating layer 27 is formed of a material having excellent flowability to planarize the surface.

On the second interlayer insulating layer 27, the surface of the second interlayer insulating layer 27 on the bit line contact plug 261 of the cell portion CE2 and the second gate of the ferry / core portion PC2 are formed of photoresist on the second interlayer insulating layer 27. A photoresist pattern (not shown) for exposing the surface of the second interlayer insulating layer 27 on the upper portion 220 is formed. In this case, a portion exposed by the photoresist pattern may include a portion of the nitride layer 241 and the sidewall spacers 240 remaining beyond the upper surface area of the bit line contact plug 261 and the second cap insulation layer 230. can do. The first gate 221 is protected by the first cap insulating film 231 which is an oxide film even when a part of the nitride film 241 is removed when the second cap insulating film is removed to expose the surface of the second gate 220. This is because a short circuit with the bit line contact plug 261 or the storage node contact plug 260 is prevented.

Next, the second interlayer insulating layer 27 which is not protected by the photoresist pattern and the first interlayer insulating layer 25 of the ferry / core portion PC2 are removed to form the surface of the bit line contact plug 261 and the nitride film. The surfaces of the second cap insulating films 230 are exposed, respectively. Thus, the first hole BH2 exposing the bit line contact plug surface is completed and a portion of the second hole IH2 is formed to expose the second gate.

An anisotropic etching using a nitride film etchant is performed on the exposed second cap insulating film of the ferry / core part PC2 to expose the surface of the second gate 220. In this case, even when the first cap insulating layer 231 including the nitride layer 241 of the cell portion CE1 and the nitride layer disposed below the cell portion CE1 is exposed, the width w1 exposing the bit line contact plug 261 is exposed due to a large etching selectivity. The alignment margin of the first hole BH2 increases. At this time, reference numeral w2 of the ferry / core portion PC2 indicates the width of the second hole IH2.

Therefore, since the first hole BH2 and the second hole IH2 are simultaneously formed, the process is simplified and the co-operation margin is increased. In this process, since there is no additional process compared to the process of the prior art, the yield of the product is increased without increasing the manufacturing cost and processing time.

Then, the photoresist pattern is removed by a method such as oxygen ashing.

Subsequently, although not shown, a general DRAM device manufacturing process, such as filling a space between the first hole BH2 and the second hole IH2 with a conductive material and forming a bit line and a second gate connection wiring, respectively. Proceed.

Therefore, since the cap insulation layer and the sidewall spacer are formed of a material having a high etching selectivity, the shoulder margin between the plug and the gate is increased, thereby improving the process and improving the product yield, and simultaneously forming the first and second holes. This simplifies the process and increases process margins.

Claims (7)

delete delete delete Forming first and second gates each having a cap insulating layer formed thereon and a gate insulating layer disposed thereunder on a semiconductor substrate having a cell portion and a ferry / core portion defined therein; Forming an impurity diffusion region in active regions of the first gate and the second gate; Forming a sidewall spacer on a side of the second gate of the ferry / core portion covering the cell portion including the first gate with a first insulating film; Forming a first interlayer insulating layer on an entire surface of the semiconductor substrate; Forming a contact hole exposing a surface of the first insulating film located above the impurity diffusion region at the lower end of the first gate side of the cell portion; Exposing the impurity diffusion region by removing the first insulating layer exposed by the contact hole; Forming a conductive plug filling the contact hole to contact the exposed impurity diffusion region; Forming a second interlayer dielectric layer on the first interlayer dielectric layer including the plug; Removing a predetermined portion of the second interlayer insulating layer and the first interlayer insulating layer to expose an upper surface of the plug and simultaneously expose the cap insulating film of the second gate of the ferry / core portion; And removing the exposed cap insulation layer to expose the upper surface of the second gate. The method of claim 4, wherein the cap insulating layer and the first insulating layer are formed of a material having a large etching selectivity. The method according to claim 4, wherein the cap insulating film is formed of an oxide film, the first insulating film is formed of a nitride film, and the first interlayer insulating layer and the second interlayer insulating layer are formed of an oxide film. The method of claim 4, further comprising: forming a bit line on the exposed plug; And forming a wiring for electrically connecting the exposed second gate.