KR20060010465A - Method for fabricating cmosfet having dual gate - Google Patents

Abstract

The present invention discloses a method of manufacturing a CMOS transistor having a dual gate structure capable of preventing deterioration of characteristics of a CMOS device by increasing doping efficiency of an nMOSFET and a pMOSFET gate electrode. The disclosed method comprises the steps of providing a silicon substrate having an nMOS region and a pMOS region defined; Sequentially forming a gate oxide film, an undoped first amorphous silicon film, and a P-doped second amorphous silicon film on the silicon substrate; Performing a first heat treatment process on the resultant to crystallize the undoped first amorphous silicon film and the P-doped second amorphous silicon film into the undoped first polysilicon film and the P-doped second polysilicon film, respectively. ; Selectively wet etching a portion of the P-doped second polysilicon film in the pMOS region; Selectively performing a B ion implantation process on the pMOS region to modify an undoped first polysilicon film portion of the pMOS region with a B-doped first polysilicon film; Performing a second heat treatment process on the resultant to modify the undoped first polysilicon film of the nMOS region into a P-doped first polysilicon film; Removing the P-doped second polysilicon film remaining on the P-doped first polysilicon film in the nMOS region; Selectively etching the P-doped first polysilicon film and the B-doped first polysilicon film to form an nMOS gate electrode and a pMOS gate electrode, respectively; Forming an n-type LDD region and a p-type LDD region in both substrates of each of the nMOS and pMOS gate electrodes; Forming spacers on both sidewalls of the nMOS and pMOS gate electrodes; And performing ion implantation of a high concentration dopant in the substrate on both sides of the spacer, and then performing a third heat treatment process to form n-type and p-type source / drain regions, respectively.

Description

Manufacturing method of CMOS transistor having dual gate structure {METHOD FOR FABRICATING CMOSFET HAVING DUAL GATE}

1 is a cross-sectional view for explaining a method of manufacturing a CMOS transistor having a dual gate structure according to the prior art.

2A to 2F are cross-sectional views of processes for describing a method of manufacturing a CMOS transistor having a dual gate structure according to an exemplary embodiment of the present invention.

Explanation of symbols on main parts of drawing

21 silicon substrate 22 device isolation film

23 gate oxide film 24 undoped first amorphous silicon film

25: P-doped second amorphous silicon film 26: primary heat treatment process

24a: undoped first polysilicon film 25a: P-doped second polysilicon film

27: mask

25b: P-doped second polysilicon film remaining after etching

28: B ion implantation process 24b: B-doped first polysilicon film

24c: undoped first polysilicon film in nMOS region

29: secondary heat treatment step 24d: P-doped first polysilicon film

24e: nMOS gate electrode 24f: pMOS gate electrode                 

30a: n-type LDD region 30b: p-type LDD region

31 spacer 32a n-type source / drain region

32b: p-type source / drain region

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a CMOS transistor having a dual gate structure capable of preventing deterioration of characteristics of a CMOS device by increasing doping efficiency of nMOSFET and pMOSFET gate electrodes. It relates to a manufacturing method.

As is well known, pMOSFETs using polysilicon gate electrodes doped with n-type impurities in CMOS devices form buried channels beneath the silicon substrate surface, in which case nMOSFETs form channels on the silicon substrate surface. Threshold voltages are different between and pMOSFETs, which can limit the design and fabrication of devices.

Therefore, a high concentration of n-type impurity doping is applied to the gate polysilicon of the nMOSFET, and a high concentration of p-type impurity doping is applied to the gate polysilicon of the pMOSFET. Such a structure is commonly referred to as a dual gate structure.

In general, a method of ion implanting phosphorous (P) is applied to the gate polysilicon of the nMOSFET, and a method of ion implanting boron (B) is applied to the gate polysilicon of the pMOSFET.

As described above, the reason for doping the polysilicon film as the gate electrode is to lower the resistance of the gate electrode.

1 is a cross-sectional view illustrating a method of manufacturing a CMOS transistor having a dual gate structure according to the related art, which will be described below.

In the conventional method of manufacturing a CMOS transistor having a dual gate structure, as shown in FIG. 1, first, a silicon substrate 11 in which an nMOSFET region and a pMOSFET region are defined is provided. A device isolation film 12 is formed by applying a well-known shallow trench isolation (STI) process to the field region. Then, p-type wells (not shown) are formed in the nMOSFET region through ion implantation of impurities using n-well masks (not shown) and p-well masks (not shown), and n-type wells (not shown) in the pMOSFET region. To form.

Subsequently, an oxide film and a polysilicon film are sequentially formed on the resultant substrate, and then phosphorus is selectively doped into the polysilicon film of the nMOSFET region, and the doped boron is selectively doped into the polysilicon film of the pMOSFET region. The polysilicon film and the oxide film are selectively etched to form the n-type gate electrode 14a of the nMOSFET and the p-type gate electrode 14b of the pMOSFET, respectively. In this case, reference numeral 13, which is not described in FIG. 1, is an oxide film remaining after etching, and becomes a gate oxide film.

Then, an n-type LDD on the silicon substrate 11 on both sides of the n-type and p-type gate electrodes 14a and 14b through an impurity ion implantation process using the n-type and p-type gate electrodes 14a and 14b as a mask. After the lightly doped drain region 16a and the p-type LDD region 16b are formed, spacers 15 are formed on both sidewalls of the n-type and p-type gate electrodes 14a and 14b.

Then, after impurity ion implantation using the n-type and p-type gate electrodes 14a and 14b including the spacer 15 as a mask, an n-type source is applied to the silicon substrate 11 on both sides of the spacer through a heat treatment process. The / drain region 17a and the p-type source / drain region 17b are formed.

However, with the recent high integration of devices, there are limitations on the heat treatment process in the nMOSFET and pMOSFET source / drain region formation processes in connection with decreasing channel length and gate oxide film thickness. That is, in the trend that the channel length and the gate oxide film thickness are reduced due to the high integration of the device, when the heat treatment process in the source / drain region forming process is performed at a high temperature of 1000 ° C. or more to improve the leakage current characteristics, There is a problem that the characteristics of the device deteriorate.

Accordingly, the present invention has been made to solve the above problems, by increasing the doping efficiency of the nMOSFET and pMOSFET gate electrode, thereby minimizing the limitation on the heat treatment process in the source / drain region forming process, the characteristics of the CMOS device It is an object of the present invention to provide a method for manufacturing a CMOS transistor having a dual gate structure capable of preventing the degradation thereof.

A method of manufacturing a CMOS transistor having a dual gate structure according to the present invention for achieving the above object includes providing a silicon substrate having an nMOS region and a pMOS region defined therein; Sequentially forming a gate oxide film, an undoped first amorphous silicon film, and a P-doped second amorphous silicon film on the silicon substrate; Performing a first heat treatment process on the resultant to crystallize the undoped first amorphous silicon film and the P-doped second amorphous silicon film into the undoped first polysilicon film and the P-doped second polysilicon film, respectively. ; Selectively wet etching a portion of the P-doped second polysilicon film in the pMOS region; Selectively performing a B ion implantation process on the pMOS region to modify an undoped first polysilicon film portion of the pMOS region with a B-doped first polysilicon film; Performing a second heat treatment process on the resultant to modify the undoped first polysilicon film of the nMOS region into a P-doped first polysilicon film; Removing the P-doped second polysilicon film remaining on the P-doped first polysilicon film in the nMOS region; Selectively etching the P-doped first polysilicon film and the B-doped first polysilicon film to form an nMOS gate electrode and a pMOS gate electrode, respectively; Forming an n-type LDD region and a p-type LDD region in both substrates of each of the nMOS and pMOS gate electrodes; Forming spacers on both sidewalls of the nMOS and pMOS gate electrodes; And performing ion implantation of a high concentration dopant into the substrate on both sides of the spacer, and then performing a third heat treatment process to form n-type and p-type source / drain regions, respectively.

Here, the undoped first amorphous silicon film is formed to a thickness of 1500 ~ 2000Å. The P-doped second amorphous silicon film is doped with P at a concentration of 5 × 10 ¹⁹ to 1 × 10 ²⁰ / cm 3 to form a thickness of 300 to 700 Pa, and the first heat treatment process is performed at a temperature of 650 ° C. Perform for hours.

In addition, the wet etching is performed using a mixed solution of HNO ₃ / CH ₃ COOH / HF / DI, the B ion implantation process is applied to the ion implantation energy of 5 ~ 10keV, 1 × 10 ¹⁵ ~ 3 × 10 ¹⁵ It is performed by supplying an ion implantation dose of / cm 2.

In addition, the secondary heat treatment process is carried out in an RTA method for 30 to 60 seconds at a temperature of 850 ~ 900 ℃, the third heat treatment process is performed at a temperature of 1000 ~ 1100 ℃ using a spike RTP apparatus.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A through 2F are cross-sectional views of processes for describing a method of manufacturing a CMOS transistor having a dual gate structure according to an exemplary embodiment of the present invention.

In the method of manufacturing a CMOS transistor having a dual gate structure according to an exemplary embodiment of the present invention, as shown in FIG. 2A, first, an nMOSFET region (hereinafter referred to as an 'nMOS region') and a pMOSFET region (hereinafter, a 'pMOS region') are described. After the silicon substrate 21 is defined, a well-known shallow trench isolation (STI) process is applied to the field region of the silicon substrate 21 to form the device isolation layer 22. Then, p-type wells (not shown) are formed in the nMOS region and n-type wells (not shown) are formed in the nMOS region through ion implantation of impurities using an n well mask (not shown) and a p-well mask (not shown). Form.

Subsequently, the gate oxide layer 23, the undoped first amorphous silicon layer 24 that is not doped with impurities, and the P-doped P that is doped with phosphorus P are formed on the silicon substrate 21. -doped) A second amorphous silicon film 25 is formed in sequence. Here, the undoped first amorphous silicon film 24 is formed to a thickness of 1500 ~ 2000Å, the P-doped second amorphous silicon film 25 is 5 × 10 ¹⁹ ~ 1 × 10 ²⁰ / cm 3 Doping P to form a thickness of 300 ~ 700Å.

Thereafter, as shown in FIG. 2B, the resultant first heat treatment process 26 is performed to crystallize the undoped first amorphous silicon film and the P-doped second amorphous silicon film. That is, the first undoped first amorphous silicon film is modified to the undoped first polysilicon film 24a through the first heat treatment process 26, and the P-doped second amorphous silicon film is converted into a P-doping agent. The polysilicon film 25a is modified.

Here, the first heat treatment process 26 is performed for 1 hour at a temperature of 650 ℃, this first heat treatment process 26 is an undoped first polysilicon film 24a and P-doped second polysilicon It serves to increase the wet etching selectivity between the film (25a).

Next, as shown in FIG. 2C, a photosensitive film is coated on the P-doped second polysilicon film 25a and patterned by exposure and development to form a mask 27 exposing the pMOS region.

Then, the P-doped second polysilicon film portion of the pMOS region exposed by the mask 27 is wet etched. Here, the wet etching is performed using a mixed solution of HNO ₃ / CH ₃ COOH / HF / d (dionized water). On the other hand, when using the mixed solution of HNO ₃ / CH ₃ COOH / HF / DI, the etching selectivity ratio between the undoped first polysilicon film 24a and the P-doped second polysilicon film is 60: 1 to After the wet etching of the P-doped second polysilicon film due to such a high etching selectivity, the undoped first polysilicon film 24a is not etched and P-doped in the pMOS region. Only the second polysilicon film portion is etched. In this case, reference numeral 25b, which is not described in FIG. 2C, indicates the P-doped second polysilicon film remaining after etching.

Subsequently, as shown in FIG. 2D, the B-doped first polysilicon film 24b is formed by performing the B ion implantation process 28 using the mask 27 to perform the undoped first polysilicon film in the pMOS region. ). Here, the B ion implantation step 28 is performed by applying an ion implantation energy of 5-10 keV and supplying an ion implantation dose of 1 × 10 ¹⁵ to 3 × 10 ¹⁵ / cm 2.

On the other hand, the B ion implantation process 28 serves to increase the doping efficiency of the subsequently formed pMOS gate electrode. In this case, reference numeral 24c, which is not described in FIG. 2D, represents an undoped first polysilicon film of the nMOS region.

Then, as shown in FIG. 2E, the mask is removed. Thereafter, a second heat treatment process 29 is performed on the resultant to obtain doped phosphorus doped in the P-doped second polysilicon layer 25b remaining after the nMOS region is etched. The undoped first polysilicon film in the nMOS region is modified to a P-doped first polysilicon film 24d by diffusion and activation into a silicon film, and the B-doped first polysilicon film 24b in the pMOS region is also modified. Activates the doped boron.

Here, the secondary heat treatment process 29 is performed by a rapid thermal annealing (RTA) method for 30 to 60 seconds at a temperature of 850 ~ 900 ℃, which activates the dopants of nMOS and pMOS, respectively, nMOS and pMOS gate It serves to increase the doping efficiency of the electrode.

Thereafter, as shown in FIG. 2F, the P-doped second polysilicon layer remaining after the etching on the P-doped first polysilicon layer 24d is removed, and then the P-doped first poly The silicon film 24d and the B-doped first polysilicon film 24b are selectively etched to form an nMOS gate electrode 24e and a pMOS gate electrode 24f, respectively.

Subsequently, the n-type LDD region 30a of the nMOS and the p-type LDD region 30b of the pMOS are implanted into the nMOS gate electrode 24e and the pMOS gate electrode 24f through the ion implantation of low concentration dopant. After forming the spacers, spacers 31 are formed on both side walls of the gate electrodes.

Then, after ion implantation of a high concentration dopant using the nMOS and pMOS gate electrodes 24e and 24f and the spacer 31 as a mask, a third heat treatment process is performed to perform the substrate 21 on both sides of the spacer 31. N-type source / drain regions 32a of nMOS and p-type source / drain regions 32b of pMOS are formed in the inside. Here, the third heat treatment process is carried out at a temperature of 1000 ~ 1100 ℃ using a spike (RPTP) rapid thermal process (RTP) apparatus. In this case, even when the tertiary heat treatment process is performed at the high temperature conditions as described above, since the dopants are previously doped and activated in the nMOS and pMOS gate formation regions in the previous process, the restriction on the tertiary heat treatment process can be minimized. . That is, even if the tertiary heat treatment process is performed at the high temperature conditions as described above, it is possible to prevent the deterioration of the characteristics of the device.

As described above, the present invention can increase the doping efficiency of the nMOS and pMOS gate electrodes by doping and activating respective dopants in the nMOS and pMOS gate formation regions before forming the nMOS and pMOS gate electrodes. Therefore, it is possible to minimize the restriction on the heat treatment process in the subsequent source / drain region forming process. Therefore, the present invention can be prevented from deteriorating the characteristics of the CMOS device, and can be advantageously applied to the production of highly integrated devices.

Claims (8)

providing a silicon substrate in which an nMOS region and a pMOS region are defined; Sequentially forming a gate oxide film, an undoped first amorphous silicon film, and a P-doped second amorphous silicon film on the silicon substrate; Performing a first heat treatment process on the resultant to crystallize the undoped first amorphous silicon film and the P-doped second amorphous silicon film into the undoped first polysilicon film and the P-doped second polysilicon film, respectively. ; Selectively wet etching a portion of the P-doped second polysilicon film in the pMOS region; Selectively performing a B ion implantation process on the pMOS region to modify an undoped first polysilicon film portion of the pMOS region with a B-doped first polysilicon film; Performing a second heat treatment process on the resultant to modify the undoped first polysilicon film of the nMOS region into a P-doped first polysilicon film; Removing the P-doped second polysilicon film remaining on the P-doped first polysilicon film in the nMOS region; Selectively etching the P-doped first polysilicon film and the B-doped first polysilicon film to form an nMOS gate electrode and a pMOS gate electrode, respectively; Forming an n-type LDD region and a p-type LDD region in both substrates of each of the nMOS and pMOS gate electrodes; Forming spacers on both sidewalls of the nMOS and pMOS gate electrodes; And Performing ion implantation of a high concentration dopant into the substrate on both sides of the spacer, and then performing a third heat treatment process to form n-type and p-type source / drain regions, respectively. Method of manufacturing a transistor. 2. The method of claim 1, wherein the undoped first amorphous silicon film is formed to a thickness of 1500 to 2000 microseconds. 2. The dual gate structure of claim 1, wherein the P-doped second amorphous silicon film is formed to a thickness of 300 to 700 Å by doping P having a concentration of 5 x 10 ¹⁹ to 1 x 10 ²⁰ / cm 3. Method of manufacturing CMOS transistors. The method of claim 1, wherein the first heat treatment is performed at a temperature of 650 ° C. for 1 hour. The method of claim 1, wherein the wet etching is performed using a mixed solution of HNO ₃ / CH ₃ COOH / HF / DI. The dual gate structure of claim 1, wherein the B ion implantation step is performed by applying an ion implantation energy of 5 to 10 keV and supplying an ion implantation dose of 1 x 10 ¹⁵ to 3 x 10 ¹⁵ / cm 2. Method of manufacturing a CMOS transistor having a. The method of claim 1, wherein the secondary heat treatment process is performed in an RTA method at a temperature of 850 ° C. to 900 ° C. for 30 to 60 seconds. The method of claim 1, wherein the tertiary heat treatment process is performed at a temperature of 1000 to 1100 ° C. using a spike RTP apparatus.

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