KR20040083860A - Apparatus for network synchronization and switching in ATM exchange - Google Patents

Abstract

PURPOSE: A switching/network synchronization device of an ATM exchange is provided to receive reference clocks, and to generate synchronous clocks by using a DP(Digital Programmable)-PLL(Phase Local Loop) to use the synchronous clocks as system clocks of the exchange. CONSTITUTION: A shared buffer switch(11) switches ATM cells. A board controller(12) generates various control signals, and performs interface/alarm signal collecting functions with a processor(14). A power unit(13) receives power, and supplies the received power to each block. The processor(14) initializes a switching fabric while reading a phase difference to control a reference voltage of a voltage control oscillator, and carries out IPC(Inter Process Communication) with an upper processor. A network synchronizer(15) receives reference clocks from two sheets of line cards, selects a normal clock to perform a DP-PLL function, and distributes synchronized system clocks to each line card.

Description

Apparatus for network synchronization and switching in ATM exchange}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching / network synchronization device of an asynchronous transfer mode (ATM) exchange, and more particularly, to implement a switchboard and a network board on a single board, and to provide a separate reference clock supply device or various A switch of an asynchronous transfer mode switch that receives a reference clock from a line card and generates a synchronous clock using a Digital Programmable-Phase Local Loop (DP-PLL) to use as the system clock of the exchange. It relates to a network device.

Typically, when a network is composed of digital switching system and transmission device using asynchronous transmission mode (ATM) technology as well as digital switching system or transmission equipment, there is a need to synchronize clocks between equipment. In this case, the synchronization network is a networked synchronization scheme in which clocks of all nodes in the network can be connected to the same frequency.

The exchange system used in the public network uses a clock synchronized with the clock of the synchronization network when transmitting data to the subscriber while operating a separate synchronization network, and the subscriber extracts and uses the clock transmitted from the synchronization network.

The network synchronizer is necessary to remove the temporal error between systems when interworking multiple systems. In the same system, synchronization is controlled based on the clock received from the upper station of the network synchronizer.

Therefore, the accuracy of the synchronizer is required to be very high, and the system placed at a very important position in the system of the synchronizer should be supplied with a high accuracy of the synchronizer clock. Typically, a network synchronizer clock was received on a digital signaling (DS1) or European transmission (E1) line.

On the other hand, if you look at the existing ATM switch or ATM router device, it can be seen that the switch board for ATM cell switching and the network board for supplying a reference clock are implemented as each board.

That is, the switch board is implemented as a separate board from the manipulator board to perform ATM cell switching operation, and the manipulator board is also implemented as a separate board from the switch board to receive and supply a reference clock.

Therefore, the conventional ATM switch or router has a problem in that the implementation of the device is complicated by the use of many boards, as well as the cost of implementing the device in terms of economics.

Accordingly, the present invention has been proposed to solve various problems occurring in the conventional ATM switch (or router) as described above.

It is an object of the present invention to implement a switchboard and a network synchronizer board in one board, receive a reference clock from a separate reference clock supply or various types of line cards, and use a digital programmable phase synchronization loop (DP-PLL: Digital). The purpose of the present invention is to provide a switch / manipulator device of an asynchronous transfer mode switch that generates a synchronous clock using a programmable-phase local loop (PL) to be used as a system clock of an exchange.

The present invention for achieving the above object,

A shared buffer switch unit for switching ATM cells;

It generates various control signals necessary to control the switch unit, and performs functions such as monitoring the received clock of the network synchronizer, selecting a reference clock for synchronization, clock division and system clock retiming, matching with the processor, and collecting alarm signals. A board controller;

It is connected to the board control unit, and controls the initialization of the switching fabric, reads the phase difference to control the reference voltage of the voltage controlled oscillator, and the overall board maintenance function and the upper processor and interprocess communication (IPC) function A processor to perform;

Receives a reference clock from E1 or RS422 from the outside, receives a reference clock from two line cards, selects a normal clock among the reference clocks selected by the processor, and distributes a synchronized system clock to each line card. A manipulator to perform;

It is characterized by consisting of a power supply for supplying the power required for the switch unit, the board control unit, the processor, the network unit to receive power from the power supply through the back board.

1 is a block diagram showing the configuration of a switch / network device of an asynchronous transfer mode (ATM) switch according to the present invention,

2 is a block diagram showing an embodiment of the network synchronizer of FIG.

3 is a block diagram illustrating an embodiment of a board controller of FIG. 1.

<Explanation of symbols for the main parts of the drawings>

12 ..... Board Controls

14 ..... Processor

15 ..... network donation

23 ..... Voltage controlled oscillators

24 ..... Clock Distribution

31 ..... processor matching

33 ..... Redundant clock supervision and selection

34 ..... reference clock dispensing part

35 ..... Oscillation Clock Divider

36 ..... Phase difference detector

Hereinafter, a preferred embodiment of the present invention according to the technical spirit as described above will be described in detail with reference to the accompanying drawings.

1 is a block diagram showing the configuration of a switch / network device of an asynchronous transfer mode (ATM) exchange according to the present invention.

Here, reference numeral 11 denotes a shared buffer type switch unit for switching ATM cells, and reference numeral 12 is implemented as an FPGA to generate various control signals necessary to control the switch unit 11, and the network synchronizer unit 15 to be described later. Represents a board control unit that performs functions such as monitoring the received clock of a clock, selecting a reference clock for synchronization, clock division and system clock retiming, matching with the processor 14 and collecting alarm signals, and reference numeral 13 denotes a back board from a power supply. The power supply unit supplies the power required to each block by receiving power through it. Reference numeral 14 uses the MPC860 module to control the reference voltage of the voltage controlled oscillator by reading the initialization and phase difference of the switching fabric, and maintaining the entire board. Represents a processor that performs functions and interprocess communication (IPC) functions Reference numeral 15 receives a reference clock from E1 or RS422 from the outside, receives a reference clock from two line cards, selects a normal clock among the reference clocks selected by the processor 14, and performs a DP-PLL function. And a network synchronizer for distributing a synchronized system clock to each line card.

Referring to Figures 2 and 3 attached to the configuration of the switch / network device of the asynchronous transfer mode (ATM) switch according to the present invention configured as described above are as follows.

First, the power supply unit 13 receives power from the external power supply through the back board and supplies power to each block. Here, the power supply unit 13 uses a fuse to prevent a short circuit, a power filter to remove hot insertion noise, and a power supply 13 to the injector / ejector and the front panel to be used as a board removal monitoring and reset signal. A push button switch is also used to monitor DC 5V and 3.3V for normal operation using a Dual Voltage Supervisor.

In the power-on state, the synchronizer unit 15 receives the reference clock redundantly from the outside by E1 or RS422, receives the reference clock from two line cards, and controls the reference clock in response to the control of the processor 14. It selects normal reference clock, performs DP-PLL function with internal voltage controlled oscillator, and distributes synchronized system clock to each line card.

Next, the switch unit 11 switches the ATM cell in response to the transmitted address, data, and control signal. The switching capacity is 5Gb / s, and it has eight input / output ports for matching through a line card and a direct backboard. Each input / output port consists of twelve 100MHz signals.

In addition, the board controller 12 is implemented with an FPGA, generates various control signals necessary to control the switch unit 11, controls the switch unit 11, and monitors and synchronizes a received clock of the network synchronizer unit 15. It performs functions such as selecting a reference clock for clock, clock division and system clock retiming, matching with the processor 14 and collecting alarm signals.

In addition, the processor 14 uses the MPC860 module to control the initialization of the switching fabric, to read the phase difference to control the reference voltage of the voltage controlled oscillator in the network unit 15, and to perform the maintenance function of the entire board. In other words, it performs interprocess communication (IPC) function.

2 is a diagram illustrating an embodiment of the network synchronizer of FIG. 1.

As shown in the drawing, a reference clock is dually received from the outside through E1 and RS422, a reference clock is received from a line card, a reference clock is selected according to an input control signal, and the selected reference clock is controlled by the board controller. A reference clock receiver 21 for transmitting to (12), a digital / analog converter 22 for converting the digital control voltage level output from the board controller 12 into an analog control voltage level corresponding thereto, and the digital / A voltage controlled oscillator 23 whose oscillation frequency changes in response to the analog control voltage output from the analog converter 22, and a clock distributor 24 for distributing the output clock of the voltage controlled oscillator 23 to the line card; It is composed of

The network synchronizer 15 configured in this manner first receives the reference clock in a redundant manner from the outside in the reference clock receiving unit 21 through E1 and RS422. Here, the E1 clock is received through the E1 Framer, Transformer, and 8.192Mhz Oscillator, and the RS422 match is received using an RS-422 receiver with a 2.048Mhz clock. In addition, according to the line card type, the board controller receives 1.398Mhz, which divides 1.024Mhz, 1.544Mhz, 2.048Mhz, 19.44Mhz, and 34.368Mhz from 16, and divides 2.148Mhz and 44.746Mhz from the line card through Pseudo ECL 4 Line Receiver. Send to (12).

The board controller 12 for the network synchronizer performs a reference clock selection, a division of the selected reference clock, a division of the voltage controlled oscillator 23 clock, a phase difference detection function, and the processor 14 to read the phase difference. To generate an interrupt. In addition, in order to control the control voltage level of the voltage controlled oscillator 23, 16-bit parallel data is received from the processor 14, converted into serial, and transmitted to the digital-to-analog converter 22.

The digital-to-analog converter 22 is a serial 16-bit digital-to-analog converter, which converts an input digital control voltage level into a corresponding analog control voltage level and applies it to the voltage controlled oscillator 23.

The voltage controlled oscillator 23 is an oven voltage controlled crystal oscillator having a center frequency of 19.44Mhz, and changes an oscillation frequency by an applied analog voltage control signal, and its output is a clock divider. Entered by (24).

The clock distributor 24 is composed of a clock buffer and a pseudo ECL 4 Line Driver for distributing 19.44Mhz, which is the output of the voltage controlled oscillator 23, to distribute the reference clock to the board controller 12 and the line card. do.

For the DP-PLL network function, the processor 14 controls the board controller 12 to implement a reference clock selection and a loop filter of the PLL as a program.

3 is a block diagram illustrating an embodiment of a board controller of FIG. 1.

As shown therein, the processor matching unit 31 generates a reference clock selection control signal by matching with the processor 14, transmits an input phase error to the processor 14, and processes an interrupt. And a reference clock selector 32 for selecting and outputting a specific reference clock from among reference clocks input in response to the selection signal output from the processor matching unit 31, and output from the processor matching unit 31. A redundant clock monitor and selector 33 which digitally monitors the redundant clock output from the reference clock selector 32 according to a control signal to determine whether it is normal and selects one, and outputs the selected reference clock; A reference clock divider 34 for dividing the reference clock output from the redundant clock monitor and selector 33 at 1 kHz and 19.4 provided at the voltage controlled oscillator 23; Phase error of the oscillation clock divider 35 for dividing and outputting the 4 MHz clock at 1 kHz and the 1 kHz clock output from the reference clock divider 34 and the oscillation clock divider 35 is detected and the interrupt is detected. It is composed of a phase difference detector 36 to be delivered to the processor matching section 31.

The board controller 12 configured as described above first selects a specific reference clock from among the reference clocks provided by the reference clock receiving unit 21 in response to the selection signal generated from the processor matching unit 31 in the reference clock selecting unit 32. The selected reference clock is transmitted to the redundant clock monitoring and selection unit 33.

The redundant clock monitor and selector 33 digitally monitors the selected redundant clock to determine whether it is normal, selects one, and transfers the selected reference clock to the reference clock divider 34.

The reference clock divider 34 divides the clock at 1 kHz so that the phase difference detector 36 at the rear stage detects the phase difference, and provides the divided clock to the phase difference detector 36.

The processor matching unit 31 matches the processor 14 to generate a reference clock selection control signal, and transmits a phase error transmitted from the phase difference detection unit 36 to the processor 14, and interrupts. It also performs processing functions.

Next, the oscillation clock divider 35 divides the 19.44Mhz clock provided by the voltage controlled oscillator 23 into 1 kHz to provide the phase difference detector 36 so that the phase difference detector 36 can detect the phase difference. .

The phase difference detector 36 detects a phase error of each 1 KHz received from the reference clock divider 34 and the oscillation clock divider 35, and transmits the phase error to the processor matching unit 34 with an interrupt.

Phase error data is transmitted to the processor 14 through the processor matching unit 34, and the processor 14 implements a loop filter using an algorithm implemented by a program. According to the algorithm to implement, PLL characteristics such as primary and secondary systems are transferred, and voltage control oscillation control value, which is digital data, is calculated, and the control voltage is output through the serial 16-bit digital-to-analog converter 22, which is then voltage controlled. It is applied to the oscillator 23 to control the output phase and frequency. The DP-PLL can implement low bands of less than 10Hz, which are difficult to implement as devices, and can implement various filters and add functions.

It is possible to filter phase noise such as jitter and wander included in the reference clock, and implement functions such as free-run and holdover. Holdover is a type of PLL operation that uses the output phase information stored in the memory to maintain the output phase before the loss when the input reference clock is lost. This function prevents abrupt changes in output frequency and phase due to the failure of the reference clock. Free-run refers to a function of providing a clock regardless of providing a reference clock, and the frequency accuracy and stability at the time of holdover can be realized by applying a constant control voltage of the voltage-controlled oscillator used without change. Use a voltage controlled oscillator that complies with the applicable standard.

According to the present invention described above, the ATM switch or the router device can be implemented by integrating the switch board without implementing the network function in a separate circuit pack, and can be implemented in the existing switch board, it is possible to reduce the type of circuit pack It is inexpensive and easy to implement the device for the synchronization device.

Claims (3)

In a switch / network device of an asynchronous transfer mode (ATM) exchange, A shared buffer switch unit for switching ATM cells; A board control unit for generating various control signals necessary for controlling the switch unit, generating a reception clock monitoring and synchronization reference clock selection signal for synchronizing the network synchronization unit to be described later, matching the processor to be described later, and collecting an alarm signal; It is connected to the board control unit, and controls the initialization of the switching fabric, reads the phase difference to control the reference voltage of the voltage controlled oscillator, and the overall board maintenance function and the upper processor and interprocess communication (IPC) function A processor to perform; Receives a reference clock from E1 or RS422 from the outside, receives a reference clock from two line cards, selects a normal clock among the reference clocks selected by the processor, and distributes a synchronized system clock to each line card. A manipulator to perform; Switch / network device of the asynchronous transfer mode (ATM) exchange, characterized in that it comprises a power supply for supplying the necessary power to the switch unit, the board control unit, the processor, the network unit to receive power from the power supply from the back board . The method of claim 1, wherein the manipulator unit, A reference clock receiver for receiving a reference clock redundantly from the outside through E1 and RS422, receiving a reference clock from a line card, selecting a reference clock according to an input control signal, and transmitting the selected reference clock to the board controller. Wow; A digital / analog converter for converting a digital control voltage level output from the board controller to an analog control voltage level corresponding thereto; A voltage controlled oscillator for changing an oscillation frequency corresponding to an analog control voltage output from the digital / analog converter; And a clock divider for distributing the output clock of the voltage controlled oscillator and supplying the output clock to the line card. According to claim 1 or 2, wherein the board control unit, A processor matching unit for generating a reference clock selection control signal by matching with the processor, transmitting a phase error to the processor, and processing an interrupt; A reference clock selection unit which selects and outputs a specific reference clock from among reference clocks input in response to a selection signal output from the processor matching unit; A redundant clock monitor and selector for digitally monitoring a redundant clock output from the reference clock selector according to a control signal output from the processor matching unit to determine whether it is normal and outputting the selected reference clock; ; A reference clock divider which divides and provides a reference clock outputted from the redundant clock monitor and selector at 1 kHz; An oscillation clock divider for dividing and outputting a 19.44Mhz clock provided at the voltage controlled oscillator at 1 kHz; Switch of the asynchronous transfer mode (ATM) switch characterized in that it comprises a phase difference detector for detecting the phase error of the 1Khz clock output from the reference clock divider and the oscillation clock divider, respectively, and transmits the interrupt to the processor matching unit. Synchronous device.