KR0173055B1 - Local timing generator - Google Patents

Abstract

The present invention relates to a local timing generating device of an Asynchronous Transfer Mode (ATM) exchange, wherein a clock signal synchronized with a reference clock signal selected by selecting one of two reference clock signals inputted from a network synchronous device is selected. It is generated by PLL (Phase Locked Loop) and generates its own clock signal even when the reference clock signal is lost due to the failure of the reference clock signal. By generating its own clock signal independently at the first stage and receiving the clock signal independently generated at the other stage as the reference clock signal, the clock is generated while maintaining the synchronous state between the mutual clock signals by the PLL by the cascade connection. Two times configured to be distributed to the unit switch device, various subscriber matching devices, and the control device Even when both of the input reference clock and a fault may cause the internal clock signal is not required to use many types of different timing generation unit has economical effect.

Description

Local timing generator

1 is a configuration diagram of an embodiment of a local timing generator according to the present invention.

* Explanation of symbols for main parts of the drawings

10: first clock selector 20: first clock generator

30: module clock and module clock cell synchronization generator

40: module clock and module clock cell synchronization divider

50: second clock selector 60: second clock generator

70: subscriber clock generator 80: subscriber clock distributor

90: matching clock and matching clock cell synchronization generator

100: matching clock and matching clock cell synchronization divider

The present invention relates to a local timing generator of an Asynchronous Transfer Mode (ATM) exchange.

The ATM exchanger generates the basic clock signal used by the exchange itself by the network synchronizer based on the synchronization clock signal input through the external communication network and supplies the reference clock signal for application in the central switch unit and the unit switch unit. A local timing signal, which is an internal use clock signal synchronized with the reference clock signal, is generated and used by the local timing generator.

The conventional local timing generator has a problem in that it is necessary to use several different timing generators in order to maintain a synchronous state in generating clock signals having different speeds required by various devices of an ATM exchanger.

Accordingly, the present invention has been made to solve the above-mentioned problems, and selects one line of two line reference clock signals inputted from a network synchronization device and generates clock locked signals (PLLs) in synchronization with the selected reference clock signal. Generated by the synchronous clock signal, and generates its own clock signal even when the reference clock signal is lost due to the failure of the reference clock signal. It generates its own clock signal and receives the clock signal generated independently from the other stage as the reference clock signal, and generates the clock while maintaining the synchronous state between the clock signals by the PLL by the cascade connection. And a local timing generator for distributing the matching device to the control device. Never.

In order to achieve the above object, the present invention includes a first clock selecting means for selectively outputting a plurality of input clocks to the outside in accordance with a clock state signal input from the outside and a failure state signal of the input clock; First clock generating means for outputting a clock signal synchronized with the clock signal inputted from the first clock selecting means; The clock signal inputted from the first clock generating means is divided into a predetermined first division value to output a divided module clock, and the divided module clock is divided into a predetermined second division value to synchronize module clock cells. Generating module clock and module clock cell synchronization generating means; Module clock and module clock cell synchronization distributing means for distributing module clock and module clock cell synchronization inputted from said module clock and module clock cell synchronization generating means to a predetermined first signal level; If the input clock signal is not transmitted through the first clock selecting means or if the input clock signal transmitted from the first clock selecting means is disturbed, the module clock transmitted from the module clock and the module clock cell synchronization generating means is changed. Second clock selecting means for selecting and outputting the input clock signal transmitted from the first clock selecting means when the normal input clock signal is transmitted from the first clock selecting means; Second clock generating means for outputting a clock signal synchronized with the clock signal inputted from the second clock selecting means; Subscriber clock generation means for dividing the clock signal inputted from the second clock generation means into a predetermined third division value and outputting the divided subscriber clock; Subscriber clock distribution means for distributing a subscriber clock input from said subscriber clock generation means to a predetermined second signal level; The clock signal inputted from the first clock generating means is divided into a predetermined fourth divided value to output a divided matched clock, and the divided matched clock is divided into a predetermined fifth divided value to perform matched clock cell synchronization. Generated matching clock and matching clock cell synchronization generating means; And a matching clock and matching clock cell synchronization distributing means for distributing the matching clock and the matching clock cell synchronization inputted from the matching clock and matching cell synchronization generating means to a predetermined third signal level and outputting them to the outside.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

1 is a configuration diagram of a local timing generator according to an exemplary embodiment of the present invention, which includes a first clock selector 10, a first clock generator 20, a module clock and a module clock cell synchronization generator 30. ), The module clock and module clock cell synchronization divider 40, the second clock selector 50, the second clock generator 60, the subscriber clock generator 70, and the subscriber clock divider 80, a matching clock and matching clock cell synchronization generating unit 90, and a matching clock and matching clock cell synchronization distributing unit 100 are provided.

The local timing generator of the present invention has a feature of generating a clock signal having two different speeds and distributing timing signals having three different speeds.

The operation of the local timing generator according to the present invention having the structure as described above will be described in detail.

The first clock selector 10 uses an synchronous input reference clock selector (Patent Application No. 94-33628, filed December 10, 1994) as a clock selector with an ATM speed of 23.4747 (155.520 x 8/53) MHz. A first input reference clock signal and a second input reference clock signal are input from a network synchronizer inside the switch, a redundant input clock signal is input from another redundant local timing generator, and three clock state signals of the clock signals are input. The input reference clock signal inputted from the network synchronizer based on the status signal generated by the function of monitoring a fault state of the input clock signal and the input clock status signal, and then the input reference clock signal input from the network synchronizer. If both lines are faulty, one external clock clock signal is received by receiving three external reference clock signals, which allows the user to select the ground signal that is in contact with the ground plane. To select.

The first clock generator 20 connects the reference clock signal selected by the first clock selector 10 to the reference clock input terminal as a reference clock signal, and connects the clock signal generated from the voltage controlled crystal oscillator to the comparison clock input terminal. The output of the phase and frequency comparator, the phase and frequency comparator to compare the phase and frequency as input, and the loop filter to transfer the control voltage to the voltage controlled crystal oscillator, and the center frequency is 164.323 ( Generates a synchronized clock signal of 155.520 x 56/53) MHz.

The module clock MCLK and the module clock cell synchronization (MCS) generator 30 may have a duty cycle of 50:50 provided in the clock signal input from the first clock generator 20. A pulse form having a size of one cycle of the module clock is divided by dividing the circuit by dividing circuit (Patent Application No. 94-34026, filing date: December 13, 1994) to output the module clock divided by seven. Generates and outputs module clock cell synchronization.

The module clock and module clock cell synchronization divider 40 connects the output of the module clock and the module clock cell synchronization generator 30 to an input terminal, and the module clock and the module clock at the ECL (Emitter-Coupled Logic) 100K differential signal level. The module clock cell synchronization is distributed and output to the outside.

The second clock selector 50 monitors whether an error occurs in the input clock signal transmitted through the first clock selector 10, or a failure occurs, or the input clock signal is transmitted from the first clock selector 10. If not, the module clock and the module clock transferred from the module clock cell synchronization generator 30 are selected and output to the second clock generator 60. If the second clock selector 50 receives a normal input clock signal from which the failure does not occur from the first clock selector 10, the second clock selector 50 selects an input clock transmitted from the first clock selector 10 to generate a second clock. Output to the clock generator 60.

Here, a circuit for monitoring the normality of the input clock signal was used by Motorola's ECL element MC10198. The operating characteristics of this monitoring circuit are as follows.

The external clock of the ECL signal level sent from the first clock selector 10 is connected to the trigger input terminal of the MC10198 device, and a pulse having a predetermined size according to R (Resistor) and C (Capacitor) time constants set in advance by a trigger signal. By using the operation characteristic that generates, the output terminal is kept high when the external clock is continuously inputted in the normal state, and if the input clock signal is not input for longer than R, C time constant The output terminal of the MC10198 device having a characteristic of transitioning to a self low state is used as an external clock monitoring circuit.

In addition, the clock selection uses an ECL device MC100E171 multiplexer (registered trademark), and the operation thereof is as follows.

An external clock sent from the first clock selector 10 and a module clock sent from the module clock cell synchronization generator 30 are connected to an input terminal of the multiplexer. The external clock monitoring signal is connected to the selection signal terminal of the multiplexer to select an external clock or a module clock.

The second clock generator 60 connects the reference clock signal selected by the second clock selector 50 to the reference clock input terminal and divides the clock signal by 7 minutes. The second clock generator 60 uses the clock signal generated from the voltage controlled crystal oscillator as a reference. It is connected to the input of the comparison clock and inputs the output of phase and frequency comparator and phase and frequency comparator to compare phase and frequency between two clocks. The voltage generates a synchronized clock signal having a center frequency of 155.520 MHz.

The subscriber clock UCLK generation unit 70 divides the clock signal inputted from the second clock generation unit 60 into eight divisions, and generates the eighth divided division clock clock UCLK.

The subscriber clock distributor 80 distributes the subscriber clock input from the subscriber clock generator 70 to the ECL 100K differential signal level.

The matching clock ICLK and the matching clock cell synchronizing generator 90 are connected to an input terminal of an output clock signal of the first clock generator 20 so that the matching clock IC and the matching clock are divided into eight. It divides and generates a matching clock cell synchronization in the form of a pulse having a size of one period of the matching clock.

The matched clock and matched clock cell sync distributor 100 distributes the matched clock and matched clock cell sync inputted from the matched clock and matched cell sync generator 90 at the ECL 100K differential signal level.

In one embodiment of the present invention, the phase and frequency comparators used in the first clock generator 20 and the second clock generator 60 are BSDIs, which are application specific integrated circuits (ASICs), and a high speed operational operational amplifier (PLC). The OPA37IC (OP AMP), a loop filter circuit by a resistor, and a capacitor are implemented using a 100E111 100K ECL integrated circuit for timing signal distribution such as the module clock and the module clock cell synchronization divider 40.

As described above, in the redundant input clock generator, the present invention generates a self-clocked signal even when the two-line input reference clocks fail. There is an economical effect of not having to use many different types of timing generators.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

Claims (7)

First clock selecting means for selectively outputting a plurality of input clocks externally input according to a clock state signal input from an external device and a fault state signal of an input clock; First clock generating means for outputting a clock signal synchronized with the clock signal inputted from the first clock selecting means; The clock signal inputted from the first clock generating means is divided into a predetermined first division value to output a divided module clock, and the divided module clock is divided into a predetermined second division value to synchronize module clock cells. Generating module clock and module clock cell synchronization generating means; Module clock and module clock cell synchronization distributing means for distributing module clock and module clock cell synchronization inputted from said module clock and module clock cell synchronization generating means to a predetermined first signal level; When the input clock signal is not transmitted through the first clock selecting means or when an input clock signal transmitted from the first clock selecting means is disturbed, the module clock transmitted from the mod clock and the module clock cell synchronization generating means is changed. Second clock selecting means for selecting and outputting the input clock signal transmitted from the first clock selecting means when the normal input clock signal is transmitted from the first clock selecting means; Second clock generating means for outputting a clock signal synchronized with the clock signal inputted from the second clock selecting means; Subscriber clock generation means for dividing the clock signal inputted from the second clock generation means into a predetermined third division value and outputting the divided subscriber clock; Subscriber clock distribution means for distributing a subscriber clock input from said subscriber clock generation means to a predetermined second signal level; The clock signal inputted from the first clock generating means is divided into a predetermined fourth divided value to output a divided matched clock, and the divided matched clock is divided into a predetermined fifth divided value to perform matched clock cell synchronization. Generated matching clock and matching clock cell synchronization generating means; And a matching clock and matching clock cell synchronization distributing means for distributing the matching clock and the matching clock cell synchronization inputted from the matching clock and matching cell synchronization generating means to a predetermined third signal level and outputting them externally. . 2. The apparatus of claim 1, wherein the first clock selecting means receives a first input reference clock signal and a second input reference clock signal from an external network synchronizer, and receives a redundant input clock from another externally duplicated local timing generator. The input reference clock signal input from the network synchronizer is preferentially selected according to a status signal generated by a function of receiving a signal and monitoring a fault state of the input clock signal and three clock status signals input from the outside, and the network If both lines of the input reference clock signal inputted from the synchronous device are in a fault state, it is configured to receive a three-line external reference clock signal for selecting a ground signal in contact with the ground plane and select a clock signal of one line. Local timing generator. The local timing generator according to claim 1, wherein the first and second clock generating means are configured by using a phase locked loop (PLL), respectively. The method of claim 1, wherein the module clock and the module clock cell synchronization generating means comprises a seventh division circuit having a duty cycle of 50:50 provided therein with a clock signal input from the first clock generating means. A local timing generator comprising: outputting a seven-divided module clock by seven divisions, and further dividing the seven-divided module clocks by 64 to generate a pulse of a module clock cell having a size of one cycle of the module clock. . 2. The method of claim 1, wherein the module clock and module clock cell synchronization distributing means comprises: ECL (Emitter-Coupled Logic) 100K differential between the module clock and the module clock cell synchronization inputted from the module clock and module clock cell synchronization generating means; (differential) Local timing generator, characterized in that configured to be output to the external distribution. 2. The subscriber clock generating means according to claim 1, wherein the subscriber clock generating means divides the clock signal inputted from the second clock generating means into eight divided clocks and outputs an eight divided clock. A local timing generating device, characterized in that configured to distribute the subscriber clock inputted from the generating means to the ECL 100K differential signal level. The matching clock and matching clock cell synchronization generating means divides the clock signal inputted from the first clock generating means into eight divisions, outputs a matching clock divided by eight, and divides the matching clock into 56 divisions. And a matching clock cell synchronization in a pulse form having a size of one matching clock cycle.