KR950015086B1 - Synchronous multiple transmission unit - Google Patents

Abstract

The synchronous mode multiplexing transmission device comprises: first and second network node interface units for performing a bidirectional 1+1 auto protection switching mode; a dependent signal processing unit for performing a signal mapping, a multiplexing/demultiplexing and a demapping and transmitting it to an external DS3 line; first and second high speed multiplexing units for performing a 1+1 switching mode; a system timing generating unit for generating a clock and a timing required by a system; and a system control unit for supplying a man machine interface for an operator.

Description

Synchronous multiplexer

1 is a point-to-point network diagram for explaining the present invention.

2 is a block diagram of an entire SDH applied synchronous multiplexer according to the present invention.

3 is a timing diagram according to the present invention.

4 is a structural diagram of a signal bus according to the present invention.

5 is a configuration diagram of a slave signal processing unit according to the present invention.

* Explanation of symbols for main parts of the drawings

1,4: Network node interface 2,3: High speed multiple part

5: System timing generator 6: Subordinate signal processor.

7: System control part a, b: STM-N signal

c: DSn signal

According to the present invention, asynchronous digital signal level mapping and multiplexing are performed after interfacing 1.544 Mb / s (DS1N), 2.048 Mb / s (DS1E), and 44.736 Mb / s (DS3) signals. ) Transmits STM-N (155.5Mb / s × N, N = 1,4,16) signal and transmits optically, DS1N, DS1E, DS3 signal through demultiplexing and history process by receiving STM-N optical signal The present invention relates to a synchronous multi-transmission apparatus for converting a digital transmission.

In general, the asynchronous multiplexing method is set up for use in a stage before pursuing the synchronization of the network, and it is inefficient in signal control and circuit configuration due to the compensation between the asynchronous input signal rates and the sequential level multiplexing in the high-level multiplexing. There is a surface, which is a problem that the unnecessary signals must go through when the input signals are synchronized.

Accordingly, the present invention devised to solve the above problems is unnecessary and efficient, economical, such as not only to replace the existing non-air multiplexing equipment, but also to cope with future transmission capacity expansion, The purpose of the present invention is to provide a SDH-applied synchronous multi-transmitter capable of constructing an in-transmission system.

In order to achieve the above object, the present invention, by receiving the STM-N optical signal from the optical path, optical / pre-conversion, clock and signal regeneration, descrambling, re-ramming, demultiplexing, SOH extraction and processing and connecting the AUG signal Generates Section Over Head (SOH), performs STM-N framing, multiplexing, scrambling, optical transmission, and duplicates to perform bidirectional 1 + 1 auto-protection switching (APS) using SOH. 1, the second network node interface means, connected to the external DS1 line, and receives the DS1E signal DS1N signal and slave signal processing means for transmitting to the external DS3 line in signal imaginary and multiplexing / de-demultiplexing and history, connected to the dependent signal processing means Maps and multiplexes and inputs one AUG signal from the first and second network node interface means to demultiplex and history to connect with the DS3 signal processor / slow multiplexer, and the AU pointer System generation, VC32 signal generation processing and VC32 POH generation processing, the first and second high speed multiple means of module switching and duplication to perform 1 + 1 switching, generating and supplying the clock and timing required for the system, and synchronizing the system clock The system uses extraction timing from external synchronous timing, STM-1 signal or slave signal as a circle, and it can also oscillate by its own oscillator internally, and performs 1 + 1 switching method with redundant operation unit and spare unit. A processor and external maintenance (OAM) for controlling and monitoring the entire system, including timing generating means and three processors, respectively, which control and monitor the first and second network node interface means and the system timing generating means. It is equipped with a processor for processing data communication functions with a network, a slave signal processing unit, and a CPU that controls and monitors high-speed multi-weeks. Communication is characterized by using a polling scheme using the DPRAM, and provided with a system control means for providing a man-machine interface for the operator.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

1 is a point-to-point network configuration applied to a transmission network between stations in order to explain the present invention, in which both devices 10 multiplex DSn (n = 1,3) signals to STM-N signals between two devices through an optical path. Point-to-point transmission

In the present invention, when the STM-N signal is STM-1 (155.52 Mb / s), the device receives the DS1N, DS1E, and DS3 dependent signals to generate the 155.520 Mb / s STM-1 signal. Up to 84 DS1N signals, up to 63 DS1E signals, and up to three 44.736 Mb / s (DS3) signals can be accommodated, and these signals can be mixed.

2 is an overall block diagram of a synchronous multi-transmitter according to the present invention, FIG. 3 is a timing diagram according to the present invention, and FIG. 4 is a signal bus structure diagram according to the present invention. 2 and 3 represent a high speed multiplexer, 5 represents a system timing generator, 6 represents a slave signal processor, and 7 represents a system controller.

In FIG. 2, the STM-1 optical signal a is input to the network node interface unit 1, and after optical / electric conversion, the clock recovery and the signal are extracted, and the extracted signal is subjected to risk ranking and reframe. Handle section overhead (SOH). The processed result is classified into alarm or performance information and transmitted to the system controller 7 through the micro interface e. DCC (D1-D3) data in the SOH is transmitted to the system control unit 7 via a separate link. The clock recovered from the optical signal is sent to the system timing generator 5. After the SOH is processed from the STM-1 signal, it is delivered to the high speed multiplexer 2, 3 via the J bus (Fig. 4a) containing the multiplexed AUG signal. The STM-1 signal interface (b) is for 1 + 1 line protection switching, and the STM-1 optical signal input to b2 passes through the same operation as 1 in the protection node network node interface (4). 4a) to the high speed multiple parts 2 and 3, respectively. In the high speed multiplexer 2, the J bus is received from the network node interfaces 1 and 4, respectively, one is selected, an AUG signal is received therefrom, and demultiplexed into an AU signal, the AU pointer is processed, and the VC32 signal is extracted and extracted. Handles VC32 path overhead (POH). As a result of processing, it is classified into alarm and performance information and transmitted to the system control unit 7 through the microprocessor interface e. The VC32 signal extracted from the high speed multiplexer 2 is transmitted to the slave signal processing unit 6 through the f-bus (Fig. 4B) including the TUG21 signal when the signal multiplexed inside the VC32 is a DS1 signal. If is transmitted to the dependent signal processing unit 6 via the g-bus (Fig. 4c) containing the C32 signal. The high speed multiplier 3 performs the same operation as the high speed multiplier 2 for protection switching. The slave signal processor 6 demultiplexes the TUG21 signal by selecting one of the respective f-buses from the high speed multiplexers 2 and 3, and then performs VC11 or VC12 through four TU11 or three TU12 pointer processes (interpretation). Extract the signal. The VC11 POH is processed from the VC11 signal, and then the DS1N signal is extracted and converted into a line signal form (c1) through a reverse synchronization process. After processing the VC12 POH from the VC12 signal, the reverse synchronization process to extract the DS1E signal is converted to the line signal form (c1) and transmitted. However, when the C32 signal is input through the g-bus from the slave signal processor 6, the DS3 signal is extracted through the reverse synchronization process, and then converted into a line signal form. The slave signal processing unit 6 is composed of seven modules in the case of TUG21 and performs 6: 1 module switching by accommodating 16 VC11 or 12 VC12 per module. The C32 consists of six modules, processing one DS3 signal per module, and performing 1 + 1 switching. Information generated by the slave signal processor 6 and performance related information are transmitted to the system controller 7 via an e-bus. The operation in the demultiplexing direction (STM-1 → AUG → AU3 → VC32 → TUG21 → VC11 / 12 → DS1N / SDiE, STM-1 → AUG → AU3 → VC32 → C32 → DS3) in the present invention has been described above. The following describes the operation in the multiplexing direction (DS1 → VC11 / VC12 → TUG21 → VC32 → AU3 → AUG → STM-1, DS3 → C32 → VC32 → AU3 → AUG → STM-1) which is the inverse of the above process.

In FIG. 3, c is a DSn (n = 1,3) signal and a received DSn (C2) is input to the slave signal processor 6 in the form of a line signal. When c2 is DS1, the slave signal processing unit 6 interfaces and extracts data, maps them to C11 / C12, which are synchronous container signals, and then inserts the corresponding POH to form VC11 / VC12 signals. A TU11 / TU12 signal is added to the VC11 / VC12 signal to form a TU11 / TU12 signal, and four for TU11 are multiplexed for three TU12 to form a TUG21 signal and loaded on the up f-bus (Fig. 4b). To (2,3). The clock timing i3 necessary for performing the above operation is supplied from the system timing generator 5. When the c2 interface signal is DS3, the slave signal processing unit 6 maps the synchronous container signal C32 through a data conversion and synchronization process, and then transfers it to the g number and transfers it to the high-speed multiplexing (2, 3). The clock timing i necessary for performing the above operation is supplied from the system timing generator 5. In the case of 2 and 3, in the case of f-bus, 7 pieces of TUG data are multiplexed to insert VC32 POH to form a VC32 signal. The generated AU pointer is multiplexed to form an AUG signal, which is loaded on the J bus (a in FIG. 4) and delivered to the respective network node interfaces 1 and 4. The network node interface unit 1, 4 selects one J bus from each J bus and inserts AUG data into the STM-1 frame together with the generated SOH. Thereafter, the signal is transmitted as the signals a2 and b1 through the scrambling and all / optical conversion. DCC channel data in the SOH is supplied from the system controller through one link. As shown in FIG. 8D, the system controller 7 outputs DCC channel data by the Tj clock supplied from the network node interfaces 1 and 4. As shown in FIG. In addition, by using the E1, E2 channel of the SOH processed by the network node interface (1, 4) can provide a haptic interface.

The system timing generation section 5 selects appropriately from the external synchronization signal d, the extraction timing from the STM-1 line (h), and the extraction timing from the DSn line, selects it as the reference timing, and synchronizes it with T0 and T1 in FIG. System clock timing such as T2 is generated and supplied to each unit. It also has its own built-in oscillator for system maintenance due to loss of reference timing, so it is used as system clock when all reference timing is lost. The system timing section 5 which performs this operation is composed of redundancy so that the system clock timing supply is not disrupted. The system controller 7 incorporates a CPU and a memory to perform supervisory control of each part. Each part performs information transfer through e-bus and controls the transfer operation. In addition, 1 (4) transmits and receives DCC channel information through one link. The system control unit 7 performs device control operation and monitoring by an operator from the outside through the man machine interface p.

3 is a timing diagram according to the present invention.

In the figure, T0 has a speed of 155.52 MHz and is used for 155.52 Mb / s signal processing, which is an STM-1 signal rate. T1 is obtained by dividing T0 by 51.84MHz in three divisions and is used to obtain VC32 signal processing rate of 50.112Mb / s. Td is obtained by dividing T0 at 19.44MHz by 8 minutes and is used for 19.44Mb / s processing of AUG parallel signal rate. Ta is an STM-1 frame clock of 8KHz and is the reference for system timing. Tb is obtained by 9 parts of Ta. STM-1's SOH byte clock has a speed of 72KHz and is used as the timing for SOH processing. Tc is obtained by counting Tb four times on the basis of Ta, and is a timing indicating an AU pointer position, and is used as a timing for AU pointer processing.

5 is a configuration diagram of the slave signal processing unit, and shows the configuration of the slave signal processing unit 6 in the case of DS1 signal reception (FIG. 5A) and in the case of DS3 signal reception (FIG. 5B).

As shown in FIG. 5A, when the DS1 signal processing units 21-1 to 21-3 are configured, the circuit of the low speed multiplexing units 22, 23, and 24 can accommodate up to 28 bidirectional DS1 signals C1 and C2. And a low-speed module switching unit 25 for performing module switching, a DS1E multiple unit 22, 23, 24 for receiving a DS1E signal with 12 DS1E signal capacities or 16 DS1N signal capacities, and a DS1N for receiving DS1N signals. It is divided into multiple sections 22, 23, and 24, and connects up to 12-16 DS1 signals to signal-differentiate and multiplexes with C1-VC1-TU1-TUG21, and four TUG21s from the high-speed multiple section (2,3). It is a low speed that connects signals and demultiplexes and history them to TUG21-TU1-VC1, maps DS1N and DS1E signals to VC1, generates path overhead (POH), terminates VC1 signal generation, and generates TU pointer. DS1 signal interface and signal consisting of central parts 22, 23, and 24, which perform circuit and module switching of the low-speed multiple parts at 7: 1 and N: 1 (N = 2,4 or 6). Perform call processing.

In the case of the DS3 signal processing units 31-1 to 31-3, as shown in FIG. 5B, one bipolar DS3 signal is connected to map to a C32 signal, and one from the high-speed multiple units 2 and 3 is used. DS32 signal portion (32,33) for receiving the C32 signal and performing the function of history as a bipolar DS3 signal, and DS3 signal portion for distributing the DS3 signal from the DS3 C) line to the operation (32) and the reserve (33), respectively. It consists of a distribution 34 to perform the 1 + 1 switching method having one operation and one spare, and performs the DS3 signal interface and signal processing.

Therefore, the present invention as described above can not only replace the existing asynchronous multiplexing equipment, but also can easily cope with the future expansion of the transmission capacity has the effect of configuring an efficient and economical transmission system.

Claims (5)

Receives STM-N optical signals from optical paths, converts photo / pre, clocks and signals, descrambles, re-ramps, demultiplexes, extracts and processes SOH, and connects AUG signals to connect section overheads (SOH). First and second network node interface means (1) for performing STM-N framing, multiplexing, scrambling, and optical transmission, and performing duplexing to perform bidirectional 1 + 1 automatic protection switching (APS) using SOH. 4) slave signal processing means (6) connected to an external DS1 line for receiving a DS1E signal / DS1N signal and transmitting the signal to the external DS3 line in signal thought, multiplexing / demultiplexing and history; Connected and connected to the DS3 signal processor / slow multiplexer by demultiplexing and history by inputting one AUG signal from the first and second network node interface means (1,4). VC32 signal generation VC32 POH generation process, the first and second high-speed multiple means (2, 3) for module switching and duplication to perform 1 + 1 switching, generating and supplying the clock and timing required for the system, System timing generating means that uses extraction timing from synchronous timing STM-1 signal or dependent signal, and can also generate self-oscillation by self-oscillator, and performs 1 + 1 switching method with redundant operation part and spare part. 5) It is composed of three processors, each of which is responsible for the control and monitoring of the entire system, including the control and monitoring of the first and second network node interface means (1, 4) and the system timing protection means (5), respectively. A processor for processing data communication between the processor and an external maintenance network (OAM), and a slave signal processor and a CPU that controls and monitors the high-speed multi-end are embedded. Use yonghan polling method, synchronous multiplex transmission apparatus comprising a system control means (7) to provide a man-machine interface for the operator. 2. The slave signal processing means according to claim 1, further comprising: It has low-speed module switching means 25 for accommodating up to 28 bidirectional DS1 signals and performs low-speed multiple circuit and module switching, and has 12 DS1E signal capacities or 16 DS1N signal capacities. Demultiplexing and inverting four TUG21 signals from the first and second fast multiplexing means (2,3), mapping DS1N and DS1E signals to VC1, generating a path overhead (POH), and terminating VC1 signal generation And the first to third low speed multiple means 22, 23, and 24 performing the TU pointer generation processing function to perform circuit and module switching of the first to third low speed multiple means 22 to 24. And a DS1 signal processing means (21). 2. The slave signal processing means according to claim 1, further comprising: The first and second signal mapping means 32 which connect one bipolar DS3 signal to map to a C32 signal and receive one signal from the first and second high speed multiple means 2 and 3 and invert it into a bipolar DS3 signal. 33. A synchronous multiplexing device, comprising: DS3 signal processing means (31) comprising DS3 signal distribution means (34) for distributing DS3 signals over a DS3C line. 2. The slave signal processing means according to claim 1, further comprising: A synchronous multiplexing device characterized by comprising one DS2 signal processing means (21) and one DS2 signal processing means (31). The synchronous multiplexing device according to claim 2, wherein the DS1 signal processing means (21) comprises one DS2N multiple means and one DS / 2 E multiple means.