KR20010073791A - Method for forming contact hall of semiconductor device - Google Patents

Abstract

PURPOSE: A method for forming a contact hole of a semiconductor device is provided to minimize silicon loss in a hole forming through a damascene process and easily form a barrier metal layer by omitting a sputtering etching. CONSTITUTION: Ar, CHF3, O2 and CH2F2 gases are used to simultaneously etch the first insulation film(16) and the second insulation film(17) under a condition of a middle plasma density in a dual frequency reactive ion etching type equipment. An inter-layer dielectric(14) and a cap insulating film(13) as well as the first and second insulation films(16,17) are selectively etched in a peripheral region. A bitline contact hole(19) is formed on the peripheral region to expose a semiconductor substrate(11) and a gate electrode(12). Here, a press condition is 30-100mT in pressure, 1300 to 2500W in upper power, 800 to 1500W in lower power, and 2-6sccm in flow of CH2F2gas. O2 gas can be left out. According to the use of CH2F2 gas, an etching selectivity with respect with silicon is increased and silicon loss is minimized. A profile of the bitline contact hole becomes narrower it goes from a bottom to an upper part, to have a slant section, so that a barrier metal layer can be deposited without conducting a sputtering etching.

Description

Method for forming contact hole of semiconductor device {METHOD FOR FORMING CONTACT HALL OF SEMICONDUCTOR DEVICE}

The present invention relates to a method for forming a contact hole in a semiconductor device, and more particularly, to a method for forming a contact hole in a semiconductor device to minimize silicon loss in hole formation through a damascene process and to easily form a subsequent barrier metal layer. will be.

A method of forming a contact hole through a damascene process of a conventional semiconductor device will be described in detail with reference to the accompanying drawings.

First, FIG. 1A is a cross-sectional view of a cell region and a peripheral region XX in a semiconductor memory. As shown in FIG. 1A, a gate oxide film (not shown) and a gate electrode 2 are formed on a semiconductor substrate 1 on which a cell region and a peripheral region are defined. And patterning the gates on which the cap insulating films 3 are stacked so as to be spaced apart from each other, and then planarizing the interlayer insulating films 4 on the upper surface thereof, and selectively etching the interlayer insulating films 4 so that the inter-gate spacing regions of the cell regions are exposed. The conductive material is then filled in to form the plug 5.

1B is a cross-sectional view of the cell region in which the process of FIG. 1A is performed, and a cross-sectional view of the cell region in the YY direction and a XX direction cross section of the peripheral region. The first and second insulating layers 6 and 7 are sequentially formed on the upper surface of the C, and the second insulating layer 7 is selectively etched through photolithography to form the bit line pattern 8.

1C is a cross-sectional view illustrating a subsequent process of FIG. 1B. As shown in FIG. 1C, a low pressure, middle plasma density in a dual frequency reactive ion etching type device is formed on a resultant product on which the bit line pattern 8 is formed. ), The cell region etches the first and second insulating layers 6 and 7 simultaneously using Ar, CHF ₃ and O ₂ gas, and the peripheral region is not only the first and second insulating layers 6 and 7 By selectively etching the interlayer insulating film 4 and the cap insulating film 3, the bit line contact hole 9 is formed to expose the plug 5 in the cell region and the semiconductor substrate 1 and the gate electrode 2 in the peripheral region. Form.

FIG. 1D is a cross-sectional view illustrating a subsequent process of FIG. 1C, and as shown therein, sputtering and etching the upper edge of the bit line contact hole 9 to facilitate deposition of a subsequent barrier metal layer (not shown). Make it happen.

However, the above-described method for forming a contact hole in a semiconductor device as described above uses a bit line contact hole to expose plugs, semiconductor substrates, and gate electrodes having different depths formed by etching lower insulating layers through Ar, CHF _3, and O ₂ gases. Since simultaneous etching is required, the silicon oxides are increased and the profile of the bit line contact hole is bent as shown in FIG. When the coating thickness of the photoresist film is made thin for easy exposure, there is a problem that the etching selectivity of the photoresist film and the etching target film is lowered due to the sputtering etching.

The present invention has been devised to solve the above-mentioned problems, and an object of the present invention is to easily form a subsequent barrier metal layer while minimizing silicon loss in hole formation through a damascene process and omitting sputter etching. The present invention provides a method for forming a contact hole in a semiconductor device.

1A to 1D are cross-sectional views showing a method for forming a contact hole in a conventional semiconductor device.

Figures 2a to 2c is a side view of a hand showing an embodiment of the present invention.

*** Explanation of symbols for main parts of drawing ***

11: semiconductor substrate 12: gate electrode

13: Cap insulation film 14: Interlayer insulation film

15: Plug 16, 17: first and second insulating film

18: bit line pattern 19: bit line contact hole

In order to achieve the object of the present invention, a method for forming a contact hole in a semiconductor device may include: forming a gate oxide film, a gate electrode, and a cap insulating film on a semiconductor substrate having a cell region and a peripheral region spaced apart from each other; Forming an interlayer insulating film over the entire surface to planarize it; Etching the interlayer insulating film formed in the inter-gate spacing region of the cell region and then filling the conductive material to form a plug; Forming a bit line pattern by sequentially forming first and second insulating layers on the upper surface of the resultant formed product of the plug and then selectively etching the second insulating layer through photolithography; The first and second insulating films, the interlayer insulating films, and the caps of the cell region and the peripheral region using Ar, CHF ₃ , O _2, and CH ₂ F ₂ gases in a dual frequency reactive ion etching type apparatus on the resultant formed bit line pattern. And selectively etching the insulating film to form a bit line contact hole so that the plug, the semiconductor substrate, and the gate electrode are simultaneously exposed.

A method of forming a contact hole in a semiconductor device according to the present invention as described above will be described in detail with reference to the accompanying drawings.

First, FIG. 2A is a cross-sectional view of a cell region and a peripheral region XX of a semiconductor memory. As shown in FIG. 2A, a gate oxide film (not shown) and a gate electrode 12 are disposed on a semiconductor substrate 11 on which a cell region and a peripheral region are defined. And patterning the gates on which the cap insulating films 13 are stacked so as to be spaced apart from each other, and then planarizing the interlayer insulating films 14 on the upper surface thereof, and selectively etching the interlayer insulating films 14 to expose the inter-gate spacing regions of the cell regions. Next, the conductive material is filled to form the plug 15.

FIG. 2B is a cross-sectional view of the cell region in which the process of FIG. 2A is performed, and a cross-sectional view of the cell region in the YY direction and a cross-sectional view in the XX direction of the peripheral region. The first and second insulating layers 16 and 17 are sequentially formed on the upper surface of the C, and the second insulating layer 17 is selectively etched through photolithography to form the bit line pattern 18.

FIG. 2C is a cross-sectional view illustrating the subsequent process of FIG. 2B. As shown in FIG. 2C, a low pressure, middle plasma density in a dual frequency reactive ion etching type device is formed on a resultant formed with the bit line pattern 18. ) As a condition, Ar, CHF ₃ , O ₂ and CH ₂ F ₂ gas are used to simultaneously etch the first and second insulating films 16 and 17 in the cell region, and the first and second insulating films 16 and 16 in the peripheral region. By selectively etching not only the interlayer insulating film 14 and the cap insulating film 13, but also the bit line contacts to expose the plug 15 of the cell region and the semiconductor substrate 11 and the gate electrode 12 of the peripheral region. The hole 19 is formed. At this time, the process conditions were set at a pressure of 30 to 100 [mT], an upper power of 1300 to 2500 [W], a lower power of 800 to 1500 [W], and a flow rate of CH ₂ F ₂ gas at 2 to 6 [SCCM], and ₂ gases can be excluded and the use of CH ₂ F ₂ gas increases the etch selectivity for silicon, minimizing the loss of silicon, and inclining the profile of the bitline contact hole gradually narrowing from top to bottom. Having a cross section allows deposition of subsequent barrier metal layers without sputter etching.

As described above, the method for forming a contact hole in a semiconductor device according to the present invention minimizes silicon loss by using CH ₂ F ₂ gas and increases the selectivity to the photoresist due to an increase in carbon content, thereby increasing the coating thickness of the photoresist. It is possible to minimize the vertical profile in the nitride film applied as the cap insulating film of the gate, thereby maximizing the bottom area of the bit line contact hole, thereby reducing the contact resistance value on the gate showing the sharpest characteristic change. In addition, as the bit line contact hole having the inclined profile is formed, the sputter etching for the barrier metal layer may be omitted, thereby contributing to the process simplification.

Claims (2)

A step of patterning a gate oxide film, a gate electrode and a cap insulating film stacked on the semiconductor substrate having a cell region and a peripheral region spaced apart from each other, and then forming an interlayer insulating film on the upper surface thereof to planarize it; Etching the interlayer insulating film formed in the inter-gate spacing region of the cell region and then filling the conductive material to form a plug; Forming a bit line pattern by sequentially forming first and second insulating layers on the upper surface of the resultant formed product of the plug and then selectively etching the second insulating layer through photolithography; The first and second insulating films, the interlayer insulating films, and the caps of the cell region and the peripheral region using Ar, CHF ₃ , O _2, and CH ₂ F ₂ gases in a dual frequency reactive ion etching type apparatus on the resultant formed bit line pattern. And forming a bit line contact hole so that the plug, the semiconductor substrate, and the gate electrode are simultaneously exposed by selectively etching the insulating film. According to claim 1, wherein the etching process conditions for forming the bit line contact hole pressure 30 ~ 100 [mT], upper power 1300 ~ 2500 [W], lower power 800 ~ 1500 [W] and CH ₂ F ₂ gas A contact hole forming method for a semiconductor device, characterized by setting a flow rate of 2 to 6 [SCCM].