KR20050005972A - Method of manufacturing semiconductor device - Google Patents
Method of manufacturing semiconductor device Download PDFInfo
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- KR20050005972A KR20050005972A KR1020030045970A KR20030045970A KR20050005972A KR 20050005972 A KR20050005972 A KR 20050005972A KR 1020030045970 A KR1020030045970 A KR 1020030045970A KR 20030045970 A KR20030045970 A KR 20030045970A KR 20050005972 A KR20050005972 A KR 20050005972A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000011229 interlayer Substances 0.000 claims abstract description 53
- 229910052751 metal Inorganic materials 0.000 claims abstract description 51
- 239000002184 metal Substances 0.000 claims abstract description 51
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 32
- 239000003990 capacitor Substances 0.000 claims abstract description 30
- 238000000034 method Methods 0.000 claims abstract description 28
- 238000005530 etching Methods 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 239000010410 layer Substances 0.000 claims description 75
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical group [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 25
- 238000000151 deposition Methods 0.000 claims description 13
- 238000005229 chemical vapour deposition Methods 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 claims description 3
- 230000002708 enhancing effect Effects 0.000 abstract 1
- 239000012212 insulator Substances 0.000 abstract 1
- 229910052718 tin Inorganic materials 0.000 description 23
- 239000007789 gas Substances 0.000 description 16
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 239000002313 adhesive film Substances 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910020286 SiOxNy Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 229910015844 BCl3 Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조방법에 관한 것으로, 보다 상세하게는, 싱글 다마신(Single Damascene)공정을 이용한 엠아이엠(MIM : Metal-Insulator-Metal) 캐패시터를 적용시킨 반도체 소자의 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device using a metal-insulator-metal (MIM) capacitor using a single damascene process. .
아날로그 캐패시터(analog capacitor)는 통상적으로 피아이피(PIP : Poly-Insulator-Poly) 구조가 아닌 엠아이엠 구조로 형성된다. 이것은 알.에프(RF) 대역의 아날로그 회로에 사용되는 캐패시터는 높은 Q(Quality Factor) 값이 요구되는데, 이를 실현하기 위해선 전극 재료로서 공핍(Depletion)이 거의 없고, 저항이 낮은 금속 전극의 사용이 필수적이기 때문이다.Analog capacitors (analog capacitors) are typically formed of an MIM structure, not a PIP (Poly-Insulator-Poly) structure. This is because capacitors used in analog circuits in RF bands require high Q (Quality Factor) values. To achieve this, there is almost no depletion as an electrode material and a low resistance metal electrode is used. Because it is essential.
엠아이엠 캐패시터의 구조는, PMD(Pre Metal Dielectric)공정 완료후에 하부 플레이트 금속 증착, 유전체막 증착 및 상부 플레이트 금속 증착을 하고, 캐패시터를 정의하기 위해 상부 플레이트 금속 식각, 유전체막 식각 및 하부 플레이트 금속 식각의 공정을 진행한 후, 산화막 계통의 층간절연막을 형성하고 캐패시터로 인한 단차 완화를 위한 화학적 기계적 연마(Chemcal Mechanical Polishing ; 이하, 씨엠피) 공정으로 상기 층간절연막을 식각하여 평탄화한다.The structure of the MIM capacitor is the bottom plate metal deposition, the dielectric film deposition and the top plate metal deposition after the completion of the Pre Metal Dielectric (PMD) process, the top plate metal etching, the dielectric film etching and the bottom plate metal etching to define the capacitor After the process of, to form an interlayer insulating film of the oxide film system and the planarization by etching the interlayer insulating film by chemical mechanical polishing (CMP) process to reduce the step by the capacitor.
그러나, 상기 씨엠피 공정시 단차가 높은 부분의 층간절연막 두께가 얇아지게 되어 비아 콘택 공정시 하부층의 손상될 수 있어 반도체소자의 특성 및 신뢰성을 저하시키고 반도체소자의 수율을 저하시키는 문제점이 있다.However, in the CMP process, the thickness of the interlayer insulating film having a high step becomes thin, which may damage the lower layer during the via contact process, thereby degrading the characteristics and reliability of the semiconductor device and reducing the yield of the semiconductor device.
종래의 반도체 소자의 제조방법에 대하여 도 1a 내지 도 1e를 참조하여 간략하게 설명하면 다음과 같다.A method of manufacturing a conventional semiconductor device will be briefly described with reference to FIGS. 1A to 1E as follows.
종래의 반도체 소자의 제조방법은, 도 1a에 도시된 바와 같이, 먼저, 반도체 기판(1) 상에 제1층간절연막(3), 하부금속배선층(11), 유전체막 형성용 절연막(13) 및 상부전극층(15)을 차례로 형성한다. 그런다음, 상기 상부전극층(15) 상에 공지의 포토리소그라피 공정을 통해서 캐패시터 상부전극 형성 영역(미도시)을 한정하는 제1감광막패턴(25)을 형성한다.In the conventional method for manufacturing a semiconductor device, as shown in FIG. 1A, first, the first interlayer insulating film 3, the lower metal wiring layer 11, the dielectric film forming insulating film 13, and the like on the semiconductor substrate 1. The upper electrode layers 15 are sequentially formed. Then, a first photoresist pattern 25 defining a capacitor upper electrode formation region (not shown) is formed on the upper electrode layer 15 through a known photolithography process.
여기서, 하부금속배선층(11)은 제 1 Ti/TiN 막(5), 알루미늄막(7) 및 제 2 Ti/TiN 막(9)의 적층구조로 형성된 것이다.이 때, 상기 제 1 Ti/TiN 막(5)에서 Ti는 접착막이고, TiN은 확산방지막이다. 그리고, 상기 알루미늄막(7)은 저항이 낮은 것으로 인해 실질적인 전기 신호를 전달하도록 기능하며, 상기 제 2 Ti/TiN 막(9)에서 Ti는 접착막이고, TiN은 반사방지막이다. 그리고, 상기 유전체막 형성용 절연막(13)은 유전상수(dielectric constant)가 높은 산화막, 예컨데, 실리콘옥시나이트라이드(SiOxNy)막, 실리콘나이트라이드(Si3N4)막, 또는, PECVD(Plasma Enhanced Chemical Vapor Deposition) 방식에 의해 형성된 산화막으로 이루어진다. 또한, 상기 상부전극층(15)은 상기 하부금속배선층(11)과 마찬가지로 Ti/TiN/Al/Ti/TiN 의 구조로 되어있는 것이 일반적이며, Al,W,Ti,TiN 또는 이들의 조합을 이용하여 구성한다. 아울러, 도시되지는 않았으나, 상기 제1층간절연막(3)에는 콘택플러그가 존재하고, 이 콘택플러그는 상기 하부금속배선층(11)과 콘택된 것으로 이해될 수 있다.Here, the lower metal wiring layer 11 is formed of a laminated structure of the first Ti / TiN film 5, the aluminum film 7, and the second Ti / TiN film 9. In this case, the first Ti / TiN In the film 5, Ti is an adhesive film and TiN is a diffusion barrier film. In addition, the aluminum film 7 functions to transmit a substantial electrical signal due to low resistance. In the second Ti / TiN film 9, Ti is an adhesive film and TiN is an antireflection film. The dielectric film forming insulating layer 13 may be an oxide film having a high dielectric constant, for example, a silicon oxynitride (SiOxNy) film, a silicon nitride (Si3N4) film, or PECVD (Plasma Enhanced Chemical Vapor Deposition). It is made of an oxide film formed by the method. In addition, the upper electrode layer 15 has a structure of Ti / TiN / Al / Ti / TiN similarly to the lower metal wiring layer 11, and may be formed using Al, W, Ti, TiN, or a combination thereof. Configure. Although not shown, a contact plug may be present in the first interlayer insulating layer 3, and the contact plug may be in contact with the lower metal wiring layer 11.
그리고 나서, 도 1b에 도시된 바와 같이, 상기 제1감광막패턴을 마스크로 하여 상기 상부전극층과 유전체막 형성용 절연막을 식각하여 상부전극(16)과 유전체막(14)을 형성한다. 이때, 상기 상부전극층의 식각은 Cl2, BCl3 및 N2 가스의 혼합 가스로 이루어진 활성화 플라즈마를 이용한 건식 식각으로 수행한다. 이어서, 상기 유전체막 형성용 절연막의 식각은 "C" 및 "F"를 주성분으로 하는 가스, 예컨데, CF4, C2F6, C4F8, C5F8 등과 같은 CxFy 가스를 이용하여 활성화시킨 플라즈마로 수행한다. 또한, 상기 유전체막 형성용 절연막의 식각시 O2, Ar 및 CHF3 등의 가스가 추가 되기도 한다. 아울러, 상기 캐패시터 상부전극(16)의 형성을 위한 공정은 상부전극층의 식각, 제1감광막패턴의 제거, 유전체막 형성용 절연막의 식각 순으로 진행하거나, 또는, 상부전극층의 식각, 유전체막 형성용 절연막의 식각, 제1감광막패턴의 제거 순으로 진행한다.1B, the upper electrode layer and the dielectric film forming insulating layer are etched using the first photoresist pattern as a mask to form the upper electrode 16 and the dielectric film 14. At this time, the etching of the upper electrode layer is performed by dry etching using an activated plasma consisting of a mixed gas of Cl2, BCl3 and N2 gas. Subsequently, the dielectric film forming insulating film is etched using a plasma activated by using a gas mainly composed of "C" and "F", for example, a CxFy gas such as CF4, C2F6, C4F8, C5F8, and the like. In addition, when etching the dielectric film forming insulating film, gases such as O 2, Ar, and CHF 3 may be added. In addition, the process for forming the capacitor upper electrode 16 may proceed in the order of etching the upper electrode layer, removing the first photoresist layer pattern, and etching of the dielectric layer forming insulating film, or etching the upper electrode layer or forming the dielectric film. The etching proceeds in order of etching the insulating film and removing the first photosensitive film pattern.
계속해서, 상기 결과물 상에 캐패시터 하부전극 형성 영역(미도시)을 한정하는 제2감광막패턴(27)을 형성한다.Subsequently, a second photoresist pattern 27 defining a capacitor lower electrode formation region (not shown) is formed on the resultant.
다음으로, 도 1c에 도시된 바와 같이, 상기 제2감광막패턴에 의해 덮히지 않고 노출된 상기 하부금속배선층을 Cl2, BCl3 및 N2의 혼합 가스로 이루어진 활성화 플라즈마로 건식 식각하여, 캐패시터 하부전극(11a)을 형성하고, 상기 제2감광막패턴을 제거한다. 도 1c에서, 미설명된 도면부호 11b는 하부금속배선을 나타낸다.Next, as shown in FIG. 1C, the lower metal wiring layer exposed without being covered by the second photoresist layer pattern is dry-etched with an activated plasma made of a mixed gas of Cl 2, BCl 3, and N 2, so that the capacitor lower electrode 11a is exposed. ) And the second photoresist pattern is removed. In FIG. 1C, reference numeral 11b, which is not described, indicates a lower metal wiring.
그런 다음, 도 1d에 도시된 바와 같이, 상기 결과물 상에 제2층간절연막(17)을 형성하고, 씨엠피 하여 상기 제2층간절연막(17) 상부의 표면 굴곡(Surface Topology)을 평탄화시킨다. 여기서, 상기 제2층간절연막(17)은 이중막 구조를 이용하며, 이중에서 하부층으로는 PE-TEOS(17a)를 이용하고, 상부층으로는 저유전율 물질인 SOG 또는 FOX (17b)을 이용한다. 상기 PE-TEOS(17a) 대신 FOX를 사용할 수도 있다.Next, as shown in FIG. 1D, a second interlayer insulating film 17 is formed on the resultant material, and CMP is used to planarize surface topography of the upper part of the second interlayer insulating film 17. In this case, the second interlayer insulating layer 17 uses a double layer structure, in which PE-TEOS 17a is used as a lower layer, and SOG or FOX 17b, which is a low dielectric constant material, is used as an upper layer. FOX may be used instead of the PE-TEOS 17a.
이어서, 도 1e에 도시된 바와 같이, 상기 제2층간절연막(17)상에 비아 홀 형성 영역(미도시)을 한정하는 제3감광막패턴(29)을 형성한다.Subsequently, as illustrated in FIG. 1E, a third photoresist layer pattern 29 defining a via hole formation region (not shown) is formed on the second interlayer insulating layer 17.
그리고, 도 1f에 도시된 바와 같이, 상기 제3감광막패턴을 마스크로 하여 상기 제2층간절연막의 소정 부분들을 선택적으로 식각하여 캐패시터 하부 및 상부전극(11a, 16)과 하부금속배선(11b)을 각각 노출시키는 비아 홀(19)들을 형성하고, 상기 제3감광막패턴을 제거한다. 이 때, 상기 제2층간절연막(17)의 식각은 CxFy 기체를 활성화 시킨 플라즈마로 건식 식각한다.As shown in FIG. 1F, predetermined portions of the second interlayer insulating layer are selectively etched using the third photoresist pattern as a mask to form the lower and upper electrodes 11a and 16 and the lower metal wiring 11b of the capacitor. Via holes 19 exposing each are formed, and the third photoresist pattern is removed. At this time, the etching of the second interlayer insulating layer 17 is dry etching using a plasma activated by the CxFy gas.
다음으로, 도 1g에 도시된 바와 같이, 상기 결과물 상에 CVD(Chemical Vapor Deposition) 방식을 이용하여 텅스텐(W)이나 구리(Cu) 등의 제1금속막(미도시)을 증착 시킨 다음, 상기 제1금속막을 씨엠피 하여 상기 비아 홀(19)들을 상기 제1금속막으로 매립시켜 하부금속배선(11b), 캐패시터 하부 및 상부전극(11a, 16)과 각각 콘택되는 비아 플러그(21)들을 형성한다. 그리고나서, 상기 제2층간절연막(17) 상에 제2금속막(미도시)의 증착 및 패터닝을 수행하여 각 비아 플러그(21)들을 통해 상기 하부금속배선(11b)과 캐패시터 하부 및 상부전극(11a, 16)과 전기적으로 콘택되는 상부금속배선(23)을 형성한다. 여기서, 상기 상부금속배선(23)들은 Ti/TiN/Al/Ti/TiN의 적층 구조로 형성한다.Next, as shown in Figure 1g, by depositing a first metal film (not shown), such as tungsten (W), copper (Cu) using the CVD (Chemical Vapor Deposition) method on the resultant, CMP of the first metal layer fills the via holes 19 with the first metal layer to form via plugs 21 contacting the lower metal wiring 11b, the capacitor lower portion, and the upper electrodes 11a and 16, respectively. do. Then, the second metal layer (not shown) is deposited and patterned on the second interlayer insulating layer 17 to pass through the lower metal wiring 11b and the capacitor lower and upper electrodes through the via plugs 21. Upper metal wirings 23 electrically contacting 11a and 16 are formed. Here, the upper metal wires 23 are formed in a stacked structure of Ti / TiN / Al / Ti / TiN.
그러나, 전술한 바와 같은 종래의 반도체 소자의 제조방법은 PMD 적용 후 형성하기 때문에 토폴로지(Topology)의 단차가 형성되며, 도 2에 도시된 바와 같이, 단차를 줄이기 위해 씨엠피 공정을 진행할 때, 상기 제2층간절연막의 상부층인 SOG 또는 FOX 가 노출되면서 리세스(Recess)되는 문제점이 발생된다. 왜냐하면, 상기 SOG 또는 FOX와 같은 물질은 다른 물질, 예컨대, 금속배선층간산화막(Inter Metal Dielectric Oxide : IMD Oxide) 이나 실리콘산화막(SiO2) 등에 비해 상대적으로 식각 속도가 빠르기 때문에 식각량의 조절이 어렵기 때문이다.However, since the conventional method of manufacturing a semiconductor device as described above is formed after the application of PMD, a step of topology is formed, and as shown in FIG. 2, when the CMP process is performed to reduce the step, Recession occurs when the SOG or FOX, which is the upper layer of the second interlayer insulating layer, is exposed. Because the material such as SOG or FOX has a relatively high etching rate compared to other materials, for example, Inter Metal Dielectric Oxide (IMD Oxide) or Silicon Oxide (SiO2), it is difficult to control the etching amount. Because.
또한, 상기 비아 홀 형성시 과소식각(Under Etch)을 방지하기 위해 과도식각(Over Etch)으로 진행하게 되는데, 상기 유전체막과 상부전극의 두께 합 만큼 영역간에 단차를 갖게 되는 바, 예컨데, 상기 하부전극을 식각 타켓으로 맞춘 경우에는, 상기 상부전극이 손상됨은 물론 심한 경우에는 상기 상부전극이 식각 노출되거나, 반대로, 상기상부전극을 식각 타켓으로 맞출 경우에는 하부전극 측에 과소식각에 의한 오픈 불량이 생길 수 있는 문제점이 발생된다.In addition, when the via hole is formed, over etching is performed in order to prevent under etching, and thus a step is provided between regions as much as the sum of the thicknesses of the dielectric film and the upper electrode. When the electrode is aligned with an etch target, the upper electrode is not only damaged, but in severe cases, the upper electrode is etched or, on the contrary, when the upper electrode is aligned with an etch target, open defects due to under-etching are caused on the lower electrode side. Problems may arise.
따라서, 본 발명은 상기와 같은 문제점을 해결하기 위하여 안출된 것으로서, 싱글 다마신 공정을 이용하여 엠아이엠 캐패시터의 구조를 개선함으로써 반도체 소자의 성능을 향상시킬 수 있는 반도체 소자의 제조방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above problems, to provide a method for manufacturing a semiconductor device that can improve the performance of the semiconductor device by improving the structure of the M capacitor using a single damascene process. There is a purpose.
도 1a 내지 도 1g는 종래의 기술에 따른 반도체 소자의 제조방법을 설명하기 위한 공정 단면도.1A to 1G are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the related art.
도 2는 종래 기술의 문제점을 설명하기 위한 도면.2 is a view for explaining the problems of the prior art.
도 3a 내지 도 3h는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 공정 단면도.3A to 3H are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
-도면의 주요 부분에 대한 부호의 설명-Explanation of symbols on main parts of drawing
51 : 반도체기판 53 : 제1층간절연막51 semiconductor substrate 53 first interlayer insulating film
55 : 제 1 Ti/TiN 막 57 : 알루미늄막55 first Ti / TiN film 57 aluminum film
59 : 제 2 Ti/TiN 막 61a : 하부전극59 second Ti / TiN film 61a bottom electrode
61b : 하부금속배선 63 : 제2층간절연막61b: lower metal wiring 63: second interlayer insulating film
77 : 제1감광막패턴 65 : 트렌치77: first photosensitive film pattern 65: trench
67 : 유전체막 형성용 절연막 69 : 상부전극층67 dielectric film forming dielectric 69 upper electrode layer
68 : 유전체막 70 : 상부전극68 dielectric film 70 upper electrode
64 : 제3층간절연막 79 : 제2감광막패턴64: third interlayer insulating film 79: second photosensitive film pattern
71 : 비아 홀 73 : 비아 플러그71: via hole 73: via plug
75 : 상부금속배선75: upper metal wiring
상기와 같은 목적을 달성하기 위한 본 발명의 반도체 소자의 제조방법은, 반도체 기판 상에 각각의 하부전극 및 하부금속배선을 형성하는 단계; 상기 기판 전면에 제1층간절연막을 형성하는 단계; 상기 제1층간절연막 상에 캐패시터 영역을 한정하는 제1감광막패턴을 형성하는 단계; 상기 제1감광막패턴을 마스크로 하여 상기 제1층간절연막을 식각하여 트렌치를 형성하는 단계; 상기 제1감광막패턴을 제거하는 단계; 상기 결과물 상에 유전체막 형성용 절연막, 상부전극층을 차례로 증착 시키는 단계; 상기 상부전극층과 유전체막 형성용 절연막을 씨엠피 하여 상기 트렌치 내에 각각의 유전체막과 상부전극을 형성하는 단계; 상기 결과의 제1층간절연막 상에 제2층간절연막을 형성하는 단계; 상기 제2층간절연막 상에 비아 홀 형성 영역을 한정하는 제2감광막패턴을 형성하는 단계; 상기 제2감광막패턴을 마스크로 하여 상기 제2층간절연막과 제1층간절연막을 식각하여 하부금속배선, 캐패시터 하부 및 상부전극을 각각 노출시키는 비아 홀을 형성하는 단계; 상기 제2감광막패턴을 제거하는 단계; 상기 결과물 상에 CVD 방식으로 제1금속막을 증착 시키고, 씨엠피 하여 상기 비아홀들을 상기 제1금속막으로 매립시키는 비아 플러그들을 형성하는 단계; 및 상기 결과의 제2층간절연막 상에 상기 비아 플러그와 연결되는 상부금속배선을 형성하는 단계를 포함한다.The method of manufacturing a semiconductor device of the present invention for achieving the above object comprises the steps of forming each of the lower electrode and the lower metal wiring on the semiconductor substrate; Forming a first interlayer insulating film on the entire surface of the substrate; Forming a first photoresist pattern defining a capacitor region on the first interlayer insulating film; Etching the first interlayer dielectric layer using the first photoresist pattern as a mask to form a trench; Removing the first photoresist pattern; Sequentially depositing an insulating film for forming a dielectric film and an upper electrode layer on the resultant product; CMP of the upper electrode layer and the dielectric film forming insulating film to form respective dielectric films and upper electrodes in the trenches; Forming a second interlayer insulating film on the resultant first interlayer insulating film; Forming a second photoresist pattern on the second interlayer insulating film, the second photoresist pattern defining a via hole formation region; Etching the second interlayer insulating layer and the first interlayer insulating layer using the second photoresist pattern as a mask to form a via hole exposing a lower metal wiring, a capacitor lower portion, and an upper electrode, respectively; Removing the second photoresist pattern; Depositing a first metal film on the resultant by CVD and forming a via plug to fill the via holes with the first metal film by CMP; And forming an upper metal wiring connected to the via plug on the resultant second interlayer insulating film.
여기서, 상기 제1층간절연막의 식각시 CxFy 가스를 이용하여 활성화시킨 플라즈마로 수행하고, 상기 CxFy 가스는 CF4, CHF3, C2F6, C4F8 등의 "C" 및 "F" 의 조합으로 이루어진 가스를 사용하며, 여기에 O2, Ar, N2, H2 가스 또는 이들의 조합으로 된 가스를 추가하기도 한다. 그리고, 상기 유전체막 형성용 절연막을 증착 시키는 단계 및 상기 상부전극층을 증착 시키는 단계는, CVD 방식을 이용하여 증착시킨며, 상기 상부전극층은 Ti/TiN 구조로 증착 시킨다.Here, the etching of the first interlayer dielectric layer is performed using a plasma activated by using a CxFy gas, and the CxFy gas uses a gas composed of a combination of "C" and "F" such as CF4, CHF3, C2F6, and C4F8. In addition, a gas of O2, Ar, N2, H2 gas or a combination thereof may be added thereto. The depositing the insulating film for forming the dielectric film and the depositing the upper electrode layer may be deposited using a CVD method, and the upper electrode layer may be deposited in a Ti / TiN structure.
본 발명에 따르면, 싱글 다마신 공정을 이용하여 엠아이엠 캐패시터의 구조를 개선함으로써 반도체 소자의 성능을 향상시킬 수 있다.According to the present invention, it is possible to improve the performance of the semiconductor device by improving the structure of the M capacitor using a single damascene process.
(실시예)(Example)
이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 보다 상세하게 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 3a 내지 도 3h는 본 발명의 실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 각 공정별 단면도이다.3A to 3H are cross-sectional views of respective processes for describing a method of manufacturing a semiconductor device according to an embodiment of the present invention.
본 발명의 실시예에 따른 반도체 소자의 제조방법은, 도 3a에 도시된 바와 같이, 먼저, 반도체 기판(51) 상에 제1층간절연막(53)과 하부금속배선층(미도시)을 차례로 형성하고, 상기 하부금속배선층(미도시)을 패터닝하여 각각의 하부전극(61a) 및 하부금속배선(61b)을 형성한다. 그리고, 상기 결과의 구조물 상에 제2층간절연막(63)을 형성한다. 그런다음, 상기 제2층간절연막(63) 상에 공지의 포토리소그라피 공정을 통해서 캐패시터 형성 영역(미도시)을 한정하는 제1감광막패턴(77)을 형성한다.In the method of manufacturing a semiconductor device according to an embodiment of the present invention, as shown in FIG. 3A, first, a first interlayer insulating film 53 and a lower metal wiring layer (not shown) are sequentially formed on a semiconductor substrate 51. The lower metal wiring layer (not shown) is patterned to form respective lower electrodes 61a and lower metal wiring 61b. Then, a second interlayer insulating film 63 is formed on the resulting structure. Then, a first photoresist layer pattern 77 defining a capacitor formation region (not shown) is formed on the second interlayer insulating layer 63 through a known photolithography process.
이 때, 상기 하부전극(61a)은 제 1 Ti/TiN 막(55), 알루미늄막(57) 및 제 2 Ti/TiN 막(59) 적층구조로 이루어진다. 여기서, 상기 제 1 Ti/TiN 막(55)에서 Ti는 접착막이고, TiN은 확산방지막이다. 그리고, 상기 알루미늄막(57)은 저항이 낮은 것으로 인해 실질적인 전기 신호를 전달하도록 기능하며 상기 제 2 Ti/TiN 막(59)에서 Ti는 접착막이고, TiN은 반사방지막이다. 아울러, 도시되지는 않았으나, 상기 제1층간절연막(53)에는 콘택플러그가 존재하고, 이 콘택플러그는 상기 하부금속배선층(미도시)과 콘택된 것으로 이해될 수 있다.In this case, the lower electrode 61a has a stacked structure of the first Ti / TiN film 55, the aluminum film 57, and the second Ti / TiN film 59. Here, in the first Ti / TiN film 55, Ti is an adhesive film and TiN is a diffusion barrier film. In addition, the aluminum film 57 functions to transmit a substantial electrical signal due to low resistance. In the second Ti / TiN film 59, Ti is an adhesive film and TiN is an antireflection film. Although not shown, a contact plug may be present in the first interlayer insulating layer 53, and the contact plug may be in contact with the lower metal wiring layer (not shown).
그리고 나서, 도 3b에 도시된 바와 같이, 상기 제1감광막패턴을 마스크로 하여 상기 제2층간절연막(63)을 식각하여 트렌치(65)를 형성하고, 상기 제1감광막패턴을 제거한다. 이 때, 상기 제2층간절연막(63)의 식각 공정은 CxFy 가스를 이용하여 활성화시킨 플라즈마로 수행한다. 여기서, CxFy 는 CF4, CHF3, C2F6, C4F8, C5F8 등의 "C" 및 "F" 의 조합으로 이루어진 가스를 말하며 여기에 O2, Ar, N2, H2 가스 또는 이들의 조합으로 된 가스가 추가 되기도 한다. 그리고 상기 트렌치(65)는 후속공정으로 형성될 유전체막의 두께와 상부전극의 두께의 합과 같은 깊이(h)로 형성하고, 유전체막과 상부전극이 형성되는 영역과 같은 너비(w)로 형성한다. 이 때, h(Depth) < w(Width)가 된다.Then, as illustrated in FIG. 3B, the second interlayer insulating layer 63 is etched using the first photoresist pattern as a mask to form a trench 65, and the first photoresist pattern is removed. In this case, the etching process of the second interlayer dielectric layer 63 is performed by plasma activated using a CxFy gas. Here, CxFy refers to a gas consisting of a combination of "C" and "F", such as CF4, CHF3, C2F6, C4F8, C5F8, and may also be added to the gas O2, Ar, N2, H2 or a combination thereof. . The trench 65 is formed to have a depth h equal to the sum of the thickness of the dielectric film to be formed in a subsequent process and the thickness of the upper electrode, and the width w to be the same as the region where the dielectric film and the upper electrode are formed. . At this time, h (Depth) < w (Width).
다음으로, 도 3c에 도시된 바와 같이, 상기 결과물의 전체표면상부에 유전체막 형성용 절연막(67)을 증착 시킨다. 상기 유전체막 형성용 절연막(67)은 CVD 방식을 이용하여 증착 시킨다. 또한, 상기 유전체막 형성용 절연막(67)은 유전상수가 높은 실리콘옥시나이트라이드(SiOxNy)막, 실리콘나이트라이드(Si3N4)막, 또는, PECVD 방식에 의해 형성된 산화막으로 이루어진다.Next, as shown in FIG. 3C, an insulating film 67 for forming a dielectric film is deposited on the entire surface of the resultant product. The dielectric film forming insulating film 67 is deposited using a CVD method. The dielectric film forming insulating film 67 is formed of a silicon oxynitride (SiOxNy) film, a silicon nitride (Si3N4) film having a high dielectric constant, or an oxide film formed by PECVD.
이어서, 도 3d에 도시된 바와 같이, 상기 유전체막 형성용 절연막(67) 상부에 상부전극층(69)을 증착 시킨다. 상기 상부전극층(69)은 CVD 방식을 이용하여 증착 시킨다. 그리고 상기 상부전극층(69)은 Ti/TiN막 구조로 증착 시키는데, TiN을 증착하는 이유는 증착 방식의 특성이 상/하부 층 표면으로 부터 일정한 방향 및 속도로 증착이 진행되기 때문이다.Subsequently, as shown in FIG. 3D, an upper electrode layer 69 is deposited on the dielectric layer forming insulating layer 67. The upper electrode layer 69 is deposited using a CVD method. In addition, the upper electrode layer 69 is deposited in a Ti / TiN film structure. The reason for depositing TiN is that deposition is performed in a predetermined direction and speed from the upper and lower layer surfaces.
그런 다음, 도 3e에 도시된 바와 같이, 상기 상부 전극층과 상기 유전체막 형성용 절연막을 씨엠피 하여 상기 트렌치(65)내에 각각의 유전체막(68)과 상부전극(70)을 형성한다.Then, as shown in FIG. 3E, each of the dielectric film 68 and the upper electrode 70 is formed in the trench 65 by CMPing the upper electrode layer and the dielectric film forming insulating film.
그리고, 도 3f에 도시된 바와 같이, 상기 결과물 상부에 제3층간절연막(64)을 형성하고, 상기 제3층간절연막(64) 상에 비아 홀 형성 영역(미도시)을 한정하는 제2감광막패턴(79)을 형성한다.As shown in FIG. 3F, a second photoresist layer pattern is formed on the resultant layer, and a second photoresist layer pattern defining a via hole formation region (not shown) is formed on the third interlayer insulation layer 64. Form 79.
다음으로, 도 3g에 도시된 바와 같이, 상기 제2감광막패턴을 마스크로 하여 상기 제2층간절연막(63)과 제3층간절연막(64)을 식각하여 하부금속배선(61b), 캐패시터 하부 및 상부전극(61, 70)을 각각 노출시키는 비아 홀(71)들을 형성한다. 이 때, 상기 제2층간절연막(63)과 제3층간절연막(64)의 식각은 CxFy 기체를 활성화시킨 플라즈마로 건식 식각 한다. 그 다음, 상기 제2감광막패턴을 제거한다.Next, as shown in FIG. 3G, the second interlayer insulating layer 63 and the third interlayer insulating layer 64 are etched using the second photoresist pattern as a mask to form the lower metal wiring 61b, the lower and upper capacitors. Via holes 71 exposing the electrodes 61 and 70, respectively, are formed. At this time, the etching of the second interlayer insulating film 63 and the third interlayer insulating film 64 is dry etching by plasma activated CxFy gas. Then, the second photoresist pattern is removed.
그런 다음, 도 3h에 도시된 바와 같이, 상기 결과물 상에 CVD 방식을 이용하여 텅스텐(W)이나 구리(Cu) 등의 제1금속막(미도시)을 증착 시킨 다음, 상기 제1금속막을 씨엠피 하여 상기 비아 홀(71)들을 상기 제1금속막으로 매립시키는 상기 하부금속배선(61b), 캐패시터 하부 및 상부전극(61a, 70)과 각각 콘택되는 비아 플러그(73)들을 형성한다. 그리고 나서, 상기 제3층간절연막(64) 상에 제2금속막(미도시)의 증착 및 패터닝을 수행하여 각 비아 플러그(73)들을 통해 상기 하부금속배선(61b), 캐패시터 하부 및 상부전극(61a, 70)과 전기적으로 콘택되는 상부금속배선들(75)을 형성한다. 여기서, 상기 상부금속배선(75)은 Ti/TiN/Al/Ti/TiN의 적층 구조로 형성한다.Then, as shown in Figure 3h, by depositing a first metal film (not shown), such as tungsten (W), copper (Cu) on the resultant by using a CVD method, and then the first metal film The via plugs 73 may be formed to contact the lower metal wiring 61b, the capacitor lower part, and the upper electrodes 61a and 70 to fill the via holes 71 with the first metal layer. Then, the second metal layer (not shown) is deposited and patterned on the third interlayer insulating layer 64 to pass through the lower metal wiring 61b, the capacitor lower portion, and the upper electrode through the via plugs 73. Upper metal wirings 75 which are in electrical contact with 61a and 70 are formed. Here, the upper metal wiring 75 is formed in a stacked structure of Ti / TiN / Al / Ti / TiN.
상기와 같은 공정을 통해 형성되는 본 발명에 따른 반도체 소자는 싱글 다마신공정을 이용하여 형성한 엠아이엠 캐패시터를 적용시켜 씨엠피 마진(Margin)을 확보할 수 있고, 반도체 소자의 성능을 향상시킬 수 있다.The semiconductor device according to the present invention formed through the above process can secure a CMP margin by applying an M capacitor formed using a single damascene process, and can improve the performance of the semiconductor device. .
이상에서와 같이, 본 발명은 층간 절연막에 싱글 다마신 공정을 이용하여 엠아이엠 캐패시터를 형성함으로써, 종래의 하부금속배선 및 하부전극과 유전체막/상부전극 간의 단차로 인해 층간절연막을 씨엠피 하여 평탄화 시켜도 완전한 평탄화가 어려운 문제와, SOG나 FOX와 같은 저유전율 물질이 드러나면서 리세스(Recess)가 심화되는 문제를 개선시킬 수 있다.As described above, the present invention forms an M capacitor using a single damascene process in the interlayer insulating film, thereby planarizing the interlayer insulating film by CMP due to the conventional lower metal wiring and the step difference between the lower electrode and the dielectric film / upper electrode. This can improve the problem that complete planarization is difficult and the recession becomes more severe as low-k materials such as SOG and FOX are exposed.
또한, 기존의 유전체막의 건식 식각 중에는 바닥에 잔류물(residue)이 종종 생성되는데 이는 금속 배선 건식식각에서 잔류물이 장벽(barrier) 역할을 하여 그 프로파일(profile)을 따라감으로 해서 브릿지(bridge)가 발생될 수 있으나 본 발명의 엠아이엠 캐패시터 형성에서는 싱글 다마신 공정을 이용하여서 이러한 문제점도 해결함과 동시에 엠아이엠 캐패시터의 성능을 개선시킬 수 있다.In addition, during the dry etching of a conventional dielectric film, a residue is often generated at the bottom, which is a bridge in the metal wiring dry etching, as the residue serves as a barrier and follows its profile. However, in the formation of the M capacitor of the present invention, a single damascene process may be used to solve these problems and at the same time improve the performance of the M capacitor.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
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| KR100705257B1 (en) * | 2005-12-05 | 2007-04-09 | 동부일렉트로닉스 주식회사 | Semiconductor device and manufacturing method thereof |
| KR100712817B1 (en) * | 2005-12-29 | 2007-04-30 | 동부일렉트로닉스 주식회사 | Semiconductor device and fabricating method of thereof |
| KR100822179B1 (en) | 2006-12-27 | 2008-04-16 | 동부일렉트로닉스 주식회사 | Capacitor in semiconductor device and method of manufactruing the same |
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| KR100442863B1 (en) * | 2001-08-01 | 2004-08-02 | 삼성전자주식회사 | Method for fabricating semiconductor device having metal-insulator-metal capacitor and damascene wiring structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100705257B1 (en) * | 2005-12-05 | 2007-04-09 | 동부일렉트로닉스 주식회사 | Semiconductor device and manufacturing method thereof |
| US7723769B2 (en) | 2005-12-05 | 2010-05-25 | Dongbu Hitek Co., Ltd. | Capacitor device of a semiconductor |
| KR100712817B1 (en) * | 2005-12-29 | 2007-04-30 | 동부일렉트로닉스 주식회사 | Semiconductor device and fabricating method of thereof |
| KR100822179B1 (en) | 2006-12-27 | 2008-04-16 | 동부일렉트로닉스 주식회사 | Capacitor in semiconductor device and method of manufactruing the same |
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