KR20020002539A - Methof for manufacturing capacitor - Google Patents

Abstract

PURPOSE: A method for manufacturing a capacitor is provided to prevent a loss of a capacitor oxide layer and to guarantee sufficient capacitance, by using a stacked layer of the first anti-reflective coating(ARC), a polysilicon layer and the second ARC as an etch barrier in etching the capacitor oxide layer. CONSTITUTION: The capacitor oxide layer is formed on a semiconductor substrate(31). A hard mask layer composed of a three-layer structure the second layer of which is a silicon layer is formed on the capacitor oxide layer. The capacitor oxide layer is selectively etched to expose the surface of the semiconductor substrate by using the hard mask layer. The remaining hard mask layer is removed. A lower electrode(42), a dielectric layer(43) and an upper electrode(44) are sequentially formed on the resultant structure.

Description

Manufacturing method of a capacitor {METHOF FOR MANUFACTURING CAPACITOR}

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a capacitor using a polysilicon hard mask.

A general method of manufacturing a capacitor is to form a polysilicon plug, deposit a diffusion barrier nitride film and a capacitor oxide film, and then perform a capacitor mask / etch process to form a capacitor in a laminate or cylinder form. However, this method is unable to secure the charge capacity required by the device due to the decrease in the critical dimension (CD), the reduction in the thickness of the photoresist film, and thus the depth of etching as the degree of integration of the device increases.

Then, instead of the polysilicon lower electrode, a metal film lower electrode was introduced, which converted the capacitor plug material into the metal film.

Recently, methods for solving the insufficient charge capacity problem have been proposed.

1A to 1D are cross-sectional views illustrating a method of manufacturing a capacitor according to the prior art.

As shown in FIG. 1A, a bit line insulating film 13 is formed on a semiconductor substrate 11 on which a predetermined process including a word line (not shown), a bit line (not shown), and an impurity bonding layer 12 is completed. Thereafter, the bit line insulating layer 13 is selectively patterned to form a plug contact hole through which the impurity bonding layer is exposed.

Subsequently, polysilicon is deposited in the contact hole, and then a recess etch back process is performed to fill the contact hole by a predetermined depth to form a capacitor contact plug 14, and titanium / titanium on the contact plug 14. The diffusion barrier 15 is formed of a stacked structure of nitride or titanium silicide / titanium nitride.

Subsequently, an etch-resistant nitride film 16 is formed on the diffusion barrier 15 to prevent loss of the contact plug 14 at the time of etching the next capacitor oxide film, and then as a transient loss prevention layer during the etching process of the capacitor oxide film, the capacitor A USG film 17 having the same oxide film series but slower etching rate as the oxide film is deposited.

Subsequently, a PSG film 18 is deposited on the USG film 17 as a capacitor oxide, which is deposited at a low temperature with a relatively high etching rate, and then polysilicon 19 having a large etching selectivity with respect to the oxide film is deposited. Deposit with a hard mask.

In order to improve CD (Critical Dimension) margin, an oxynitride or Si-rich nitride is deposited on the polysilicon 19 as an anti-reflection film 20.

As shown in FIG. 1B, the PSG film 18 and the USG film 17 may be formed by performing a mask and etching process for the lower electrode of the capacitor using the anti-reflection film 20 and the polysilicon 19 for hard mask. ), All of the anti-reflection film 20 is lost, and about 30% of the loss of the polysilicon 19 for the hard mask is generated, and the etch-resistant nitride film 16 remains.

As shown in FIG. 1C, when dry etching is performed to remove the remaining polysilicon 19a for the hard mask, the top and sidewalls of the polysilicon 19a are lower than that of the PSG film 18, which is a capacitor oxide film under the residual polysilicon 19a. Partially lost PSG film 18a is generated, and then the etch preventing nitride film 16 is etched to connect only the capacitor contact plug 12 and the lower electrode, and then the upper and sidewalls of the partly lost PSG film 18a. The loss of is further increased so that the height of the capacitor oxide film is reduced to 2/3 of the initial value.

As shown in FIG. 1D, such reduction in the capacitor height then reduces the charge capacity of the capacitor consisting of the lower electrode 21 / insulator 22 / upper electrode 23 to two thirds of the value required by the device. To deteriorate the device characteristics.

The present invention has been made to solve the problems of the prior art, and an object thereof is to provide a method for producing a capacitor suitable for securing a sufficient capacitor capacity by preventing the loss of the capacitor oxide film.

1a to 1d is a cross-sectional view of the manufacturing process of the capacitor according to the prior art,

Figures 2a to 2e is a cross-sectional view of the manufacturing process of the capacitor according to the embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

31 semiconductor substrate 32 impurity bonding layer

33: bit line insulating film 34: capacitor contact plug

35a / 35b: diffusion barrier 36: etching prevention nitride

37: USG film 38: PSG film

39: first antireflection film 40: polysilicon for hard mask

41: second antireflection film 42: lower electrode

43 dielectric layer 43 upper electrode

A method of manufacturing a capacitor of the present invention for achieving the above object comprises a first step of forming a capacitor oxide film on a semiconductor substrate having a predetermined process; A second step of forming a hard mask layer having a triple structure on the capacitor oxide film, wherein the second layer is made of a silicon film; Selectively etching the capacitor oxide layer using the hard mask layer to expose a surface of the semiconductor substrate; A fourth step of removing the hard mask layer remaining after the third step; And a fifth step of sequentially forming the lower electrode, the dielectric layer, and the upper electrode on the resultant of the fourth step, wherein the method of manufacturing the capacitor of the present invention is for preventing etching on a semiconductor substrate on which a predetermined process is completed. A first step of sequentially forming a nitride film and a capacitor oxide film; A second step of sequentially forming a hard mask and an anti-reflection film on the capacitor oxide film; A third step of selectively etching the capacitor oxide film using the anti-reflection film and the hard mask as an etching mask; A fourth step of etching the etching preventing nitride film using the hard mask remaining after the third step; Forming a lower electrode conductive layer on the resultant of the fourth step and then applying a photosensitive film to prevent deformation of the conductive layer for the lower electrode during subsequent chemical mechanical polishing; And forming a lower electrode by chemically mechanically polishing the conductive layer for lower electrode of the fifth step, and etching the hard mask remaining after the fourth step by using the corrosion phenomenon of the chemical mechanical polishing. Characterized in that made.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

2A to 2D are cross-sectional views illustrating a method of manufacturing a capacitor according to an embodiment of the present invention.

As shown in FIG. 2A, after the bit line insulating layer 33 is formed on the semiconductor substrate 31 on which the predetermined process including the impurity bonding layer 32 is completed, the bit line insulating layer 33 is selectively patterned. A plug contact hole for exposing the impurity bonding layer 32 is formed.

Subsequently, polysilicon is deposited in the contact hole, and then a recess etch back process is performed to fill the contact hole by a predetermined depth to form a capacitor contact plug 34, and titanium / titanium on the contact plug 34. A diffusion barrier film formed of a stacked structure of nitrides 35a / 35b or titanium silicide / titanium nitride is formed.

Subsequently, Si _x N _y (x: y = 1: 1 to 5: 1) is used as the etch-resistant nitride film 36 to prevent the loss of the lower capacitor contact plug 34 during the subsequent etching of the capacitor oxide film on the diffusion barrier. The deposition method is deposited using a deposition method or a plasma deposition method at a temperature of 400 to 1000 에서 at 400 to 800 占 폚, and then deposits a USG film 37, which is an anti-diffusion film of a capacitor oxide film, on the etch-resistant nitride film 36. The 37 may be any one of a high density plasma oxide (High Density Plasma-Oxide), a plasma enhanced tetra ethyl ortho silicate (PE-TEOS), a PE-SiH ₄ , a low pressure (TE) -TEOS, and an advanced planarization layer (APL). One USG film is deposited at a thickness of 1000 Pa to 5000 Pa at 300 ° C to 600 ° C.

Subsequently, the PSG film 38 was deposited as a capacitor oxide film on the USG film 37 at a thickness of 5000 to 15000 mm at 300 to 600 ° C., and then the CD margin of a subsequent capacitor oxide film on the PSG film 38 was improved. For this purpose, either the oxynitride or the silicon sub-nitride film is deposited as the first anti-reflection film 39 at a thickness of 500 Pa to 1500 Pa at 300 ° C to 600 ° C by the plasma method.

Subsequently, any one of doped silicon, amorphous silicon, or polysilicon is deposited on the first antireflection film 39 at a thickness of 1000 Pa to 5000 Pa at 400 ° C to 1200 ° C.

Subsequently, in order to further improve the CD margin of the subsequent capacitor oxide film according to the design rule required by the device, any one of the oxynitride or silicon sub-nitride film as the second anti-reflection film 41 may be applied at 300 ° C. to 600 ° C. by the plasma method. It is deposited at a thickness of -1000 kPa.

As shown in FIG. 2B, the first and second anti-reflection films 39 and 41 and the hard mask layer 40 may be formed to form a capacitor electrode having a cylindrical shape, a concave shape, or a stacked shape. After etching selectively, the PSG film 38 and the USG film 37 are selectively etched using the patterned first and second anti-reflection films 39 and 41 and the hard mask layer 40. At this time, all of the first anti-reflection film 41 is removed to form a hard mask layer 40a remaining at a thickness of about 2/3 of the initial deposition thickness, compared to the initially deposited hard mask layer 40, The second antireflection film 39 remains at the initial deposition thickness. In addition, the etch-resistant nitride film 36 also remains at the initial deposition thickness.

As shown in FIG. 2C, some of the remaining hard mask layer 40a is removed, and the chlorine-based gas and the fluorine-based gas are maintained while maintaining the pressure in the chamber at 10 mTorr to 500 mTorr by the plasma method. Dry etching is performed using any one of a mixture gas, CF ₄ , SF ₄ , CHF ₃ , C _x F _y .

At this time, the first anti-reflection film 39 only loses about 200 mm thick (39a), and the lower PSG film 38 is not lost at all.

As shown in FIG. 2D, the etch-resistant nitride film 36 is etched. At this time, the upper first anti-reflection film 39a is completely removed, but the lower PSG film 38 and the USG film 37 are lost. Remaining without. At this time, during the etching of the etch-resistant nitride film 36, the plasma pressure is maintained at 10 mTorr to 500 mTorr and the flow rate of C ₂ F ₆ , CH ₃ F and CO, which is faster than the oxide film, is ₁ sccm to Dry etching is performed while maintaining the temperature of the upper electrode and the lower electrode in the chamber at 10 ° C. to 80 ° C. while adjusting the temperature to 10 sccm, 5 sccm to 40 sccm, and 1 sccm to 10 sccm.

As shown in FIG. 2E, a metal film of any one of tungsten, ruthenium, or iridium is used as the lower electrode 42 at a thickness of 200 to 800 Pa at 300 to 1000 ° C. by chemical vapor deposition (CVD) or sputtering. After deposition, chemical mechanical polishing is performed to form the cylindrical lower electrode 42.

Subsequently, the PSG film 38, which is the capacitor oxide film, is removed by a wet deep out to expose the lower USG film 37, and the dielectric layer 43 and the upper electrode 44 are deposited on the entire structure.

As described above, in the present invention, the lower first anti-reflection film is used as a barrier film for removing the hard mask polysilicon and etching-etch nitride film etching process, thereby preventing loss of the upper and sidewalls of the capacitor oxide film.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the method of manufacturing a capacitor according to the present invention uses a laminated film of a first anti-reflection film, polysilicon and a second anti-reflection film as an etching barrier when the capacitor oxide film is etched to prevent the loss of the capacitor oxide film, thereby ensuring sufficient capacitor capacity. It works.

Claims (20)

In the manufacturing method of a semiconductor device, A first step of forming a capacitor oxide film on the semiconductor substrate where a predetermined process is completed; A second step of forming a hard mask layer having a triple structure on the capacitor oxide film, wherein the second layer is made of a silicon film; Selectively etching the capacitor oxide layer using the hard mask layer to expose a surface of the semiconductor substrate; A fourth step of removing the hard mask layer remaining after the third step; A fifth step of sequentially forming a lower electrode / dielectric layer / upper electrode on the resultant of the fourth step Method for producing a capacitor, characterized in that comprises a. The method of claim 1, In the second step, The hard mask layer having the triple structure includes a first antireflection film, a silicon film, and a second antireflection film. The method of claim 2, The first anti-reflection film is any one of an oxynitride or a silicon sub-nitride film, the method of manufacturing a capacitor, characterized in that the deposition by the plasma method from 300 ℃ to 600 ℃ to 500 ~ 1500Å thickness. The method of claim 2, The second anti-reflection film is any one of an oxynitride or a silicon sub-nitride film, the method of manufacturing a capacitor, characterized in that the deposition by the plasma method at 300 ~ 1000Å thickness from 300 ℃ to 600 ℃. The method of claim 2, The silicon film is any one of doped silicon, amorphous silicon, or polysilicon, the method of manufacturing a capacitor, characterized in that the deposition at a thickness of 1000 ~ 5000Å at 400 ℃ to 1200 ℃. The method of claim 1, The third step, Forming a photoresist pattern on the hard mask layer to etch the capacitor oxide film after the second step; And Selectively etching the hard mask and the capacitor oxide layer using the photoresist pattern as a mask Method for producing a capacitor, characterized in that comprises a. The method according to claim 1 or 2, The fourth step, After the third step, the silicon film and the first anti-reflection film remaining in the hard mask layer of the triple structure, the first anti-reflection film is removed when etching the remaining silicon film manufacturing capacitors Way. The method of claim 7, wherein The silicon film is dry-etched using any one of CF ₄ , SF _4, CHF ₃ , and C _x F _y while maintaining the pressure in the chamber at 10 mTorr to 500 mTorr in a plasma method. Way. In the manufacturing method of a semiconductor device, Forming an etch-resistant nitride film on the semiconductor substrate on which the contact plug is formed to prevent loss of the contact plug during subsequent etching of the capacitor oxide film; A second step of forming a capacitor oxide film on the etching preventing nitride film; A third step of sequentially forming a first antireflection film, a hard mask, and a second antireflection film on the capacitor oxide film; Forming a photoresist pattern for etching a capacitor oxide film on the second antireflection film, and then etching a second antireflection film, a hard mask, a first antireflection film, and a capacitor oxide film using the photoresist pattern as a mask; A fifth step of removing the hard mask using the first anti-reflection film remaining after the fourth step; A sixth step of removing the etch-resistant nitride film by using the first anti-reflection film remaining after the fifth step; And A seventh step of forming a lower electrode by chemical mechanical polishing after forming a conductive layer for the lower electrode on the resultant of the sixth step; Method for producing a capacitor, characterized in that comprises a. The method of claim 9, Before the second step, Forming a USG film to prevent the loss of the nitride film for the etch barrier during the wet removal of the subsequent capacitor oxide film Method for producing a capacitor, characterized in that comprises a. The method of claim 9, The contact plug is made of a laminated structure of polysilicon and a diffusion barrier, the diffusion barrier is a manufacturing method of a capacitor, characterized in that the laminated film of titanium / titanium nitride or a laminated film of titanium / titanium silicide. The method of claim 9, The etch-resistant nitride film is Si _x N _y (x: y = 1: 1 to 5: 1), but the low-capacity or plasma method of the capacitor, characterized in that to deposit a 300Å ~ 1000Å thickness at 400 ℃ ~ 800 ℃ Manufacturing method. The method of claim 10, The USG film is any one of a high density plasma oxide film, PE-TEOS, PE-SiH ₄ , LP-TEOS, APL oxide film, but the capacitor is manufactured at a temperature of 1000 ~ 5000Å at 300 ℃ to 600 ℃ Way. The method of claim 9, Wherein the capacitor oxide film using a PSG film, the method of manufacturing a capacitor, characterized in that the deposition at a thickness of 5000 ~ 15000Å at 300 ℃ to 600 ℃. The method of claim 9, In the third step, The hard mask is any one of doped silicon, amorphous silicon or polysilicon, the method of manufacturing a capacitor, characterized in that to deposit a thickness of 1000 ~ 5000Å at 400 ℃ to 1200 ℃. The method of claim 9, In the third step, The first anti-reflection film is any one of an oxynitride or a silicon sub-nitride film, the method of manufacturing a capacitor, characterized in that the deposition by the plasma method from 300 ℃ to 600 ℃ to 500 ~ 1500Å thickness. The method of claim 9, In the third step, The second anti-reflection film is any one of an oxynitride or a silicon sub-nitride film, the method of manufacturing a capacitor, characterized in that the deposition by the plasma method at 300 ~ 1000Å thickness from 300 ℃ to 600 ℃. The method of claim 9, The fifth step, A method of manufacturing a capacitor of a semiconductor device, characterized by using any one of CF ₄ , SF _4, CHF ₃ , C _x F _y while maintaining the pressure in the chamber at 10 mTorr to 500 mTorr in a plasma method. The method of claim 9, The sixth step, The plasma pressure is maintained at 10 mTorr to 500 mTorr, and the flow rates of C ₂ F ₆ , CH ₃ F and CO, which are faster than the oxide film, are adjusted to 1 sccm to 10 sccm, 5 sccm to 40 sccm, and 1 sccm to 10 sccm, respectively. And the temperature of the electrode in a chamber at 10 degreeC-80 degreeC, The manufacturing method of the capacitor characterized by the above-mentioned. The method of claim 9, After the seventh step, Removing the capacitor oxide film by a wet deep out to expose a lower electrode; And And sequentially forming a dielectric layer and an upper electrode on the exposed lower electrode.