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KR20010025844A - Method for forming multi-layer wire of semiconductor device - Google Patents

Method for forming multi-layer wire of semiconductor device Download PDF

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Publication number
KR20010025844A
KR20010025844A KR1019990036888A KR19990036888A KR20010025844A KR 20010025844 A KR20010025844 A KR 20010025844A KR 1019990036888 A KR1019990036888 A KR 1019990036888A KR 19990036888 A KR19990036888 A KR 19990036888A KR 20010025844 A KR20010025844 A KR 20010025844A
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KR
South Korea
Prior art keywords
wiring
insulating film
interlayer insulating
inter
contact
Prior art date
Application number
KR1019990036888A
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Korean (ko)
Inventor
이윤봉
Original Assignee
김영환
현대반도체 주식회사
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Priority to KR1019990036888A priority Critical patent/KR20010025844A/en
Publication of KR20010025844A publication Critical patent/KR20010025844A/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for forming a metallized multilayer of a semiconductor device is provided to enable a simplified and simultaneous forming of contact holes for connecting respective metallized layers. CONSTITUTION: After an interlayer dielectric layer(22) is formed on a semiconductor substrate(21), the first metallized layer(23) is formed thereon and then patterned to define the first opening for a connection to the device. Next, the first intermetallic dielectric layer(24) is formed thereon, and the second metallized layer(25) is patterned to define the second opening for a connection to the first metallized layer(23). The second intermetallic dielectric layer(24) is then formed thereon. Thereafter, all the dielectric layers(22,24,26) are etched at a portion corresponding to the first opening to form the first contact(27), and the intermetallic dielectric layers(24,26) are simultaneously etched at another portion corresponding to the second opening to form the second contact(28). In addition, the second intermetallic dielectric layer(26) is simultaneously etched to expose a portion of the second metallized layer(25) and to form the third contact(29) thereto. Next, the third metallized layer(30) is patterned to be connected to the third contact(29).

Description

반도체소자의 다층배선 형성방법{METHOD FOR FORMING MULTI-LAYER WIRE OF SEMICONDUCTOR DEVICE}METHODS FOR FORMING MULTI-LAYER WIRE OF SEMICONDUCTOR DEVICE

본 발명은 반도체소자의 다층배선 형성방법에 관한 것으로, 특히 다층배선을 선택적으로 접속시키는 콘택(contact) 형성공정을 단순화하기에 적당하도록 한 반도체소자의 다층배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a multilayer wiring of a semiconductor device, and more particularly, to a method for forming a multilayer wiring of a semiconductor device suitable for simplifying a contact forming process for selectively connecting a multilayer wiring.

종래 반도체소자의 다층배선 형성방법을 첨부한 도1의 단면도를 참조하여 상세히 설명하면 다음과 같다.Referring to the cross-sectional view of Figure 1 attached to a conventional method for forming a multilayer wiring of a semiconductor device as follows.

먼저, 소자(미도시)가 형성된 반도체기판(1)의 상부에 층간절연막(2)을 형성한 다음 일부를 식각하여 콘택홀을 형성한다.First, an interlayer insulating film 2 is formed on the semiconductor substrate 1 on which an element (not shown) is formed, and then a portion thereof is etched to form a contact hole.

그리고, 상기 콘택홀에 도전물질을 채워 콘택(3)을 형성한 다음 콘택(3)을 포함한 층간절연막(2)의 상부에 배선물질을 증착하고, 패터닝하여 콘택(3)을 통해 소자와 선택적으로 접속되는 제1배선(4)을 형성한다.Then, the contact hole is filled with a conductive material to form a contact 3, and then a wiring material is deposited on the interlayer insulating layer 2 including the contact 3, and then patterned to selectively contact the device through the contact 3. The first wiring 4 to be connected is formed.

그리고, 상기 제1배선(4)을 포함한 층간절연막(2)의 상부에 배선간절연막(5)을 형성한 다음 제1배선(4)의 일부가 노출되도록 식각하여 콘택홀을 형성한다.Then, the interlayer insulating film 5 is formed on the interlayer insulating film 2 including the first wiring 4, and then a portion of the first wiring 4 is etched to form a contact hole.

그리고, 상기 콘택홀에 도전물질을 채워 콘택(6)을 형성한 다음 콘택(6)을 포함한 배선간절연막(5)의 상부에 배선물질을 증착하고, 패터닝하여 콘택(6)을 통해 제1배선(4)과 선택적으로 접속되는 제2배선(7)을 형성한다.Then, a contact 6 is formed by filling a conductive material in the contact hole, and then a wiring material is deposited on the interlayer insulating film 5 including the contact 6, and then patterned to form a first wiring through the contact 6. A second wiring 7 which is selectively connected with (4) is formed.

그리고, 상기 제1배선(4) 상에 제2배선(7)을 형성하는 것과 동일하게 제2배선(7) 상에 배선간절연막(8) 및 콘택(9)을 통해 제2배선(7)과 선택적으로 접속되는 제3배선(10)을 형성한 다음 제3배선(10)을 포함한 배선간절연막(8)의 상부에 보호막(11)을 형성한다.The second wiring 7 is formed on the second wiring 7 through the inter-wire insulating film 8 and the contact 9 on the second wiring 7 in the same manner as the second wiring 7 is formed on the first wiring 4. After forming the third wiring (10) to be selectively connected to and then forming a protective film 11 on top of the inter-wire insulating film (8) including the third wiring (10).

그러나, 상기한 바와같은 종래 반도체소자의 다층배선 형성방법은 각 배선을 접속시키기 위한 콘택을 형성할 때, 각기 사진식각공정이 요구됨에 따라 공정이 복잡함과 아울러 금속부산물(particle)의 양이 증가하여 수율 감소 및 제조원가 상승의 요인이 되는 문제점이 있었다.However, in the method of forming a multilayer wiring of a conventional semiconductor device as described above, when forming a contact for connecting each wiring, the photolithography process is required, and the amount of metal by-products increases. There has been a problem of a decrease in yield and a rise in manufacturing cost.

본 발명은 상기한 바와같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 한번의 사진식각공정을 통해 각 배선을 접속시키는 콘택을 동시에 형성함으로써, 콘택형성을 단순화할 수 있는 반도체소자의 다층배선 형성방법을 제공하는데 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the conventional problems as described above, and an object of the present invention is to simultaneously form a contact connecting each wire through a single photolithography process, thereby simplifying contact formation. The present invention provides a method for forming a multilayer wiring.

도1은 종래 반도체소자의 다층배선을 보인 단면도.1 is a cross-sectional view showing a multilayer wiring of a conventional semiconductor device.

도2는 본 발명의 일 실시예를 보인 단면도.Figure 2 is a cross-sectional view showing an embodiment of the present invention.

***도면의 주요부분에 대한 부호의 설명****** Explanation of symbols for main parts of drawing ***

21:반도체기판 22:층간절연막21: semiconductor substrate 22: interlayer insulating film

23,25,30:제1∼제3금속배선 24,26:제1,제2배선간절연막23, 25, 30: 1st to 3rd metal wiring 24, 26: 1st, 2nd wiring insulating film

27∼30:제1∼제3콘택 31:보호막27-30: First-third contact 31: Protective film

상기한 바와같은 본 발명의 목적을 달성하기 위한 반도체소자의 다층배선 형성방법은 소자가 형성된 반도체기판의 상부에 층간절연막을 형성하는 공정과; 상기 층간절연막의 상부에 소자와 선택적으로 접속될 영역이 이격되도록 제1배선을 패터닝하는 공정과; 상기 제1배선을 포함한 층간절연막의 상부에 제1배선간절연막을 형성하는 공정과; 상기 제1배선간절연막의 상부에 제1배선과 선택적으로 접속될 영역이 이격되도록 제2배선을 패터닝하는 공정과; 상기 제2배선을 포함한 제1배선간절연막의 상부에 제2배선간절연막을 형성하는 공정과; 상기 제1배선의 이격영역 상,하부에 형성된 제2,제1배선간절연막 및 층간절연막과, 제2배선의 이격영역 상,하부에 형성된 제2,제1배선간절연막과, 상기 제2배선의 일부가 노출되도록 제2배선간절연막을 식각한 다음 도전물질을 채워 제1∼제3콘택을 동시에 형성하는 공정과; 상기 제1∼제3콘택을 포함한 제2배선간절연막의 상부에 제3콘택을 통해 제2배선과 선택적으로 접속되는 제3배선을 패터닝하는 공정을 구비하여 이루어지는 것을 특징으로 한다.A method for forming a multilayer wiring of a semiconductor device for achieving the object of the present invention as described above comprises the steps of forming an interlayer insulating film on top of the semiconductor substrate on which the device is formed; Patterning a first wiring so as to space a region to be selectively connected to an element on the interlayer insulating film; Forming a first interlayer insulating film over the interlayer insulating film including the first wiring; Patterning the second wiring so that an area to be selectively connected to the first wiring is spaced apart from the first inter-wire insulating film; Forming a second inter-wire insulating film on the first inter-wire insulating film including the second wiring; Second and first interlayer insulating films and interlayer insulating films formed above and below the separation region of the first wiring line; second and first interlayer insulating films formed above and below the separation region of the second wiring line; and the second wiring line. Etching the second inter-wire insulating film to expose a portion of the semiconductor layer, and then filling the conductive material to simultaneously form the first to third contacts; And patterning a third wiring selectively connected to the second wiring through the third contact on the second inter-wire insulating film including the first to third contacts.

상기한 바와같은 본 발명에 의한 반도체소자의 다층배선 형성방법을 첨부한 도2의 단면도를 일 실시예로 하여 상세히 설명하면 다음과 같다.The cross-sectional view of FIG. 2 with the method of forming the multilayer wiring of the semiconductor device according to the present invention as described above will be described in detail as an embodiment.

먼저, 소자(미도시)가 형성된 반도체기판(21)의 상부에 층간절연막(22)을 형성한 다음 층간절연막(22) 상부에 소자와 선택적으로 접속될 영역이 이격되도록 제1배선(23)을 패터닝한다. 이때, 소자와 선택적으로 접속될 영역은 제1배선(23)과 소자를 선택적으로 접속시키는 제1콘택이 형성될 영역을 의미한다.First, the interlayer insulating film 22 is formed on the semiconductor substrate 21 on which the device (not shown) is formed, and then the first wiring 23 is disposed so that the region to be selectively connected to the device is spaced on the interlayer insulating film 22. Pattern. In this case, the region to be selectively connected to the element refers to a region where a first contact for selectively connecting the first wiring 23 to the element is to be formed.

그리고, 상기 패터닝된 제1배선(23)을 포함한 층간절연막(22)의 상부에 제1배선간절연막(24)을 형성한 다음 제1배선(23)과 선택적으로 접속될 영역이 이격되도록 제2배선(25)을 패터닝한다.In addition, a first interlayer insulating film 24 is formed on the interlayer insulating film 22 including the patterned first wiring 23, and then a second region is formed so that a region to be selectively connected to the first wiring 23 is spaced apart. The wiring 25 is patterned.

그리고, 상기 패터닝된 제2배선(25)을 포함한 제1배선간절연막(24)의 상부에 제2배선간절연막(26)을 형성한 다음 상기 제1배선(23)의 이격영역 상,하부에 형성된 제2,제1배선간절연막(26,24) 및 층간절연막(22)과, 제2배선(25)의 이격영역 상,하부에 형성된 제2,제1배선간절연막(26,24)과, 상기 제2배선(25)의 일부가 노출되도록 제2배선간절연막(26)을 식각하고, 도전물질을 채워 제1∼제3콘택(27∼29)을 동시에 형성한다. 이때, 한번의 식각을 통해 제1∼제3콘택(27∼29)을 동시에 형성하기 위해서 층간절연막(22) 및 제1,제2배선간절연막(24,26)을 동일한 재질로 형성하는 것이 바람직하고, 이에 따라 금속부산물의 발생을 최소화할 수 있게 되며, 제1,제2배선(23,25)의 이격된 영역은 제1,제2콘택(27,28)에 의해 각각 접속된다.In addition, a second inter-wire insulating film 26 is formed on the first inter-wire insulating film 24 including the patterned second wiring 25, and then above and below the separation area of the first wiring 23. The second and first interlayer insulating layers 26 and 24 and the interlayer insulating layer 22 formed therein, and the second and first interlayer insulating layers 26 and 24 formed above and below the separation region of the second wiring 25. The second interlayer insulating layer 26 is etched to expose a portion of the second wiring 25, and the first to third contacts 27 to 29 are simultaneously formed by filling the conductive material. In this case, in order to simultaneously form the first to third contacts 27 to 29 through one etching, the interlayer insulating film 22 and the first and second interwire insulating films 24 and 26 may be formed of the same material. Accordingly, the generation of metal by-products can be minimized, and the spaced apart regions of the first and second wirings 23 and 25 are connected by the first and second contacts 27 and 28, respectively.

그리고, 상기 제1∼제3콘택(27∼29)을 포함한 제2배선간절연막(26)의 상부에 제3콘택(29)을 통해 제2배선(24)과 선택적으로 접속되는 제3배선(30)을 패터닝한 다음 제3배선(30) 및 제1,제2콘택(27,28)을 포함한 제2배선간절연막(26)의 상부에 보호막(31)을 형성한다.In addition, a third wiring (not shown) may be selectively connected to the second wiring 24 through the third contact 29 on the second inter-wire insulating layer 26 including the first to third contacts 27 to 29. After patterning 30, a passivation layer 31 is formed on the second inter-wire insulating layer 26 including the third wiring 30 and the first and second contacts 27 and 28.

한편, 상기한 바와같은 본 발명의 일 실시예에 있어서, 반도체기판(11) 상에 형성된 소자(미도시)와 제1배선(23)을 선택적으로 접속시키는 제1콘택(27)이 식각률(etch rate)에 의한 문제, 종횡비(aspect ratio)에 의한 문제 또는 설계상의 중첩(overlap)에 의한 문제 등으로 인해 제2,제3콘택(28,29)과 동시에 형성하는 것이 불가능할 때는 제1배선(23)을 형성하는 공정까지는 종래와 동일하게 실시한 다음 제2,제3콘택(28,29)을 형성함에 있어서, 본 발명의 일 실시예를 적용할 수 있다.Meanwhile, in one embodiment of the present invention as described above, the first contact 27 for selectively connecting the element (not shown) formed on the semiconductor substrate 11 and the first wiring 23 is etched. When it is impossible to simultaneously form the second and third contacts 28 and 29 due to a problem due to a rate, an aspect ratio, or a design overlap, the first wiring 23 ) Is performed in the same manner as in the prior art, and then, in forming the second and third contacts 28 and 29, an embodiment of the present invention may be applied.

상기한 바와같은 본 발명의 실시예에서는 제1∼제3배선(23,25,30)의 3층배선을 예로 들었지만, 보다 많은 배선층을 적용함에 있어서도 응용이 가능할 것이다.In the embodiment of the present invention as described above, the three-layer wiring of the first to third wirings 23, 25, and 30 is taken as an example. However, the application may be applied even when more wiring layers are applied.

상기한 바와같은 본 발명에 의한 반도체소자의 다층배선 형성방법은 한번의 사진식각공정을 통해 각 배선을 접속시키는 콘택을 동시에 형성함으로써, 콘택형성을 단순화하여 공정시간 단축 및 제조원가 절감의 효과가 있으며, 금속부산물의 발생을 최소화하여 수율을 향상시킬 수 있는 효과가 있다.As described above, the method for forming a multilayer wiring of a semiconductor device according to the present invention simultaneously forms a contact connecting each wiring through a single photolithography process, thereby simplifying contact formation and reducing process time and manufacturing cost. There is an effect that can improve the yield by minimizing the generation of metal by-products.

Claims (3)

소자가 형성된 반도체기판의 상부에 층간절연막을 형성하는 공정과; 상기 층간절연막의 상부에 소자와 선택적으로 접속될 영역이 이격되도록 제1배선을 패터닝하는 공정과; 상기 제1배선을 포함한 층간절연막의 상부에 제1배선간절연막을 형성하는 공정과; 상기 제1배선간절연막의 상부에 제1배선과 선택적으로 접속될 영역이 이격되도록 제2배선을 패터닝하는 공정과; 상기 제2배선을 포함한 제1배선간절연막의 상부에 제2배선간절연막을 형성하는 공정과; 상기 제1배선의 이격영역 상,하부에 형성된 제2,제1배선간절연막 및 층간절연막과, 제2배선의 이격영역 상,하부에 형성된 제2,제1배선간절연막과, 상기 제2배선의 일부가 노출되도록 제2배선간절연막을 식각한 다음 도전물질을 채워 제1∼제3콘택을 동시에 형성하는 공정과; 상기 제1∼제3콘택을 포함한 제2배선간절연막의 상부에 제3콘택을 통해 제2배선과 선택적으로 접속되는 제3배선을 패터닝하는 공정을 구비하여 이루어지는 것을 특징으로 하는 반도체소자의 다층배선 형성방법.Forming an interlayer insulating film over the semiconductor substrate on which the element is formed; Patterning a first wiring so as to space a region to be selectively connected to an element on the interlayer insulating film; Forming a first interlayer insulating film over the interlayer insulating film including the first wiring; Patterning the second wiring so that an area to be selectively connected to the first wiring is spaced apart from the first inter-wire insulating film; Forming a second inter-wire insulating film on the first inter-wire insulating film including the second wiring; Second and first interlayer insulating films and interlayer insulating films formed above and below the separation region of the first wiring line; second and first interlayer insulating films formed above and below the separation region of the second wiring line; and the second wiring line. Etching the second inter-wire insulating film to expose a portion of the semiconductor layer, and then filling the conductive material to simultaneously form the first to third contacts; And patterning a third wiring, which is selectively connected to the second wiring through a third contact, over the second inter-wire insulating film including the first to third contacts. Formation method. 제 1 항에 있어서, 상기 층간절연막 및 제1,제2배선간절연막은 동일한 재질로 형성하는 것을 특징으로 하는 반도체소자의 다층배선 형성방법.The method of claim 1, wherein the interlayer insulating layer and the first and second interlayer insulating layers are formed of the same material. 소자가 형성된 반도체기판의 상부에 층간절연막을 형성한 다음 일부를 식각하여 콘택홀을 형성하고, 도전물질을 채워 제1콘택을 형성하는 공정과; 상기 제1콘택을 포함한 층간절연막의 상부에 제1콘택을 통해 소자와 선택적으로 접속되는 제1배선을 패터닝하는 공정과; 상기 제1배선을 포함한 층간절연막의 상부에 제1배선간절연막을 형성하는 공정과; 상기 제1배선간절연막의 상부에 제1배선과 선택적으로 접속될 영역이 이격되도록 제2배선을 패터닝하는 공정과; 상기 제2배선을 포함한 제1배선간절연막의 상부에 제2배선간절연막을 형성하는 공정과; 상기 제2배선의 이격영역 상,하부에 형성된 제2,제1배선간절연막과, 상기 제2배선의 일부가 노출되도록 제2배선간절연막을 식각한 다음 도전물질을 채워 제2,제3콘택을 동시에 형성하는 공정과; 상기 제2,제3콘택을 포함한 제2배선간절연막의 상부에 제3콘택을 통해 제2배선과 선택적으로 접속되는 제3배선을 패터닝하는 공정을 구비하여 이루어지는 것을 특징으로 하는 반도체소자의 다층배선 형성방법.Forming a contact hole by forming an interlayer insulating film on the semiconductor substrate on which the device is formed, and then etching a portion of the semiconductor substrate, and filling the conductive material to form a first contact; Patterning a first wiring selectively connected to the device via the first contact on the interlayer insulating film including the first contact; Forming a first interlayer insulating film over the interlayer insulating film including the first wiring; Patterning the second wiring so that an area to be selectively connected to the first wiring is spaced apart from the first inter-wire insulating film; Forming a second inter-wire insulating film on the first inter-wire insulating film including the second wiring; Etching the second and first inter-wire insulating films formed on the upper and lower portions of the separation area of the second wiring and the second inter-wire insulating film so that a portion of the second wiring is exposed, and then filling the conductive material to fill the second and third contacts Simultaneously forming; And patterning a third wiring, which is selectively connected to the second wiring through a third contact, over the second inter-wire insulating film including the second and third contacts. Formation method.
KR1019990036888A 1999-09-01 1999-09-01 Method for forming multi-layer wire of semiconductor device KR20010025844A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101503682B1 (en) * 2008-04-18 2015-03-20 삼성전자 주식회사 Shared type image sensor and method of fabricating the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101503682B1 (en) * 2008-04-18 2015-03-20 삼성전자 주식회사 Shared type image sensor and method of fabricating the same

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