KR0166798B1 - Forming method of metal wiring - Google Patents
Forming method of metal wiring Download PDFInfo
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- KR0166798B1 KR0166798B1 KR1019950052213A KR19950052213A KR0166798B1 KR 0166798 B1 KR0166798 B1 KR 0166798B1 KR 1019950052213 A KR1019950052213 A KR 1019950052213A KR 19950052213 A KR19950052213 A KR 19950052213A KR 0166798 B1 KR0166798 B1 KR 0166798B1
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- conductive layer
- interlayer insulating
- forming
- insulating film
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- 239000002184 metal Substances 0.000 title claims abstract description 45
- 238000000034 method Methods 0.000 title claims abstract description 44
- 239000010410 layer Substances 0.000 claims abstract description 99
- 239000011229 interlayer Substances 0.000 claims abstract description 56
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000004519 manufacturing process Methods 0.000 abstract description 7
- 238000000206 photolithography Methods 0.000 description 20
- 239000007769 metal material Substances 0.000 description 12
- 239000004020 conductor Substances 0.000 description 11
- 238000009792 diffusion process Methods 0.000 description 10
- 239000004065 semiconductor Substances 0.000 description 8
- 239000011810 insulating material Substances 0.000 description 7
- 239000012535 impurity Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 금속배선 형성방법에 관한 것으로, 한 번의 콘택형성 공정에 의해 다층배선 공정을 수행할 수 있어 배선공정수를 줄일 수 있으므로 제조공정 단가를 낮출 수 있고, 제작수율을 높일 수 있도록 한 것이다.The present invention relates to a method for forming a metal wiring, and can perform a multi-layer wiring process by one contact forming process, thereby reducing the number of wiring processes, thereby lowering the manufacturing process cost and increasing the manufacturing yield.
본 발명에 따른 금속배선 형성방법은 복수개의 도전층들을 연결하는 금속배선 형성방법에 있어서, 기판상에 제1도전층을 형성하는 단계; 상기 제1도전층상에 제1층간절연막을 형성하는 단계; 상기 제1층간절연막 위에 콘택부분을 제외한 부분만 남도록 제2도전층을 형성하는 단계; 상기 제2도전층과 상기 제1층간절연막의 노출된 표면에 상기 제2도전층의 콘택부분을 매립하도록 제2층간절연막을 형성하는 단계; 상기 제2층간절연막과 제1층간절연막을 선택적으로 제거하여 상기 제2도전층의 콘택부분을 통해서 제1도전층을 노출시키는 제1콘택홀과, 제2도전층을 노출시키는 제2콘택홀을 각각 형성하는 단계; 상기 제1 및 2콘택홀내에 제1 및 2금속바아를 각각 매립형성하는 단계; 상기 제2금속바아를 포함한 상기 제2층간절연막 위에 제3도전층을 형성하는 단계를 포함하여 이루어진다.In accordance with another aspect of the present invention, there is provided a method of forming a metal wiring, the method comprising: forming a first conductive layer on a substrate; Forming a first interlayer insulating film on the first conductive layer; Forming a second conductive layer on the first interlayer insulating film so that only a portion except for a contact portion remains; Forming a second interlayer insulating film so as to fill a contact portion of the second conductive layer on an exposed surface of the second conductive layer and the first interlayer insulating film; Selectively removing the second interlayer insulating film and the first interlayer insulating film to expose a first contact hole through the contact portion of the second conductive layer, and a second contact hole exposing the second conductive layer. Forming each; Embedding first and second metal bars in the first and second contact holes, respectively; And forming a third conductive layer on the second interlayer insulating film including the second metal bar.
Description
제1a∼1f도는 종래의 금속배선 형성공정 단면도.1A to 1F are cross-sectional views of a conventional metal wiring forming step.
제2a∼2e도는 본 발명에 따른 금속배선 형성공정 단면도.2A to 2E are cross-sectional views of a metal wiring forming process according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
21 : 반도체기판 22 : 확산층21 semiconductor substrate 22 diffusion layer
23 : 제1층간절연막 24 : 제1도전층23: first interlayer insulating film 24: first conductive layer
24a : 제1콘택부분 25 : 제2층간절연막24a: first contact portion 25: second interlayer insulating film
26 : 제2도전층 26a : 제2콘택부분26: second conductive layer 26a: second contact portion
27 : 제3층간절연막 28 : 제1콘택홀27: third interlayer insulating film 28: first contact hole
28a : 제1금속바아 29 : 제2콘택홀28a: first metal bar 29: second contact hole
29a : 제2금속바아 30 : 제3콘택홀29a: second metal bar 30: third contact hole
30a : 제3금속바아 31 : 제3도전층30a: third metal bar 31: third conductive layer
본 발명은 반도체장치의 금속배선 형성방법에 관한 것으로, 특히 한 번의 콘택형성 공정에 의해 다층배선 공정을 수행할 수 있으므로 고집적 소자의 다층배선 형성시에 적합하도록 한 금속배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in a semiconductor device, and more particularly, to a method for forming metal wirings suitable for forming multi-layer wirings of a highly integrated device since a multi-layer wiring process can be performed by one contact forming process.
종래의 금속배선 형성방법을 첨부된 도면을 참조하여 간략하게 설명하면 다음과 같다.Referring to the accompanying drawings, a conventional metal wire forming method is briefly described as follows.
제1a∼1f도는 종래의 금속배선 형성공정 단면도로서, 3층 배선형성시의 공정도이다.1A to 1F are sectional views of a conventional metal wiring forming step, and a process chart at the time of forming a three-layer wiring.
종래의 금속배선 형성방법은, 먼저 제1a도에 도시된 바와 같이, 반도체기판(1)을 준비하고, 상기 반도체기판(1)의 일부분에 불순물이온을 주입하여 확산층(2)을 형성한다.In the conventional metal wiring forming method, first, as shown in FIG. 1A, a semiconductor substrate 1 is prepared, and a diffusion layer 2 is formed by implanting impurity ions into a portion of the semiconductor substrate 1.
그다음 상기 확산층(2)을 포함한 상기 반도체기판(1)위에 절연물질을 증착하여 제1층간절연막(3)을 형성한다.Then, an insulating material is deposited on the semiconductor substrate 1 including the diffusion layer 2 to form a first interlayer insulating film 3.
이어서 사진석판술(photolithography) 및 사진식각 공정에 의해 상기 제1층간절연막(3)을 선택적으로 제거하여 상기 확산층(2)을 노출시키는 제1콘택홀(3a)을 형성한다.Subsequently, the first interlayer insulating layer 3 is selectively removed by photolithography and photolithography to form a first contact hole 3a exposing the diffusion layer 2.
그다음 제1b도에 도시된 바와 같이, 상기 제1콘택홀(3a)을 포함한 상기 제1층간절연막(3)위에 상기 제1콘택홀(3a)을 매립하도록 금속물질을 증착하고, 상기 제1콘택홀(3a)에 매립된 부분만 남도록 상기 금속물질층을 선택적으로 제거하여 제1금속바아(metal bar)(4)를 형성한다.Next, as illustrated in FIG. 1B, a metal material is deposited to fill the first contact hole 3a on the first interlayer insulating layer 3 including the first contact hole 3a and the first contact. The metal material layer is selectively removed so that only a portion embedded in the hole 3a is left to form a first metal bar 4.
이어서 상기 제1금속바아(4)를 포함한 상기 제1층간절연막(3)상에 도전물질을 증착하고, 사진석판술 및 사진식각 공정에 의해 상기 도전물질을 선택적으로 제거하여 제1도전층(5)을 형성한다.Subsequently, a conductive material is deposited on the first interlayer insulating film 3 including the first metal bar 4, and the conductive material is selectively removed by photolithography and photolithography to thereby remove the first conductive layer 5. ).
이때 상기 제1도전층(5)은 상기 제1금속바아(4)에 의해 상기 확산층(2)과 전기적으로 연결된다.In this case, the first conductive layer 5 is electrically connected to the diffusion layer 2 by the first metal bar 4.
그다음 제1c도에 도시된 바와 같이, 상기 제1도전층(5)을 포함한 상기 제1층간절연막(3)의 노출된 표면에 절연물질을 증착하여 제2층간절연막(6)을 형성한다. 이어서 사진석판술 및 사진식각 공정에 의해 상기 제2층간절연막(6)을 선택적으로 제거하여 상기 제1도전층(5)을 노출시키는 제2콘택홀(6a)을 형성한다.Next, as illustrated in FIG. 1C, an insulating material is deposited on an exposed surface of the first interlayer insulating film 3 including the first conductive layer 5 to form a second interlayer insulating film 6. Subsequently, the second interlayer insulating film 6 is selectively removed by photolithography and photolithography to form a second contact hole 6a exposing the first conductive layer 5.
그다음 제1d도에 도시된 바와 같이, 상기 제2콘택홀(6a)을 포함한 상기 제2층간절연막(6)위에 상기 제2콘택홀(6a)을 매립하도록 금속물질을 증착하고, 상기 제2콘택홀(6a)에 매립되는 부분만 남도록 상기 금속물질층을 선택적으로 제거하여 제2금속바아(7)를 형성한다.Next, as illustrated in FIG. 1D, a metal material is deposited to fill the second contact hole 6a on the second interlayer insulating layer 6 including the second contact hole 6a and the second contact. The second metal bar 7 is formed by selectively removing the metal material layer so that only the portion embedded in the hole 6a remains.
이어서 상기 제2금속바아(7)를 포함한 상기 제2층간절연막(6)위에 도전물질을 증착하고, 사진석판술 및 사진식각 공정에 의해 상기 도전물질을 선택적으로 제거하여 제2도전층(8)을 형성한다.Subsequently, a conductive material is deposited on the second interlayer insulating film 6 including the second metal bar 7, and the conductive material is selectively removed by photolithography and photolithography to form a second conductive layer 8. To form.
이때 상기 제2도전층(8)은 상기 제2금속바아(7)에 의해 상기 제1도전층(5)과 전기적으로 상호 연결된다.In this case, the second conductive layer 8 is electrically connected to the first conductive layer 5 by the second metal bar 7.
그다음 제1e도에 도시된 바와 같이, 상기 제2도전층(8)을 포함한 상기 제2층간절연막(6)의 노출된 표면에 절연물질을 증착하여 제3층간절연막(9)을 형성한다. 이어서 사진석판술 및 사진식각 공정에 의해 상기 제3층간절연막(9)을 선택적으로 제거하여 상기 제2도전층(8)을 노출시키는 제3콘택홀(9a)을 형성한다.Next, as illustrated in FIG. 1E, an insulating material is deposited on an exposed surface of the second interlayer insulating film 6 including the second conductive layer 8 to form a third interlayer insulating film 9. Subsequently, the third interlayer insulating layer 9 is selectively removed by photolithography and photolithography to form a third contact hole 9a exposing the second conductive layer 8.
그다음 제1f도에 도시된 바와 같이, 상기 제3콘택홀(9a)을 포함한 상기 제3층간절연막(9)위에 금속물질을 상기 제3콘택홀(9a)을 매립하도록 증착하고, 상기 제3콘택홀(9a)에 매립되는 부분만 남도록 상기 금속물질층을 선택적으로 제거하여 제3금속바아(10)를 형성한다.Next, as shown in FIG. 1F, a metal material is deposited on the third interlayer insulating layer 9 including the third contact hole 9a to fill the third contact hole 9a and the third contact. The third metal bar 10 is formed by selectively removing the metal material layer so that only a portion embedded in the hole 9a remains.
이어서 상기 제3금속바아(10)를 포함한 상기 제3층간절연막(9)상에 도전물질을 증착하고, 사진석판술 및 사진식각 공정에 의해 상기 도전물질을 선택적으로 제거하여 제3도전층(11)을 형성하므로써 3층 배선공정을 완료한다.Subsequently, a conductive material is deposited on the third interlayer insulating film 9 including the third metal bar 10, and the conductive material is selectively removed by photolithography and photolithography to form a third conductive layer 11. ) To complete the 3-layer wiring process.
이때 상기 제3도전층(11)은 상기 제3금속바아(10)에 의해 상기 제2도전층(8)과 전기적으로 상호 연결된다.In this case, the third conductive layer 11 is electrically connected to the second conductive layer 8 by the third metal bar 10.
상기에서와 같이 종래의 금속배선 형성방법에 있어서는 다음과 같은 문제점이 있다. 종래의 금속배선 형성방법에 있어서는 다층배선 형성시에 배선층수 만큼의 콘택홀 형성 공정과 함께 배선형성 공정이 필요하게 되어 배선공정수가 증가하므로 제조공정 단가가 높아지고, 생산성이 떨어진다.As described above, the conventional metal wiring forming method has the following problems. In the conventional metal wiring forming method, the wiring forming process is required along with the contact hole forming process as many as the number of wiring layers at the time of forming the multilayer wiring, thereby increasing the number of wiring processes, resulting in higher manufacturing process cost and lower productivity.
또한 종래의 금속배선 형성방법에 있어서는 배선층수가 증가함에 따라 공정 태트(TAT)가 증가하고, 제작수율이 떨어진다.In addition, in the conventional metal wiring forming method, as the number of wiring layers increases, the process tAT increases and the production yield decreases.
본 발명은 상기 종래의 문제점을 해결하기 위하여 안출한 것으로서, 한 번의 콘택형성 공정에 의해 다층배선 공정을 수행할 수 있어 배선공정수를 줄일 수 있으므로 배선공정을 단순화시킴은 물론 생산성을 향상시키고, 제작수율을 높일 수 있도록 한 금속배선 형성방법을 제공함에 그 목적이 있다.The present invention has been made in order to solve the above-mentioned problems, it is possible to perform a multi-layer wiring process by a single contact forming process can reduce the number of wiring process, simplifying the wiring process as well as improving the productivity, fabrication It is an object of the present invention to provide a method for forming a metal wiring to increase the yield.
상기 목적을 달성하기 위한 본 발명에 따른 금속배선 형성방법은 복수개의 도전층들을 연결하는 금속배선 형성방법에 있어서, 가판상에 제1도전층을 형성하는 단계; 상기 제1도전층상에 제1층간절연막을 형성하는 단계; 상기 제1층간절연막 위에 콘택부분을 제외한 부분만 남도록 제2도전층을 형성하는 단계; 상기 제2도전층과 상기 제1층간절연막의 노출된 표면에 상기 제2도전층의 콘택부분을 매립하도록 제2층간절연막을 형성하는 단계; 상기 제2층간절연막과 제1층간절연막을 선택적으로 제거하여 상기 제2도전층의 콘택부분을 통해서 제1도전층을 노출시키는 제1콘택홀과, 제2도전층을 노출시키는 제2콘택홀을 각각 형성하는 단계; 상기 제1 및 2콘택홀내에 제1 및 2금속바아를 각각 매립형성하는 단계; 상기 제2금속바아를 포함한 상기 제2층간절연막 위에 제3도전층을 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.According to an aspect of the present invention, there is provided a metal wiring forming method comprising: forming a first conductive layer on a substrate by forming a metal wiring connecting a plurality of conductive layers; Forming a first interlayer insulating film on the first conductive layer; Forming a second conductive layer on the first interlayer insulating film so that only a portion except for a contact portion remains; Forming a second interlayer insulating film so as to fill a contact portion of the second conductive layer on an exposed surface of the second conductive layer and the first interlayer insulating film; Selectively removing the second interlayer insulating film and the first interlayer insulating film to expose a first contact hole through the contact portion of the second conductive layer, and a second contact hole exposing the second conductive layer. Forming each; Embedding first and second metal bars in the first and second contact holes, respectively; And forming a third conductive layer on the second interlayer insulating film including the second metal bar.
본 발명을 첨부된 도면을 참조하여 상세히 설명한다.The present invention will be described in detail with reference to the accompanying drawings.
제2a∼2e도는 본 발명에 따른 금속배선 형성방법 단면도로서, 3층 배선형성시의 공정단면도이다.2A to 2E are cross-sectional views of a metal wiring forming method according to the present invention, which is a process cross section at the time of forming three-layer wiring.
본 발명에 따른 금속배선 형성방법은, 먼저 제2a도에 도시된 바와 같이, 반도체기판(21)을 준비하고, 상기 반도체기판(21)일부분에 불순물 이온주입을 실시하여 확산층(22)을 형성한다.In the method for forming metal wirings according to the present invention, first, as shown in FIG. 2A, a semiconductor substrate 21 is prepared, and a portion of the semiconductor substrate 21 is implanted with impurity ions to form a diffusion layer 22. .
이어서 상기 확산층(22)을 포함한 반도체기판(21)상에 배선층간을 전기적으로 격리시키기 위해 절연물질을 증착하여 제1층간절연막(23)을 형성한다.Subsequently, an insulating material is deposited on the semiconductor substrate 21 including the diffusion layer 22 to form a first interlayer insulating film 23 by electrically insulating an insulating material.
그다음 제2b도에 도시된 바와 같이, 상기 제1층간절연막(23)상에 금속물질을 증착하고, 사진석판술(photolithography) 및 사진식각 공정에 의해 상기 금속물질층을 선택적으로 제거하여 제1도전층(24)을 형성한다.Next, as shown in FIG. 2B, a metal material is deposited on the first interlayer insulating film 23, and the metal material layer is selectively removed by photolithography and photolithography to form a first conductive layer. Forms layer 24.
이때 상기 확산층(22)과 전기적으로 연결되는 상기 제1도전층(24a)의 제1콘택부분(24a)에 금속물질이 형성되지 않도록 한다.At this time, the metal material is not formed in the first contact portion 24a of the first conductive layer 24a electrically connected to the diffusion layer 22.
이어서 제2c도에 도시된 바와 같이, 상기 제1콘택부분(24a)을 포함한 제1도전층(24)과 제1층간절연막(23)의 노출된 표면에 절연물질을 증착하여 제2층간절연막(25)을 형성한다.Subsequently, as shown in FIG. 2C, an insulating material is deposited on the exposed surfaces of the first conductive layer 24 including the first contact portion 24a and the first interlayer insulating film 23 to form a second interlayer insulating film ( 25).
그다음 상기 제2층간절연막(25)위에 금속물질을 증착하고, 사진석판술 및 사진식각 공정에 의해 상기 금속물질층을 선택적으로 제거하여 제2도전층(26)을 형성한다.Next, a metal material is deposited on the second interlayer insulating film 25, and the metal material layer is selectively removed by photolithography and photolithography to form a second conductive layer 26.
이때 상기 제1도전층(24)과 전기적으로 연결되는 상기 제2도전층(26)의 제1콘택부분(26a)에 금속물질이 형성되지 않도록 한다.In this case, a metal material is not formed in the first contact portion 26a of the second conductive layer 26 electrically connected to the first conductive layer 24.
이어서 제2d도에 도시된 바와 같이, 상기 제2콘택부분(26a)을 포함한 상기 제2도전층(26)과 제2층간절연막(25)의 노출된 표면에 절연물질을 증착하여 제3층간절연막(27)을 형성한다.Subsequently, as illustrated in FIG. 2D, an insulating material is deposited on the exposed surfaces of the second conductive layer 26 and the second interlayer insulating layer 25 including the second contact portion 26a to form a third interlayer insulating layer. (27) is formed.
그다음 상기 확산층(22)과 제1도전층(24) 및 제2도전층(26)이 각각 노출되도록 사진석판술 및 사진식각 공정에 의해 상기 제3층간절연막(27)과 제2층간절연막(25) 및 제1층간절연막(23)을 선택적으로 제고하여 제1, 2, 3콘택홀(28)(29)(30)을 한 번에 형성한다.Then, the third interlayer insulating film 27 and the second interlayer insulating film 25 by photolithography and photolithography processes to expose the diffusion layer 22, the first conductive layer 24, and the second conductive layer 26, respectively. ) And the first interlayer insulating film 23 are selectively formed to form the first, second and third contact holes 28, 29 and 30 at once.
이때 상기 제1콘택홀(28)은 상기 제1도전층(24)의 제1콘택부분(24a)의 상, 하부에 걸쳐 형성된 상기 제3층간절연막(27)과 제2층간절연막(25) 및 제1층간절연막(23) 부분을 선택적으로 제거하여 형성한다.In this case, the first contact hole 28 includes the third interlayer insulating layer 27 and the second interlayer insulating layer 25 formed over and under the first contact portion 24a of the first conductive layer 24. A portion of the first interlayer insulating film 23 is selectively removed.
또한 상기 제2콘택홀(29)은 상기 제2도전층(26)의 제2콘택부분(26a)의 상, 하부에 걸쳐 형성된 상기 제3층간절연막(27)과 제2층간절연막(25) 부분을 선택적으로 제거하여 형성한다.In addition, the second contact hole 29 is a portion of the third interlayer insulating layer 27 and the second interlayer insulating layer 25 formed over and under the second contact portion 26a of the second conductive layer 26. It is formed by selectively removing.
그리고 상기 제3콘택홀(30)은 상기 제3층간절연막(27) 부분을 선택적으로 제거하여 형성한다.The third contact hole 30 is formed by selectively removing a portion of the third interlayer insulating layer 27.
이어서 제2e도에 도시된 바와 같이, 상기 제1, 2, 3콘택홀(28)(29)(30)을 포함한 상기 제3층간절연막(27)의 노출된 표면상에 상기 제1, 2, 3콘택홀(28)(29)(30)을 완전 매립하도록 도전물질을 증착한다.Subsequently, as shown in FIG. 2E, the first, second, and third contact holes 28, 29, and 30 are exposed on the exposed surface of the third interlayer insulating film 27 including the first, second, and third contact holes 28, 29, and 30. The conductive material is deposited to completely fill the three contact holes 28, 29, and 30.
그다음 상기 제1, 2, 3콘택홀(28)(29)(30)내에 매립된 도전물질부분만 남도록 상기 도전물질층을 선택적으로 제거하여 제1, 2, 3금속바아(28a)(29a)(30a)를 한 번에 형성한다.Then, the conductive material layer is selectively removed so that only portions of the conductive material embedded in the first, second, and third contact holes 28, 29, and 30 remain, so that the first, second, and third metal bars 28a and 29a are formed. 30a is formed at once.
이때 상기 제1금속바아(28a)는 확산층(22)꽈 상기 제1도전층(24)을 전기적으로 상호 연결시켜 준다.At this time, the first metal bar 28a electrically connects the diffusion layer 22 to the first conductive layer 24.
또한 상기 제2금속바아(29a)는 상기 제1도전층(24)과 상기 제2도전층(26)을 전기적으로 상호 연결시켜 준다.In addition, the second metal bar 29a electrically interconnects the first conductive layer 24 and the second conductive layer 26.
이어서 상기 제3금속바아(30a)를 포함한 상기 제3층간절연막(27)상에 도전물질을 증착하고, 사진석판술 및 사진식각 공정에 의해 상기 도전물질층을 선택적으로 제거하여 제3도전층(31)을 형성하므로써 3층 배선공정을 완료한다.Subsequently, a conductive material is deposited on the third interlayer insulating film 27 including the third metal bar 30a, and the conductive material layer is selectively removed by photolithography and photolithography to form a third conductive layer ( 31) to complete the three-layer wiring process.
이때 상기 제3금속바아(30a)는 상기 제2도전층(26)과 상기 제3도전층(31)을 전기적으로 상호 연결시켜 준다.In this case, the third metal bar 30a electrically connects the second conductive layer 26 and the third conductive layer 31 to each other.
상기에서와 같이 본 발명에 따른 금속배선 형성방법에 있어서는 다음과 같은 효과가 있다.As described above, the metal wiring forming method according to the present invention has the following effects.
본 발명에 따른 금속배선 형성방법에 있어서는 배선층수에 상관없이 한 번의 콘택형성 공정에 의해 다층배선 공정을 수행할 수 있어 배선공정수를 줄일 수 있으므로 고집적소자의 다층배선 형성시에 적합하다.In the metal wiring forming method according to the present invention, the multilayer wiring process can be performed by one contact forming process irrespective of the number of wiring layers, so that the number of wiring processes can be reduced, which is suitable for forming multilayer wirings of highly integrated devices.
그러므로써 배선공정수의 감소로 인하여 제조공정 단가를 낮출수 있고, 생산성을 향상시킬 수 있음은 물론 제작수율을 높일 수 있다.Therefore, due to the reduction in the number of wiring processes, the manufacturing process cost can be lowered, productivity can be improved, and manufacturing yield can be increased.
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| KR100539576B1 (en) * | 1999-08-09 | 2005-12-29 | 매그나칩 반도체 유한회사 | Method of manufacturing multilevel metal interconnetion |
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| KR100539576B1 (en) * | 1999-08-09 | 2005-12-29 | 매그나칩 반도체 유한회사 | Method of manufacturing multilevel metal interconnetion |
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