JPS60187039A - Multilayer interconnection member - Google Patents

Abstract

PURPOSE:To obtain an excellent electrical connection by a method wherein, when the upper wiring is to be connected to the underlying wiring, an interlayer insulating layer is covered on the underlaying wiring, the insulating layer is removed corresponding to the connected part, a connection hole burying layer is filled therein surrounded with an etching preventing member, and the upper wiring is brought to come in contact with the burying layer. CONSTITUTION:An insulating film 2 is coated on an Si substrate 1, the first layer of Al source wiring 3A and a fine Al wiring 3B are formed thereon, and an interlayer insulating layer 4 is coated on the whole surface including the above-mentioned layer and wirings. Then, the insulating layer 4 located on the wirings 3A and 3B is removed, and an Al burying layer 7 is filled in the part where the layer 4 was removed while said part is being surrounded by a Ti-W alloy or the etching preventing member 6 consisting of Cu. At this time, an etching preventing member 6 is provided on the bottom face and the side wall of the wiring 3B, but on the wiring 3A of large area, an aperture is provided on the etching preventing member 6 located on the bottom face. Subsequently, the second layer of wirings 8A and 8B are connected to the wirings 3A and 3B through the intermediary of the etching preventing member 6, and the semiconductor device is protected by covering a protective layer 9 on the whole surface.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a technology that is effective when applied to multilayer wiring technology, and particularly to a technology that is effective when applied to multilayer wiring technology for semiconductor integrated circuit devices (hereinafter referred to as IC). It is about effective techniques.

[Background technology]

An IC equipped with a multilayer wiring structure in which conductive layers and insulating layers are alternately stacked on top of a semiconductor substrate to form a plurality of layers has a structure in which the upper layer wiring is provided via the lower layer wiring and the interlayer insulation layer, and the upper layer wiring is provided through the interlayer insulation layer. Electrical connections are made through connection holes, but in order to achieve high integration, the connection holes tend to be formed by a dry etching process.

In an IC with a multilayer wiring structure constructed by a combination of these, the connection hole forms a steep stepped shape, and the adhesion of the upper layer wiring in that part is extremely poor, resulting in decreased electrical reliability. There is a problem with this.

Therefore, it is conceivable to fill the inside of the contact hole with aluminum using vertical evaporation technology to alleviate the steep step shape and obtain electrical reliability of the upper layer wiring.

As a result of studies on this technology, the present inventors have found that the connection holes, particularly those with relatively large diameters used for power supply wiring and equal pressure (hereinafter referred to as large-area connection holes), are suitable for electrical connections. We have found a problem in that there are cases where the process is not carried out properly.

This is due to the reasons mentioned below.

The process of embedding aluminum inside the connection hole is as follows. First, a lower wiring is formed, an interlayer insulating layer is formed to cover it, and a contact hole is formed by removing the interlayer insulating layer at a predetermined upper part of the lower wiring. Thereafter, aluminum is formed on the entire upper surface of the silicon oxide layer by vertical evaporation technique so as to fill the inside of the connection hole. Then, a mask is formed to remove unnecessary aluminum other than the aluminum embedded in the connection circuit, and the unnecessary aluminum is removed. The mask uses photoresist, an insulating film, etc., and is usually formed by rotating a wafer constituting an IC, applying a mask material having flowability, and removing the flowability. Therefore, a thick mask is formed on the aluminum part buried in the small contact hole, and a thin mask as thin as the unnecessary aluminum part is formed on the aluminum part buried in the large-area contact hole. As a result, when an attempt is made to remove the thin mask and expose its top surface in order to remove unnecessary aluminum, the thin mask on the top of the aluminum embedded in the large-area connection hole is also removed and its top surface is exposed. In other words, along with the removal of unnecessary aluminum,
This is because the aluminum embedded in the large-area contact hole and the lower layer wiring below it are partially removed, resulting in poor electrical connection between the lower layer wiring and the upper layer wiring in that portion.

The inventor of the present invention was able to obtain the result through experiments that the above-mentioned problem occurs when the diameter of the large-area connecting hole is about 8 [μm] or more, although it varies depending on the manufacturing process conditions.

[Purpose of the invention]

An object of the present invention is to provide technical means that can improve the electrical connection between lower layer wiring and upper layer wiring, especially in large-area contact holes.

Another object of the present invention is to provide technical means that can improve the electrical reliability in the connection hole between lower layer wiring and lower layer wiring.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, in a lower layer wiring having a connection hole in a predetermined upper part thereof, photo-etching is performed after forming a layer made of a conductive metal between the lower layer wiring and a layer made of a conductive metal for filling the connection hole. By providing a layer made of a conductive material that is difficult to be etched by the process, the lower layer wiring is not etched by the photoetching process, especially in large-area contact holes, so that good electrical connection between the lower layer wiring and the upper layer wiring can be achieved. It is something to do.

The configuration of the present invention will be explained together with examples.

In this embodiment, a case where the present invention is applied to an IC having a multilayer wiring structure will be described.

In all the figures, parts having the same functions are designated by the same reference numerals, and their explanations will not be repeated.

〔Example〕

FIG. 1 is a sectional view of a main part showing a micro connection hole and a large area connection hole in the same cross section for explaining the present invention in detail.

In FIG. 1, reference numeral 1 denotes a semiconductor substrate (hereinafter referred to as substrate) made of single-crystal silicon, which is used to form a small contact hole and a large-area contact hole, which will be described later. Semiconductor elements and the like constituting a logic circuit are provided, and are for constituting an IC. 2
is an insulating layer formed on the upper surface of the substrate 1, and is mainly used to electrically insulate first-layer wiring, which will be described later, from semiconductor elements provided on the substrate 1.

3A and 3B are first layer wirings made of aluminum or aluminum alloy, for example.

The power supply wiring 3A is mainly attached to a predetermined upper surface portion of the insulating layer 20 between the semiconductor element component regions of the substrate 10, and is provided in plural lengths, for example, a bonding pad provided around the substrate 10 (not shown) and logic It is used to electrically connect semiconductor elements for configuring a circuit and to flow a relatively large current required to operate the logic circuit. A plurality of fine wirings 3B are provided extending mainly on a predetermined upper surface portion of the insulating layer 20 between the semiconductor elements of the substrate 10, and are used to electrically connect the semiconductor elements.

4 is an interlayer insulating layer provided on the top of the substrate 1 to cover the wirings 3A and 3B, and is mainly used to electrically insulate the first layer wirings 3A and 3B from the second layer wirings to be described later. .

5A is an insulating layer 4 between the eyebrows at a predetermined upper part of the first layer power supply wiring 3A.
This is a large-area connection hole formed by selectively removing , and is for electrically connecting the first-layer power supply wiring 3A and the second-layer power supply wiring to be described later. Reference numeral 5B denotes a micro connection hole formed by selectively removing the interlayer insulating layer 4 above a predetermined portion of the first-layer micro-wiring 3B, so that the first-layer micro-wiring 3B and the second-layer micro-wiring described later It is for electrical connection.

6 is an anti-etching member made of, for example, titanium-tungsten alloy or copper. The etching prevention member 6 has a connecting hole 5A,
15B, the first layer wiring 3A is not bound by the interlayer insulating layer 4.

In particular, the wiring 3A on which the wide contact hole 5A is provided above is etched by the photo-etching process that is performed after forming the contact hole 5AK burying layer (to be described later). The etching prevention member 6 is made of a conductive material that is difficult to be etched by the photo-etching process performed after forming the connection hole filling layer.The etching prevention member 6
Due to the manufacturing process, the power supply wiring 3 in the large-area connection hole 5A
In addition to being provided on the upper part of A, K is also provided on the upper surface of the fine wiring 3B in the fine connection hole 5B. From this, the film thickness of the etching prevention member 6 and the material for constructing it are the same as that of the first layer wiring 3A.

It is determined so as not to cause a problem with the resistance value of 3B and the second layer wiring, which will be described later. The anti-etching member 6 is made of a conductive material that has good adhesion to the first layer wirings 3A and 3B, and also has good adhesion to the multi-hole filling layer described later. be done. Note that the etching prevention member 6 is not provided in the central portion of the large-area connecting hole 5A. The reason for this will be explained later.

Reference numeral 7 denotes a contact hole burying layer made of aluminum or aluminum alloy that is provided to fill the contact holes 5A and 5B, and alleviates the steep step difference in the contact holes 5A and 5BK, and provides electrical connection between the lower layer wiring and the upper layer wiring. This is to improve the quality of the product.

The second-layer power supply wiring 8A made of aluminum or aluminum alloy is provided on the upper surface of the insulating layer between the connection hole 5A and, for example, a connection hole of another first-layer power supply wiring (not shown). This is for electrically connecting the first layer power supply wiring through the connection hole. The second layer fine wiring 8B made of aluminum or aluminum alloy is
It is provided on the upper surface of the insulating layer 4 between the connection hole 5B and, for example, a connection hole of another first-layer fine wiring (not shown), and electrically connects a plurality of first-layer fine wirings through the connection hole. It is for connecting to. 8A may also be connected to a bonding pad. Reference numeral 9 denotes an insulating layer made of, for example, a phosphor silicate glass layer, which is provided so as to cover the upper surface of the IC, and is mainly used to protect the second layer wirings 8A and 8B from the outside.

Next, the specific manufacturing method of this example will be explained.

FIG. 2 is a reverse mold. FIG. 6 is a sectional view of a main part mainly showing connection holes in each manufacturing process for detailed explanation of the present invention.

First, a substrate 1 is prepared. After semiconductor elements and the like are formed on the main surface of the substrate 1, an insulating layer 2 is formed. The insulating layer 2 can be formed using thermal oxidation technology or chemical vapor deposition (hereinafter referred to as CV).
It is sufficient to use a silicon oxide layer based on technology (referred to as D).

A first-layer power supply wiring 3A and fine wiring 3B are formed in a predetermined region on the upper surface of the insulating layer 2 to a thickness of approximately 1 [μm]. A layer made of aluminum or an aluminum alloy is formed using a sputter deposition technique so as to cover the upper surface of the insulating layer 2. Then, dry etching technology may be used to pattern the first layer wiring according to the pattern trap.

After that, an insulating layer 4 is formed. This uses a layer made of silicon oxide, etc. formed by sputtering, and the film thickness is 1.
It may be formed to have a thickness of about 3 [μm].

Next, the insulating layer 4 above a predetermined portion of the first layer wirings 3A and 3B.
are selectively removed to form connection holes 5A and 5B. Then, as shown in FIG. 2, a layer made of a conductive material such as a titanium-tungsten alloy or copper is deposited on the exposed portions of the first layer 3A and 3B and the surface of the insulating layer 40 using a sputter deposition technique. 6A is formed to a thickness of about 1000 to 20001).

Next, as shown in FIG. 3, contact hole filling layers 7 and 7A made of aluminum or aluminum alloy are formed by vertical evaporation technique to cover the layer 6A made of the conductive material in order to fill the contact holes 5A and 5B. Form using. At this time, the layer 7 is formed so as to break at the difference portion that occurs on the surface of the insulating layer 4. Furthermore, a photoresist layer 10 is formed to cover the upper surface. At this time, the photoresist layer 1o above the layer 7 made of aluminum or aluminum alloy in the connection hole 5B is formed thicker than the photoresist layer 1° formed on the insulating layer 4. On the other hand, the photoresist layer 10 above the layer 7 made of aluminum or aluminum alloy in the connection hole 5A
Due to its nature, the thickness of the photoresist layer 10 formed on the insulating layer 4 is the same.

Next, the photoresist layer 10 is removed from its upper surface so that the unnecessary upper surface of the layer 7A made of aluminum or aluminum alloy is exposed. For this reason, the fourth
As shown in the figure, the photoresist layer 10 remains on the upper part of the contact hole 5B, but the photoresist layer 10 does not remain in the center of the contact hole 5A, so the contact hole filling layer 7 in the center of the contact hole 5A is exposed.

Next, as shown in FIG. 5, the unnecessary layer 7A of aluminum or aluminum alloy on the upper part of the insulating layer 4 is removed using an etching technique. At this time, the connection hole filling layer 7 at the center of the connection hole 5A is also etched. Since there is an etching prevention member 6 under the connection hole filling layer 7, the first layer wiring 3A will not be etched. This is because the conductive material constituting the etching stopper member 6 is difficult to be etched by the etching solution used in the etching step.

After the step shown in FIG. 5, as shown in FIG. 6, the unnecessary etching prevention member 6 on the upper part of the insulating layer 4 is removed.

This is to prevent the first layer wirings 3A and 3B from being electrically short-terminated. Although the anti-etching member 6 remains in the connecting holes 5A and 5B, this does not cause a problem with the resistance of the connecting holes 5A and 5B.

The film thickness of the etching prevention member 6 is 1000 to 2000 [λ]
This is because it is thin and made of a conductive material such as titanium-tungsten alloy or copper. At the same time, the connection hole 5
The exposed anti-etching material 6 in A is selectively removed.

After the process shown in FIG. 6, the second layer wiring 8A is formed.

8B is formed using the same technique as the first-layer wirings 3A and 3B, and a protective layer 9 is formed to cover the top of the wiring. The protective layer 9 may be formed of, for example, a layer of Phos-7 ossilicate glass using CVD technology.

Through these series of manufacturing steps, the IC of this example is completed.

〔effect〕

The following effects can be obtained in an IC having a relatively large diameter connection hole such as a power supply wiring connection hole.

+11 By providing the anti-etching member on the upper surface of the lower layer wiring, the lower layer wiring is not etched in the subsequent photo-etching process, and the electrical connection between the lower layer wiring and the upper layer wiring is prevented in the connection hole. The effect of improving the condition can be obtained.

+22 By providing the anti-etching member on the upper surface of the lower layer wiring, the lower layer wiring is not etched in the subsequent photo-etching process, which has the effect of further improving the planarization of the upper surface of the IC. .

(31 above, Ill, 12) provides the effect that the reliability of the IC can be improved.

Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the above-mentioned Examples, and it is possible to make various changes without departing from the gist of the invention. Not even. .

For example, in the above embodiment, the etching prevention member was formed after forming the connection hole filling layer, but the etching prevention member was formed after forming the layer made of the conductive material for forming the first layer wiring. A conductive layer for etching prevention may be formed at the same time as the step of patterning the first layer wiring using a dry etching technique.

Further, in the above embodiments, the etching prevention member is made of a titanium-tungsten alloy or copper, but it may also be made of a copper alloy or tantalum. A conductive material that has a different etching rate from the contact hole filling layer and does not significantly increase the resistance value of the contact hole is sufficient.
A) may be a connection hole in the bonding pad portion.

[Application field]

In the above explanation, the invention made by the present inventor was mainly applied to the multilayer wiring technology of semiconductor devices, which is the background field of application, but the invention is not limited thereto. It can be applied to multilayer wiring technology, etc.

Furthermore, although the above embodiment describes an IC having a two-layer wiring structure, the present invention is not limited to the two-layer wiring structure (it may include a three-layer wiring structure or a multi-layer wiring structure). It may also be applied to ICs.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a main part showing that lower layer wiring and upper layer wiring are electrically connected through connection holes for explaining the present invention in detail, FIG. It is a main part cross-sectional part mainly showing the connection hole part in each manufacturing process for demonstrating the specific manufacturing method of an example. DESCRIPTION OF SYMBOLS 1... Substrate, 2... Insulating layer, 3A, 3B... 1st layer wiring, 4... Interlayer insulating layer, 5A, 5B... Connection hole, 6... Erosion prevention member, 7 , 7A... Connection hole filling layer, 8A, 8B... Second layer wiring, 9... Protective layer, 1o... Photoresist layer. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6

Claims (1)

[Claims] 1. A first wiring formed by a first conductive layer provided on the upper main surface of the substrate, and a second layer provided above the first conductive layer with an insulating layer interposed therebetween. a second wiring constituted by a second conductive layer; a connection hole provided in the insulating layer above a predetermined portion of the first wiring for electrically connecting to the second wiring; and a third conductive layer provided to electrically connect with the second wiring and fill the inside of the connection hole, the multilayer wiring member comprising: a top surface of the first wiring in the connection hole; A multilayer wiring member comprising: a fourth conductive layer made of a conductive material different from that of the third conductive layer. 2. A claim characterized in that the fourth conductive layer is for preventing the first wiring from being etched by an unnecessary etching process of the third conductive layer outside the connection hole. The multilayer wiring member according to item 1.