KR20010001159A - Wafer level chip scale package using via hole and manufacturing method for the same - Google Patents
Wafer level chip scale package using via hole and manufacturing method for the same Download PDFInfo
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- KR20010001159A KR20010001159A KR1019990020204A KR19990020204A KR20010001159A KR 20010001159 A KR20010001159 A KR 20010001159A KR 1019990020204 A KR1019990020204 A KR 1019990020204A KR 19990020204 A KR19990020204 A KR 19990020204A KR 20010001159 A KR20010001159 A KR 20010001159A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Abstract
Description
본 발명은 웨이퍼 레벨 칩 스케일 패키지(WL-CSP ; Wafer level chip scale package) 및 그 제조방법에 관한 것이며, 더욱 구체적으로는 웨이퍼를 관통하는 비아 홀(Via hole)을 이용하여 반도체 칩의 활성면의 반대편에 솔더 볼(Solder ball)과 같은 외부 접속 단자를 형성한 것을 특징으로 하는 비아 홀을 이용한 웨이퍼 레벨 칩 스케일 패키지 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wafer level chip scale package (WL-CSP) and a method of manufacturing the same. More specifically, the present invention relates to an active surface of a semiconductor chip using via holes penetrating through a wafer. The present invention relates to a wafer level chip scale package using a via hole and a method of manufacturing the same, wherein an external connection terminal such as a solder ball is formed on the opposite side.
반도체 소자 제조기술이 발전함에 따라 전통적인 플라스틱 패키지는 경박단소화되는 경향을 보이고 있다. 리드 프레임(Lead frame)을 이용한 플라스틱 패키지의 일부분은 기판(Substrate)과 솔더 볼들을 이용한 비지에이(BGA ; Ball Grid Array) 패키지 형태로 발전되었으며, 다시 반도체 칩과 크기 면에서 거의 비슷한 칩 스케일 패키지(CSP ; Chip Scale Package) 형태로 발전되었다.As semiconductor device manufacturing technology develops, traditional plastic packages tend to be light and short. Part of the plastic package using the lead frame has been developed into a ball grid array (BGA) package using a substrate and solder balls, and again a chip scale package that is almost similar in size to a semiconductor chip. It was developed in the form of CSP (Chip Scale Package).
또한, 기판을 관통하는 도전성의 비아 홀(Via hole)을 형성함으로써 기판의 상하면(상하면에 형성된 금속 배선 및 볼 패드들 등)을 전기적으로 연결하거나 또는 다층의 금속 배선을 형성할 수 있었다.In addition, by forming conductive via holes penetrating the substrate, the upper and lower surfaces of the substrate (such as metal wirings and ball pads formed on the upper and lower surfaces) may be electrically connected, or multilayer metal wirings may be formed.
도 1은 비아 홀을 이용한 종래의 비지에이 패키지(100)를 도시한 단면도이다. 도 1을 참고하여 이를 설명하면 다음과 같다.1 is a cross-sectional view illustrating a conventional BG package 100 using a via hole. Referring to Figure 1 will be described as follows.
종래의 비지에이 패키지(100)는 금속 배선이 형성된 기판(20)의 상면에 반도체 칩(10)이 실장되고 본딩 와이어를 통해 전기적으로 연결되며, 기판(20)의 하면의 볼 패드들에 각각 솔더 볼들(50)이 부착되어 있다.In the conventional BG package 100, a semiconductor chip 10 is mounted on an upper surface of a substrate 20 on which metal wires are formed and electrically connected through a bonding wire, and soldered to ball pads on a lower surface of the substrate 20, respectively. The balls 50 are attached.
반도체 칩(10)을 포함하는 기판(20)의 상면 위로 에폭시(Epoxy)와 같은 봉지수단(40)이 봉지되어 외부환경으로부터 전기적 연결부분을 보호하며, 기판의 상면 금속 배선과 하면 볼 패드들은 비아 홀(30)을 통하여 전기적으로 연결되고, 이에 반도체 칩이 외부 접속 단자인 솔더 볼들을 통해 외부와 접속되는 구조이다.An encapsulation means 40 such as epoxy is encapsulated above the upper surface of the substrate 20 including the semiconductor chip 10 to protect the electrical connection from the external environment. Electrically connected through the hole 30, the semiconductor chip is connected to the outside through the solder balls, which are external connection terminals.
위에서 설명한 바와 같이, 종래의 비아 홀은 기판과 같은 반도체 칩이 실장되는 부재에 형성되며, 비아 홀을 이용하여 상/하면이 전기적으로 연결됨으로써 패키지 실장 영역이 최소화될 수 있었다.As described above, the conventional via hole is formed in a member on which a semiconductor chip such as a substrate is mounted, and the package mounting area may be minimized by electrically connecting the upper and lower surfaces using the via hole.
최근에는 웨이퍼 제조공정(Fabrication)을 통하여 칩 스케일 패키지를 직접 제조하는 기술이 개발되고 있으며, 이러한 기술을 통하여 제조되는 패키지를 소위 웨이퍼 레벨 칩 스케일 패키지(WL-CSP)라고 한다.Recently, a technique for directly manufacturing a chip scale package through a wafer fabrication process has been developed, and a package manufactured through such a technique is called a wafer level chip scale package (WL-CSP).
이러한 웨이퍼 레벨 칩 스케일 패키지는 반도체 칩의 활성면에 솔더 볼들이 형성되는 것이 일반적이며, 이러한 구조에 따라 웨이퍼 레벨 칩 스케일 패키지를 적층하거나 또는 전하결합소자(CCD ; Charge Coupled Device)와 같은 센서 패키지 (Sensor Package) 등의 제작에 응용할 때 구조적으로 상당한 어려움이 뒤따르게 되었다.In the wafer level chip scale package, solder balls are generally formed on the active surface of the semiconductor chip, and according to the structure, a wafer package may be stacked or a sensor package (such as a charge coupled device (CCD)). When applied to fabrication of sensor package, etc., considerable structural difficulties have been followed.
본 발명의 목적은 본딩패드가 형성되지 않은 반도체 칩의 하면에 솔더 볼들을 형성하고, 본딩패드와 솔더 볼들을 전기적으로 연결한 것을 특징으로 하는 웨이퍼 레벨 칩 스케일 패키지 및 그 제조방법을 제공하는 것이다.Disclosure of Invention An object of the present invention is to provide a wafer level chip scale package and a method of manufacturing the same, wherein solder balls are formed on a lower surface of the semiconductor chip on which the bonding pads are not formed, and the bonding pads and the solder balls are electrically connected.
도 1은 종래의 비지에이 패키지를 도시한 단면도,1 is a cross-sectional view showing a conventional vijay package,
도 2는 본 발명의 일 실시예에 따른 비아 홀을 이용한 웨이퍼 레벨 칩 스케일 패키지를 도시한 부분 절개 사시도,2 is a partial cutaway perspective view of a wafer level chip scale package using via holes in accordance with an embodiment of the present invention;
도 3a 및 도 3b는 도 2의 평면도 및 배면도,3a and 3b are a plan view and a rear view of FIG.
도 4는 본 발명의 다른 실시예에 따른 웨이퍼 레벨 칩 스케일 패키지 제조방법을 순차적으로 도시한 순서도,4 is a flowchart sequentially illustrating a method of manufacturing a wafer level chip scale package according to another embodiment of the present invention;
도 5a 내지 도 5f는 도 4의 각 공정을 간략히 도시한 공정도이다.5A to 5F are process diagrams schematically illustrating the processes of FIG. 4.
〈도면의 주요 부분에 대한 설명〉<Description of Main Parts of Drawing>
10, 110, 210 : 반도체 칩 20 : 기판10, 110, 210: semiconductor chip 20: substrate
30, 260 : 비아 홀 40, 130, 230 : 봉지수단30, 260: via hole 40, 130, 230: sealing means
50, 150, 250 : 솔더 볼 100 : 비지에이 패키지50, 150, 250: Solder Ball 100: Vigie This Package
112, 212 : 본딩패드 114, 214 : 활성면112, 212: bonding pads 114, 214: active surface
116 : 하면 120, 220 : 전도성 라인116: lower surface 120, 220: conductive line
140, 240 : 금속 배선 200, 300 : 칩 스케일 패키지140, 240: metal wiring 200, 300: chip scale package
242 : 볼 패드 270 : 웨이퍼242: ball pad 270: wafer
272 : 스크라이빙 라인272: Scribing Line
이러한 목적을 달성하기 위하여 본 발명은 본딩패드들이 형성된 활성면과 반대면의 하면을 갖는 반도체 칩과; 활성면과 하면을 전기적으로 연결하며, 반도체 칩의 측면들을 따라 형성된 전도성 라인과; 전도성 라인을 통하여 임의의 본딩패드에 전기적으로 연결되고 하면에서 임의의 본딩패드에 대응되는 볼 패드를 형성하는 금속 배선과; 본딩패드들, 금속 배선 및 전도성 라인을 봉지하는 봉지수단; 및 볼 패드 위에 각각 형성되는 솔더 볼들;을 포함하는 칩 스케일 패키지에 있어서, 전도성 라인은 반도체 칩들이 구비된 웨이퍼 레벨에서 스크라이빙 라인을 따라 형성된 비아 홀을 이용함으로써 형성되는 것을 특징으로 하는 웨이퍼 레벨 칩 스케일 패키지를 제공한다.In order to achieve the above object, the present invention provides a semiconductor chip comprising a bottom surface opposite to an active surface on which bonding pads are formed; Conductive lines electrically connecting the active surface and the bottom surface, the conductive lines being formed along side surfaces of the semiconductor chip; A metal wire electrically connected to any bonding pad through a conductive line and forming a ball pad at a lower surface corresponding to the bonding pad; Encapsulation means for encapsulating bonding pads, metal lines and conductive lines; And solder balls respectively formed on the ball pads, wherein the conductive lines are formed by using via holes formed along the scribing line at the wafer level where the semiconductor chips are provided. Chip scale packages are available.
또한, 위와 같은 목적을 달성하기 위하여 본 발명은 위와 같은 웨이퍼 레벨 칩 스케일 패키지를 제조하는 방법에 있어서, 반도체 칩들이 구비된 웨이퍼를 준비하는 단계와; 본딩패드와 볼 패드들에 각기 연결되는 금속 배선들을 형성하는 단계와; 웨이퍼의 스크라이빙 라인을 따라 다수의 비아 홀을 형성하는 단계와; 비아 홀의 내부에 전도성 라인을 형성하는 단계와; 스크라이빙 라인을 따라 반도체 칩들을 분리시키는 단계와; 볼 패드들을 제외한 반도체 칩을 봉지하는 단계; 및 볼 패드들 위로 각각 솔더 볼을 형성하는 단계;를 포함하는 웨이퍼 레벨 칩 스케일 패키지 제조방법을 제공한다.In addition, to achieve the above object, the present invention provides a method for manufacturing a wafer-level chip scale package as described above, comprising the steps of: preparing a wafer with semiconductor chips; Forming metal wires respectively connected to the bonding pads and the ball pads; Forming a plurality of via holes along the scribing line of the wafer; Forming a conductive line in the via hole; Separating the semiconductor chips along the scribing line; Encapsulating the semiconductor chip except for the ball pads; And forming solder balls on the ball pads, respectively.
이하, 첨부 도면을 참조하여 본 발명의 바람직한 실시예들을 설명하면 다음과 같다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.
도 2는 본 발명의 일 실시예에 따른 비아 홀을 이용한 웨이퍼 레벨 칩 스케일 패키지(200)를 도시한 부분 절개 사시도이며, 도 3a 및 도 3b는 도 2의 웨이퍼 레벨 칩 스케일 패키지(200)를 도시한 평면도 및 배면도이다. 도 2 내지 도 3b를 참조하여 본 발명에 따른 웨이퍼 레벨 칩 스케일 패키지(200)를 설명한다.2 is a partial cutaway perspective view of a wafer level chip scale package 200 using via holes in accordance with one embodiment of the present invention, and FIGS. 3A and 3B illustrate the wafer level chip scale package 200 of FIG. 2. One top view and one rear view. 2 to 3B, a wafer level chip scale package 200 according to the present invention will be described.
본 발명에 따른 웨이퍼 레벨 칩 스케일 패키지(200)는 본딩패드들(112)이 형성된 반도체 칩(110)의 활성면(114)에 본딩패드들과 연결되는 금속 배선들(140)이 형성되어 있으며, 활성면(114)의 반대면인 하면(116)에 볼 패드들(도시되지 않음)이 형성되어 각 볼 패드들 위로 솔더 볼들(150)이 형성되어 있다.In the wafer level chip scale package 200 according to the present invention, metal wires 140 connected to the bonding pads are formed on the active surface 114 of the semiconductor chip 110 on which the bonding pads 112 are formed. Ball pads (not shown) are formed on the bottom surface 116 opposite to the active surface 114 to form solder balls 150 over the respective ball pads.
반도체 칩(110)의 측면을 따라 활성면의 금속 배선(140)과 하면의 볼 패드를 전기적으로 연결시키는 전도성 라인(120)이 형성되어 있으며, 볼 패드들을 제외한 반도체 칩(110)이 사진 공정에서의 감광물질 - 포토 솔더 레지스트(PSR ; Photo Solder Resist)와 같은 봉지수단(230)으로 봉지되어 있다.Conductive lines 120 are formed along the side surfaces of the semiconductor chip 110 to electrically connect the metal wires 140 on the active surface and the ball pads on the bottom surface thereof. It is encapsulated with a sealing means 230 such as a photosensitive material of the photo-solder resist (PSR).
이때, 전도성 라인(120)은 반도체 칩들이 구비된 웨이퍼 레벨에서 스크라이빙 라인을 따라 형성된 비아 홀을 이용함으로써 형성되는 것을 특징으로 한다. 이와 같이 웨이퍼 레벨에서 반도체 칩을 관통하는 비아 홀을 형성하는 기술은 소위 MEMS(MicroElectroMechanical Systems)라 칭하는 극소 전자 기계 시스템을 통하여 달성될 수 있다.In this case, the conductive line 120 is formed by using via holes formed along the scribing line at the wafer level where the semiconductor chips are provided. As such, the technique of forming via holes penetrating through the semiconductor chip at the wafer level can be achieved through a microelectromechanical system called MEMS (MicroElectroMechanical Systems).
좀 더 상세히 설명하면, 레이저 드릴(Laser drill)과 같은 장치를 이용하거나 또는 기존의 식각 기술을 이용하여 원하는 형태의 비아 홀을 형성할 수 있다.In more detail, a via hole of a desired shape may be formed by using an apparatus such as a laser drill or using an existing etching technique.
이러한 경우, 웨이퍼의 두께는 일반적인 웨이퍼의 두께인 약 320㎛보다 작게 형성하는 것이 유리하며, 실제 가공을 위해서는 약 50㎛ 내지 100㎛의 두께로 형성하는 것이 바람직하다. 예를 들어, 반도체 칩을 직접 적층하기 위한 웨이퍼(Wafer for die stack)의 두께는 약 50㎛로 형성될 수 있다.In this case, it is advantageous to form the thickness of the wafer to be smaller than about 320 μm, which is the thickness of a general wafer, and for actual processing, it is preferable to form the thickness of about 50 μm to 100 μm. For example, a thickness of a wafer for directly stacking semiconductor chips may be formed to about 50 μm.
이러한 구조의 웨이퍼 레벨 칩 스케일 패키지는 기존의 활성면 위로 배선을 재배열한 후 솔더 볼들을 실장하는 구조에 비하여 솔더 볼 배치의 자유도를 갖게 되어, 웨이퍼 레벨 칩 스케일 패키지를 응용함에 있어 유리한 면을 갖는다.The wafer level chip scale package of this structure has a degree of freedom in solder ball placement compared to a structure in which the solder balls are mounted after rearranging the wiring on the existing active surface, which is advantageous in applying a wafer level chip scale package.
도 4는 본 발명의 다른 실시예에 따른 웨이퍼 레벨 칩 스케일 패키지 제조방법을 순차적으로 도시한 순서도이며, 도 5a 내지 도 5f는 도 4의 각 공정을 간략히 도시한 공정도이다. 도 4 내지 도 5f를 참고로 하여 이를 설명하면 다음과 같다.4 is a flowchart sequentially illustrating a method for manufacturing a wafer level chip scale package according to another embodiment of the present invention, and FIGS. 5A to 5F are process diagrams briefly illustrating respective processes of FIG. 4. This will be described below with reference to FIGS. 4 to 5F.
도 4에 따르면, 본 발명에 따라 비아 홀을 이용한 웨이퍼 레벨 칩 스케일 패키지 제조방법은 반도체 칩들이 구비된 웨이퍼를 준비하는 단계(180)와, 금속 배선을 형성하는 단계(182)와, 다수의 비아 홀들을 형성하는 단계(184)와, 비아 홀 내부에 전도성 라인을 형성하는 단계(186)와, 개개의 반도체 칩으로 분리하는 단계(188)와, 봉지하는 단계(190) 및 반도체 칩의 하면에 솔더 볼을 형성하는 단계(192)를 포함한다.Referring to FIG. 4, a method of manufacturing a wafer level chip scale package using via holes according to the present invention includes preparing a wafer having semiconductor chips (180), forming metal wiring (182), and a plurality of vias. Forming holes 184, forming conductive lines in the via holes 186, separating them into individual semiconductor chips 188, encapsulating 190 and bottom surfaces of the semiconductor chips. Step 192 of forming solder balls.
이와 같은 제조공정을 도 5a 내지 도 5f를 참고로 하여 설명한다.Such a manufacturing process will be described with reference to FIGS. 5A to 5F.
먼저, 본딩패드들(212)이 활성면(214)에 형성된 반도체 칩들(210)이 스크라이빙 라인(272)을 통하여 구분된 웨이퍼(270)가 준비된다(도 5a), 본딩패드들과 연결되는 금속 배선들(240)과 볼 패드들(242)이 반도체 칩(210) 위로 형성되며(도 5b), 웨이퍼(270)의 스크라이빙 라인(272)을 따라 다수개의 비아 홀들(260)이 형성된다(도 5c).First, the wafer 270 in which the semiconductor chips 210 having the bonding pads 212 formed on the active surface 214 are separated through the scribing line 272 is prepared (FIG. 5A) and connected to the bonding pads. Metal wires 240 and ball pads 242 are formed over the semiconductor chip 210 (FIG. 5B), and a plurality of via holes 260 are formed along the scribing line 272 of the wafer 270. Formed (FIG. 5C).
비아 홀들(260)은 소위 MEMS 기술을 통하여 웨이퍼(270)를 관통하여 형성될 수 있으며, 각 비아 홀(260) 내부에 구리(Cu)와 같은 전도성 라인(220)을 형성한 후 감광물질- 포토 솔더 레지스트(PSR)와 같은 봉지수단(230)으로 채워진다(도 5d). 이때, 웨이퍼(270)의 두께는 약 50㎛ 내지 100㎛의 범위 내로 형성되는 것이 바람직하며, 비아 홀들은 레이저 드릴링(Laser drilling) 또는 식각 기술(Etching technology) 등을 이용하여 형성될 수 있다.Via holes 260 may be formed through the wafer 270 through a so-called MEMS technique, and after the conductive lines 220 such as copper (Cu) are formed in each via hole 260, a photosensitive material-photo It is filled with sealing means 230, such as solder resist PSR (FIG. 5D). In this case, the thickness of the wafer 270 is preferably formed in the range of about 50 μm to 100 μm, and the via holes may be formed using laser drilling or etching technology.
이와 같이, 본딩패드(212)와, 금속 배선(240)과, 전도성 라인(220) 및 볼 패드(242)가 전기적으로 연결된 상태의 반도체 칩(210)들이 쏘잉(Sawing) 공정을 통하여 웨이퍼에서 개개로 분리되며(도 5e), 분리된 반도체 칩(210)이 볼 패드를 제외한 표면에 감광물질(PSR)과 같은 봉지수단(230)으로 봉지되고, 마지막으로 봉지수단(230)에서 노출된 볼 패드들 위로 각각 솔더 볼들(250)이 형성됨으로써 웨이퍼 레벨 칩 스케일 패키지(300)가 제조된다.As such, the semiconductor chips 210 having the bonding pads 212, the metal wires 240, the conductive lines 220, and the ball pads 242 electrically connected to each other are individually separated from the wafer through a sawing process. 5E, the separated semiconductor chip 210 is encapsulated with an encapsulation means 230 such as a photosensitive material PSR on a surface except the ball pad, and finally the ball pad exposed from the encapsulation means 230. Wafer level chip scale package 300 is fabricated by forming solder balls 250 over each of them.
위와 같은 제조방법에서, 전도성 라인이 형성된 비아 홀 내부로 감광물질이 충진되는 공정은 도팅(Dotting) 공정을 통해 수행될 수 있으며, 개개로 분리된 반도체 칩의 표면을 감광물질로 봉지하는 공정은 디핑(Dipping) 공정을 통해 수행되는 것이 일반적이다. 여기서, 디핑 공정이란 개개의 반도체 칩을 액상의 감광물질이 담긴 용기 내에 잠기게 함으로써 봉지하는 공정이다.In the above manufacturing method, the process of filling the photosensitive material into the via hole in which the conductive line is formed may be performed through a dotting process, and the process of encapsulating the surface of the separated semiconductor chip with the photosensitive material is dipping. It is generally carried out through a dipping process. Here, the dipping step is a step of encapsulating each semiconductor chip by immersing it in a container containing a liquid photosensitive material.
이상에서 설명한 바와 같이, 비아 홀을 이용함으로써 반도체 칩의 하면에 솔더 볼들이 구비된 칩 스케일 패키지를 웨이퍼 레벨에서 제조할 수 있으며, 특히 개개의 반도체 칩으로 분리하기 전까지의 공정이 웨이퍼 레벨에서 수행되기 때문에 양산성이 우수한 칩 스케일 패키지를 제조할 수 있다.As described above, by using the via hole, a chip scale package having solder balls on the lower surface of the semiconductor chip can be manufactured at the wafer level, and in particular, the process until separation into individual semiconductor chips is performed at the wafer level. As a result, it is possible to manufacture a chip scale package having excellent mass productivity.
본 발명에 따른 웨이퍼 레벨 칩 스케일 패키지 및 그 제조방법은 웨이퍼 제조공정 중에 웨이퍼를 관통하는 비아 홀을 형성하고, 형성된 비아 홀을 이용하여 반도체 칩의 하면에 솔더 볼을 형성한 것을 그 구조적 특징으로 하며, 이러한 특징에 따라 칩 스케일 패키지를 적층할 수 있는 등 칩 스케일 패키지의 응용 범위를 확장할 수 있고, 또한 비아 홀을 형성함에 있어 비아 홀의 형성 위치를 반도체 칩들의 경계부분인 스크라이빙 라인으로 대부분의 제조공정이 웨이퍼 레벨에서 수행됨에 따라 양산성이 우수한 칩 스케일 패키지를 제조할 수 있다.Wafer-level chip scale package and a method of manufacturing the same according to the present invention is characterized in that the via hole penetrating the wafer during the wafer manufacturing process, and the solder ball formed on the lower surface of the semiconductor chip using the formed via hole According to this characteristic, the application range of the chip scale package can be extended, such as stacking the chip scale package, and the formation position of the via hole is mostly formed by the scribing line which is the boundary of the semiconductor chips. As the manufacturing process is performed at the wafer level, it is possible to manufacture a chip scale package having excellent mass productivity.
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100708872B1 (en) * | 2004-09-08 | 2007-04-17 | 디엔제이 클럽 인코 | packaged integrated circuit device |
| US7276799B2 (en) | 2003-08-26 | 2007-10-02 | Samsung Electronics Co., Ltd. | Chip stack package and manufacturing method thereof |
| KR100817050B1 (en) * | 2005-08-26 | 2008-03-26 | 삼성전자주식회사 | Method of manufacturing package of wafer level semiconductor chip |
| KR100914980B1 (en) * | 2007-10-23 | 2009-09-02 | 주식회사 하이닉스반도체 | Stacked semiconductor package |
| US7595559B2 (en) | 2004-07-27 | 2009-09-29 | Samsung Electronics Co., Ltd. | Integrated circuit chip having pass-through vias therein that extend between multiple integrated circuits on the chip |
| US7998861B2 (en) | 2008-11-28 | 2011-08-16 | Electronics And Telecommunications Research Institute | Method of manufacturing through-via |
| US8319324B2 (en) | 2006-12-05 | 2012-11-27 | Samsung Electronics Co., Ltd. | High I/O semiconductor chip package and method of manufacturing the same |
| US8400576B2 (en) | 2003-02-04 | 2013-03-19 | Plastic Logic Limited | Transistor-controlled display devices |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR101012701B1 (en) | 2002-11-25 | 2011-02-09 | 삼성테크윈 주식회사 | Semiconductor package and manufacturing method of the same |
| US7955893B2 (en) | 2008-01-31 | 2011-06-07 | Alpha & Omega Semiconductor, Ltd | Wafer level chip scale package and process of manufacture |
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8400576B2 (en) | 2003-02-04 | 2013-03-19 | Plastic Logic Limited | Transistor-controlled display devices |
| US7276799B2 (en) | 2003-08-26 | 2007-10-02 | Samsung Electronics Co., Ltd. | Chip stack package and manufacturing method thereof |
| US7537959B2 (en) | 2003-08-26 | 2009-05-26 | Samsung Electronics Co., Ltd. | Chip stack package and manufacturing method thereof |
| US7977156B2 (en) | 2003-08-26 | 2011-07-12 | Samsung Electronics Co., Ltd. | Chipstack package and manufacturing method thereof |
| US8368231B2 (en) | 2003-08-26 | 2013-02-05 | Samsung Electronics Co., Ltd. | Chipstack package and manufacturing method thereof |
| US7595559B2 (en) | 2004-07-27 | 2009-09-29 | Samsung Electronics Co., Ltd. | Integrated circuit chip having pass-through vias therein that extend between multiple integrated circuits on the chip |
| KR100708872B1 (en) * | 2004-09-08 | 2007-04-17 | 디엔제이 클럽 인코 | packaged integrated circuit device |
| KR100817050B1 (en) * | 2005-08-26 | 2008-03-26 | 삼성전자주식회사 | Method of manufacturing package of wafer level semiconductor chip |
| US8319324B2 (en) | 2006-12-05 | 2012-11-27 | Samsung Electronics Co., Ltd. | High I/O semiconductor chip package and method of manufacturing the same |
| KR100914980B1 (en) * | 2007-10-23 | 2009-09-02 | 주식회사 하이닉스반도체 | Stacked semiconductor package |
| US7998861B2 (en) | 2008-11-28 | 2011-08-16 | Electronics And Telecommunications Research Institute | Method of manufacturing through-via |
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