KR102653531B1 - Semiconductor package - Google Patents

Abstract

The technical idea of the present invention is a support panel including a cavity; a semiconductor chip provided in the cavity of the support panel and including a semiconductor substrate and a chip pad; an encapsulant provided between a sidewall of the semiconductor chip and a sidewall of the support panel defining the cavity; and an insulating layer on the upper surface of the semiconductor chip and the upper surface of the support panel; and a conductive redistribution pattern extending on the upper surface of the insulating layer and electrically connected to the chip pad of the semiconductor chip, wherein the support panel has a thickness equal to or greater than the thickness of the semiconductor chip, and the support panel and the semiconductor chip have a thickness equal to or greater than the thickness of the semiconductor chip. The semiconductor substrate of the chip provides a semiconductor package containing the same material.

Description

Semiconductor package {SEMICONDUCTOR PACKAGE}

The technical idea of the present invention relates to a semiconductor package and a method of manufacturing the same, and more specifically, to a semiconductor package with a fan-out structure and a method of manufacturing the same.

In accordance with the rapid development of the electronics industry and user demands, electronic devices are becoming more compact, multi-functional, and high-capacity, and accordingly, highly integrated semiconductor chips are required. In particular, in highly integrated semiconductor chips with an increased number of input/output (I/O) terminals, the spacing between input/output terminals is reduced, which may cause interference between input/output terminals. In order to increase the spacing between input/output terminals, a fan-out semiconductor package is required. is being used.

The problem to be solved by the technical idea of the present invention is to provide a semiconductor package and a manufacturing method thereof.

In order to solve the above-described problem, the technical idea of the present invention is to include a support panel including a cavity; a semiconductor chip provided in the cavity of the support panel and including a semiconductor substrate and a chip pad; an encapsulant provided between a sidewall of the semiconductor chip and a sidewall of the support panel defining the cavity; and an insulating layer on the upper surface of the semiconductor chip and the upper surface of the support panel; and a conductive redistribution pattern extending on the upper surface of the insulating layer and electrically connected to the chip pad of the semiconductor chip, wherein the support panel has a thickness equal to or greater than the thickness of the semiconductor chip, and the support panel and the semiconductor chip have a thickness equal to or greater than the thickness of the semiconductor chip. The semiconductor substrate of the chip provides a semiconductor package containing the same material.

In example embodiments, the semiconductor substrate of the support panel and the semiconductor chip includes silicon.

In exemplary embodiments, the encapsulant covers a lower surface of the semiconductor chip, and the lower surface of the support panel is on the same plane as the lower surface of the encapsulant.

In exemplary embodiments, the lower surface of the support panel and the lower surface of the semiconductor chip are on the same plane, and the surface roughness of the lower surface of the support panel is the same as the surface roughness of the lower surface of the semiconductor chip.

In example embodiments, the cavity partially penetrates the support panel, and the support panel further includes a bottom surface supporting a bottom surface of the semiconductor chip.

In exemplary embodiments, the conductive pillar extends from the chip pad of the semiconductor chip to the upper surface of the insulating layer and electrically connects the chip pad of the semiconductor chip to the conductive redistribution pattern; , the insulating layer and the encapsulant are formed of the same material and are integrated into one body.

In exemplary embodiments, the encapsulant includes an epoxy molding compound.

In order to solve the above-described problem, the technical idea of the present invention includes preparing a support panel including a pocket portion extending from the upper surface; preparing a carrier substrate to which a semiconductor chip is attached, and attaching the carrier substrate to the upper surface of the support panel so that the semiconductor chip is accommodated in the pocket portion of the support panel; forming a hole in the support panel extending from a lower surface of the support panel and communicating with the pocket portion; forming an encapsulant to fill the hole of the support panel; separating the carrier substrate from the semiconductor chip and the support panel; and forming, on the support panel and the semiconductor chip, a redistribution structure including a conductive redistribution pattern electrically connected to a chip pad of the semiconductor chip.

In example embodiments, the support panel includes silicone.

In exemplary embodiments, after forming the redistribution structure, a polishing process is performed on the lower surface of the support panel and the lower surface of the encapsulant to reduce the thickness of the support panel and the thickness of the encapsulant. Includes.

In example embodiments, performing the polishing process includes removing a portion of the encapsulant to expose a lower surface of the semiconductor chip.

In order to solve the above-described problem, the technical idea of the present invention includes preparing a support panel including a cavity extending from the upper surface; placing a semiconductor chip with a conductive filler attached on a chip pad within the cavity of the support panel; forming a first insulating layer covering the sidewall and top surface of the semiconductor chip and covering the sidewall of the conductive filler; and forming, on the support panel and the semiconductor chip, a redistribution structure including a conductive redistribution pattern electrically connected to a chip pad of the semiconductor chip through the conductive filler. to provide.

According to exemplary embodiments of the present invention, the support panel is formed from a silicon wafer and may be made of the same material (eg, silicon) as the semiconductor substrate of the semiconductor chip. In this case, since the support panel and the semiconductor chip, which make up most of the semiconductor package, have a similar level of thermal expansion coefficient, the bending phenomenon that occurs due to the difference in thermal expansion coefficient between the components constituting the semiconductor package can be more easily prevented. You can control it.

1 is a cross-sectional view showing a semiconductor package according to exemplary embodiments of the present invention.
FIGS. 2A to 2N are cross-sectional views showing a method of manufacturing the semiconductor package shown in FIG. 1.
3 is a cross-sectional view showing a semiconductor package according to exemplary embodiments of the present invention.
4 is a cross-sectional view showing a semiconductor package according to exemplary embodiments of the present invention.
FIGS. 5A to 5K are cross-sectional views showing a method of manufacturing the semiconductor package shown in FIG. 4.

Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. However, the exemplary embodiments of the present disclosure may be modified in various other forms, and the scope of the present disclosure should not be construed as being limited to the embodiments described in detail below. It is preferred that the exemplary embodiments of the present disclosure be interpreted as being provided to more completely explain the concept of the present disclosure to those with average knowledge in the art. Identical symbols refer to identical elements throughout. Furthermore, various elements and areas in the drawings are schematically drawn. Accordingly, the concept of the present disclosure is not limited by the relative sizes or spacing drawn in the accompanying drawings.

Terms such as first, second, etc. may be used to describe various components, but the components are not limited by the terms. The above terms are used only for the purpose of distinguishing one component from another. For example, a first component may be named a second component, and conversely, the second component may be named a first component without departing from the scope of the present disclosure.

The terminology used in this disclosure is only used to describe specific embodiments and is not intended to limit the concept of this disclosure. Singular expressions include plural expressions unless the context clearly dictates otherwise. In this application, expressions such as “comprises” or “has” are intended to designate the presence of features, numbers, steps, operations, components, parts, or combinations thereof described in the specification, but are not intended to indicate the presence of one or more other features or It should be understood that this does not exclude in advance the possibility of the presence or addition of numbers, operations, components, parts, or combinations thereof.

Unless otherwise defined, all terms used herein, including technical terms and scientific terms, have the same meaning as commonly understood by those skilled in the art in the technical field to which the concept of the present disclosure pertains. Additionally, commonly used terms, as defined in dictionaries, should be interpreted to have meanings consistent with what they mean in the context of the relevant technology, and should not be used in an overly formal sense unless explicitly defined herein. It will be understood that this is not to be interpreted.

1 is a cross-sectional view showing a semiconductor package 10 according to exemplary embodiments of the present invention.

Referring to FIG. 1, the semiconductor package 10 includes a support panel 110, a semiconductor chip 120, an encapsulant 130, a redistribution structure 140, an external connection terminal 151, and a rear protective layer 170. ) may include. The semiconductor package 10 may be a semiconductor package with a fan-out structure in which the footprint of the semiconductor package 10 is larger than the footprint of the semiconductor chip 120.

The support panel 110 may include an upper surface 118 and a lower surface 119 that are opposed to each other. The support panel 110 may have a generally flat shape, and the upper surface 118 and lower surface 119 of the support panel 110 may each be flat. Hereinafter, the horizontal direction is defined as a direction (e.g., X direction and/or Y direction) parallel to the upper surface 118 of the support panel 110, and the vertical direction (e.g., Z direction) is defined as It is defined as a direction perpendicular to the upper surface 118 of (110) (for example, Z direction). In addition, the horizontal width of any member is defined as the length along the horizontal direction (for example, X direction and/or Y direction), and the vertical height or thickness of any member is defined as the length along the vertical direction (for example, Z direction). It is defined as the length according to the direction.

The support panel 110 may include a cavity 111 to accommodate the semiconductor chip 120. From a plan view, the shape of the cavity 111 may correspond to the shape of the semiconductor chip 120. For example, from a plan view, the cavity 111 and the semiconductor chip 120 may have a rectangular shape. In exemplary embodiments, the cavity 111 may extend from the upper surface 118 to the lower surface 119 of the support panel 110 and may penetrate the support panel 110 . In other example embodiments, cavity 111 extends from top surface 118 of support panel 110, but may partially penetrate support panel 110.

In example embodiments, the thickness of the support panel 110 may be equal to or greater than the thickness of the semiconductor chip 120 .

In example embodiments, the support panel 110 may include silicon (Si). For example, support panel 110 may be a bare silicon wafer. In other example embodiments, support panel 110 may include ceramic, plastic, polymer, glass, metal, etc.

The semiconductor chip 120 may be accommodated in the cavity 111 of the support panel 110. The semiconductor chip 120 may include an upper surface 128 and a lower surface 129 that are opposed to each other, and the upper surface 128 of the semiconductor chip 120 may be a pad surface provided with the chip pad 123. The sidewall of the semiconductor chip 120 is spaced apart from the sidewall of the support panel 110 defining the cavity 111, and an encapsulant 130 is filled between the sidewall of the semiconductor chip 120 and the sidewall of the support panel 110. A gap may form. In example embodiments, the top surface 128 of the semiconductor chip 120 and the top surface 118 of the support panel 110 may be on the same plane.

The semiconductor chip 120 may include a semiconductor substrate 121 including active and inactive surfaces that are opposed to each other. The active surface of the semiconductor substrate 121 is the surface adjacent to the upper surface 128 of the semiconductor chip 120, and the inactive surface of the semiconductor substrate 121 is the surface adjacent to the lower surface 129 of the semiconductor chip 120 or the semiconductor chip ( It may correspond to the lower surface 129 of 120). The semiconductor substrate 121 may include, for example, silicon. A semiconductor device layer may be formed on the active surface of the semiconductor substrate 121. A plurality of various types of individual devices may be formed in the semiconductor device layer. The chip pad 123 of the semiconductor chip 120 may be electrically connected to individual devices formed in the semiconductor device layer. For example, the plurality of individual devices may be microelectronic devices, such as a metal-oxide-semiconductor field effect transistor (MOSFET) such as a complementary metal-oxide-semiconductor transistor (CMOS transistor), a system large scale integration (LSI), etc. ), image sensors such as CIS (CMOS imaging sensor), MEMS (micro-electro-mechanical system), active elements, passive elements, etc. In example embodiments, the semiconductor chip 120 may be a memory chip. In example embodiments, the semiconductor chip 120 may be a logic chip.

The encapsulant 130 may be provided in the cavity 111 of the support panel 110. The encapsulant 130 may be filled between the sidewall of the semiconductor chip 120 and the sidewall of the support panel 110. The encapsulant 130 may contact the sidewall of the semiconductor chip 120 and the sidewall of the support panel 110, and may extend along the sidewall of the semiconductor chip 120 and the sidewall of the support panel 110. Additionally, the encapsulant 130 may cover the lower surface 129 of the semiconductor chip 120. In example embodiments, the top surface 138 of the encapsulant 130 may be on the same plane as the top surface 118 of the support panel 110 and/or the top surface 128 of the semiconductor chip 120. In example embodiments, the lower surface 139 of the encapsulant 130 may be on the same plane as the lower surface 119 of the support panel 110.

In example embodiments, the encapsulant 130 may be formed of insulating polymer, epoxy, or a combination thereof. In example embodiments, the encapsulant 130 may be formed from photo imageable dielectric (PID), or polyimide.

In example embodiments, encapsulant 130 may be formed of a molding material. In example embodiments, the encapsulant 130 may be formed of epoxy molding compound (EMC).

The redistribution structure 140 may be provided on the support panel 110 and the semiconductor chip 120. The redistribution structure 140 may include a conductive structure electrically connected to the semiconductor chip 121 and a redistribution insulating layer 141 covering the conductive structure. For example, the conductive structure may be a single-layer conductive layer or may include conductive layers with a multi-layer structure.

In example embodiments, the redistribution structure 140 may include a redistribution insulating layer 141, a first conductive redistribution pattern 143, and a second conductive redistribution pattern 145.

The redistribution insulating layer 141 may include a plurality of insulating layers sequentially stacked on the top surface 118 of the support panel 110 and the top surface 128 of the semiconductor chip 120. For example, the redistribution insulating layer 141 includes a first insulating layer 1411 laminated on the top surface 118 of the support panel 110 and the top surface 128 of the semiconductor chip 120, and a first insulating layer. It may include a second insulating layer 1413 stacked on (1411). The first insulating layer 1411 and the second insulating layer 1413 may be formed of insulating polymer, epoxy, or a combination thereof. In example embodiments, the first insulating layer 1411 and the second insulating layer 1413 may be formed from PID or polyimide.

In example embodiments, the redistribution insulation layer 141 and the encapsulant 130 may include the same material or a combination of the same materials. In example embodiments, the redistribution insulating layer 141 and the encapsulant 130 may be formed from the same insulating polymer. For example, the redistribution insulation layer 141 and the encapsulant 130 may be formed of polyimide.

The first conductive redistribution pattern 143 may be physically and electrically connected to the chip pad 123 of the semiconductor chip 120. The first conductive redistribution pattern 143 includes a conductive line pattern 1431 extending along the upper surface of the first insulating layer 1411 and a conductive via pattern 1433 extending through the first insulating layer 1411. It can be included. The conductive line pattern 1431 may be covered by the second insulating layer 1413. The conductive via pattern 1433 may electrically connect the conductive line pattern 1431 and the chip pad 123 of the semiconductor chip 120.

The second conductive redistribution pattern 145 is provided on the first conductive redistribution pattern 143 and may be physically and electrically connected to the first conductive redistribution pattern 143. The second conductive redistribution pattern 145 may form a bump pad to which the external connection terminal 151 is attached. That is, the second conductive redistribution pattern 145 may include under bump metal. A portion of the second conductive redistribution pattern 145 is buried in the opening of the second insulating layer 1413 and is in contact with the first conductive redistribution pattern 143, and a portion of the second conductive redistribution pattern 145 is in contact with the first conductive redistribution pattern 143. 2 may be on the top surface of the insulating layer 1413.

The first conductive redistribution pattern 143 and the second conductive redistribution pattern 145 are made of tungsten (W), copper (Cu), zirconium (Zr), titanium (Ti), tantalum (Ta), and aluminum (Al). , ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), or a combination thereof.

The external connection terminal 151 is attached to the second conductive redistribution pattern 145 and can electrically connect the semiconductor package 10 and an external device. For example, the external connection terminal 151 may include solder balls or solder bumps. Signals (e.g., data signals, control signals, power signals, and/or ground signals) provided from external devices are connected to the external connection terminal 151, the second conductive redistribution pattern 145, and the first conductive redistribution pattern ( It may be provided to the semiconductor chip 120 through a signal transmission path that sequentially passes through 143). In addition, the signal output from the semiconductor chip 120 is transmitted to an external device through a signal transmission path sequentially passing through the first conductive redistribution pattern 143, the second conductive redistribution pattern 145, and the external connection terminal 151. can be provided.

The rear protective layer 170 may be provided on the lower side of the support panel 110 and the lower side of the semiconductor chip 120. The rear protective layer 170 may be a film-type member. The rear protective layer 170 may be attached to the lower surface 119 of the support panel 110 and the lower surface 139 of the encapsulant 130. The rear protective layer 170 may cover and protect the lower surface 119 of the support panel 110. The rear protective layer 170 may be formed of, for example, insulating polymer, epoxy, or a combination thereof. In some example embodiments, the rear protective layer 170 may have adhesive properties and may serve to secure a structure such as a heat sink attached to the lower side of the rear protective layer 170.

In the case of a semiconductor package with a general fan-out structure, a significant portion of the semiconductor package is occupied by the molding material for molding the semiconductor chip, and warpage occurs due to a mismatch in the thermal expansion coefficient of the components that make up the semiconductor package. ), the fan-out ratio, which is the ratio of the overall package size and the size of the semiconductor chip, is required to be within the target range. However, according to exemplary embodiments of the present invention, the support panel 110 is formed from a silicon wafer and may be made of the same material (eg, silicon) as the semiconductor substrate 121 of the semiconductor chip 120. In this case, since the support panel 110 and the semiconductor chip 120, which make up most of the semiconductor package 10, have a similar level of thermal expansion coefficient, the thermal expansion coefficient between the components constituting the semiconductor package 10 The bending phenomenon that occurs due to the difference can be more easily controlled.

FIGS. 2A to 2N are cross-sectional views showing a method of manufacturing the semiconductor package 10 shown in FIG. 1 . Hereinafter, a method of manufacturing the semiconductor package 10 illustrated in FIG. 1 will be described with reference to FIGS. 2A to 2N.

Referring to FIG. 2A, the support panel 110 is prepared. The support panel 110 has an upper surface 118 and a lower surface 1191 that are opposed to each other, and may include pocket portions 112 provided on the upper side. The pocket portions 112 extend from the upper surface 118 of the support panel 110 and may partially penetrate the support panel 110. For example, the pocket portions 112 of the support panel 110 may be formed through a laser processing and/or etching process on a flat silicon wafer. In FIG. 2A, the support panel 110 is shown as including two pocket portions 112, but this is merely an example and the support panel 110 may include tens to hundreds of pocket portions 112.

Prepare a carrier substrate 511 on which the semiconductor chips 120 are attached, and position the carrier substrate 511 so that the support panel 110 and the carrier substrate 511 are aligned in the vertical direction (e.g., Z direction). . The carrier substrate 511 may be positioned so that the semiconductor chips 120 are aligned in a direction perpendicular to the pocket portions 112 (eg, Z-direction). An adhesive film 513 may be disposed on one side of the carrier substrate 511, and the semiconductor chips 120 may be attached to one side of the carrier substrate 511 through the adhesive film 513. The adhesive film 513 may be a release film.

Referring to FIGS. 2A and 2B , after aligning the carrier substrate 511 and the support panel 110 in the vertical direction (e.g., Z direction), the carrier substrate 511 is lowered. Attached to the support panel 110. The carrier substrate 511 may be attached to the upper surface 118 of the support panel 110 by the adhesive film 513. The carrier substrate 511 is attached to the upper surface 118 of the support panel 110 so that the semiconductor chips 120 attached to the carrier substrate 511 are accommodated in the pocket portions 112 of the support panel 110. When the carrier substrate 511 and the support panel 110 are attached, each semiconductor chip 120 can be accommodated in the corresponding pocket portion 112. The top surface 128 of the semiconductor chip 120 and the top surface 118 of the support panel 110 are attached to the adhesive film 513, and the top surface 128 of the semiconductor chip 120 and the top surface 118 of the support panel 110 are attached to the adhesive film 513. (118) may be on the same plane. As shown in FIG. 2B, the vertical height and horizontal width of the pocket portion 112 may be greater than the vertical height and horizontal width of the semiconductor chip 120. Accordingly, a gap may be formed between the sidewall of the semiconductor chip 120 and the sidewall of the support panel 110, and a gap may be formed between the bottom surface 129 of the semiconductor chip 120 and the bottom surface of the pocket portion 112. can be formed.

2B and 2C, after attaching the carrier substrate 511 on the upper surface 118 of the support panel 110, a portion of the support panel 110 is removed to form a pocket portion ( A hole 116 communicating with 112 is formed. The hole 116 may extend from the lower surface 1191 of the support panel 110 and communicate with the pocket portion 112. As the hole 116 is formed, the semiconductor chip 120 may be exposed through the lower surface 1191 of the support panel 110. For example, in order to form the hole 116 in the support panel 110, a portion of the support panel 110 may be removed through a laser cutting and/or etching process. The hole 116 and the pocket portion 112 of the support panel 110 may form a cavity 111 that penetrates the support panel 110.

Referring to FIG. 2D, the encapsulant 130 may be formed to fill the cavity 111 of the support panel 110. The encapsulant 130 covers the lower surface 1191 of the support panel 110 and flows into the cavity 111 of the support panel 110 through the lower surface 1191 of the support panel 110. Cavity 111 can be filled. The encapsulant 130 may at least partially fill the gap between the sidewall of the semiconductor chip 120 and the sidewall of the support panel 110. The upper surface 138 of the encapsulant 130 may contact the adhesive film 513. The upper surface 138 of the encapsulant 130 may be on the same plane as the upper surface 118 of the support panel 110.

Meanwhile, in FIGS. 2A to 2C, the steps of attaching the support panel 110 having the pocket portion 112 to the carrier substrate 511 and forming the hole 116 communicating with the pocket portion 112 are performed sequentially. It was explained that a cavity 111 penetrating the support panel 110 was formed. However, in some embodiments, the support panel 110 may be prepared with the cavity 111 before attaching the support panel 110 and the carrier substrate 511. That is, preparing the support panel 110 having the cavity 111 and attaching the carrier substrate 511 to the support panel 100 may be performed sequentially. In this case, as shown in FIG. 2C, the step of forming the hole 116 can be omitted.

Referring to FIGS. 2D and 2E , after forming the encapsulant 130 , the carrier substrate 511 is separated from the support panel 110 and the semiconductor chips 120 . For example, after applying a laser beam or heat to the adhesive film 513 to reduce the adhesive strength of the adhesive film 513, the carrier substrate 511 may be separated from the support panel 110. As the carrier substrate 511 and the adhesive film 513 are removed, the top surface 118 of the support panel 110 and the top surface 128 of the semiconductor chip 120 may be exposed.

Referring to FIGS. 2E and 2F , the thickness of the support panel 110 and the thickness of the encapsulant 130 can be reduced by performing a polishing process from the lower side of the result of FIG. 2E. Through the polishing process, a lower portion of the support panel 110 and a lower portion of the encapsulant 130 may be removed. The polishing process may include chemical mechanical polishing, grinding process, etc. The lower surface 1192 of the support panel 110 and the lower surface 1392 of the encapsulant 130 may be flattened through a polishing process, and the flattened lower surface 1192 of the support panel 110 and the lower surface 1392 of the encapsulant 130 may be flattened. The flattened lower surfaces 1392 may be on the same plane.

In other exemplary embodiments, the polishing process to reduce the thickness of the support panel 110 and the thickness of the encapsulant 130 is performed while the carrier substrate (511 in FIG. 2D) is attached to the support panel 110. Alternatively, the carrier substrate 511 may be removed from the support panel 110 after the polishing process is completed.

Referring to FIG. 2G, a first insulating layer 1411 is formed on the top surface 118 of the support panel 110 and the top surface 128 of the semiconductor chip 120. The first insulating layer 1411 may include an opening that exposes the chip pad 123 of the semiconductor chip 120. To form the first insulating layer 1411, an insulating material layer covering the top surface 118 of the support panel 110, the top surface 128 of the semiconductor chip 120, and the top surface 138 of the encapsulant 130. A step of forming and a step of forming an opening exposing the chip pad 123 by performing a patterning process on the insulating material layer may be performed sequentially. The patterning process for the insulating material layer may include an etching process or a laser drilling process.

Referring to FIG. 2H, a first conductive redistribution pattern 143 connected to the chip pad 123 of the semiconductor chip 120 is formed. The first conductive redistribution pattern 143 includes a conductive via pattern 1433 that fills the opening of the first insulating layer 1411 and a conductive line pattern 1431 extending along the upper surface of the first insulating layer 1411. can do. The conductive via pattern 1433 and the conductive line pattern 1431 may be formed together through the same metal wiring process.

Referring to FIG. 2I, a second insulating layer 1413 is formed on the first insulating layer 1411 and the conductive line pattern 1431. The second insulating layer 1413 may include an opening that exposes the conductive line pattern 1431. To form the second insulating layer 1413, forming an insulating material layer covering the first insulating layer 1411 and the conductive line pattern 1431, and performing a patterning process on the insulating material layer to form a conductive line pattern. The steps of forming an opening exposing the pattern 1431 may be performed sequentially. The patterning process for the insulating material layer may include an etching process or a laser drilling process.

Referring to FIG. 2J , a second conductive redistribution pattern 145 connected to a portion of the conductive line pattern 1431 exposed through the opening of the second insulating layer 1413 is formed. The first insulating layer 1411, the first conductive redistribution pattern 143, the second insulating layer 1413, and the second conductive redistribution pattern 145 may constitute the redistribution structure 140.

Referring to FIG. 2K, after forming the second conductive redistribution pattern 145, an external connection terminal 151 is formed on the second conductive redistribution pattern 145. For example, to form the external connection terminal 151, a solder ball may be attached to the second conductive redistribution pattern 145 and then a reflow process may be performed on the solder ball.

Referring to FIGS. 2K and 2L, the thickness of the support panel 110 and the thickness of the encapsulant 130 can be reduced by performing a polishing process from the lower side of the result of FIG. 2K. That is, by performing a polishing process on the lower surface 1192 of the support panel 110 and the lower surface 1392 of the encapsulant 130, the thickness of the support panel 110 and the thickness of the encapsulant 130 can be reduced. there is. The polishing process may include chemical mechanical polishing, grinding process, etc. The lower surface 119 of the support panel 110 and the lower surface 139 of the encapsulant 130 may be flattened through a polishing process, and the flattened lower surface 119 of the support panel 110 and the lower surface 139 of the encapsulant 130 may be flattened. The flattened lower surfaces 139 may be on the same plane.

In exemplary embodiments, the polishing process may be performed to remove a portion of the support panel 110 and a portion of the encapsulant 130 but not expose the lower surface 129 of the semiconductor chip 120. In other exemplary embodiments, the polishing process may be performed until the lower surface 129 of the semiconductor chip 120 is exposed.

Referring to FIG. 2M, a rear protective layer 170 is formed that covers the lower surface 119 of the support panel 110 and the lower surface 139 of the encapsulant 130. The rear protective layer 170 has a film form and can be attached to the lower surface 119 of the support panel 110 and the lower surface 139 of the encapsulant 130 through a lamination process.

Referring to Figure 2n, a sawing process is performed on the result of Figure 2m. From a plan view, a sawing process may be performed along the scribe lane (SL) of the support panel 110 that separates the cavities 111 of the support panel 110 from each other. The redistribution structure 140, the support panel 110, and the rear protective layer 170 are cut along the scribe lane (SL) of the support panel 110, and the result of FIG. 2M is divided into individual semiconductor packages (FIG. It can be separated into 1 and 10).

FIG. 3 is a cross-sectional view showing a semiconductor package 11 according to exemplary embodiments of the present invention. Hereinafter, the semiconductor package 11 shown in FIG. 3 will be described, focusing on differences from the semiconductor package 10 described with reference to FIG. 1 .

Referring to FIG. 3, the semiconductor package 11 includes a support panel 110, a semiconductor chip 120, an encapsulant 130, a redistribution structure 140, an external connection terminal 151, and a rear protective layer 170. ) may include.

The lower surface 119 of the support panel 110, the lower surface 139 of the encapsulant 130, and the lower surface 129 of the semiconductor chip 120 may each be a flattened surface. The lower surface 119 of the support panel 110, the lower surface 139 of the encapsulant 130, and the lower surface 129 of the semiconductor chip 120 may be on the same plane. The rear protective layer 170 may be attached to the lower surface 119 of the support panel 110, the lower surface 139 of the encapsulant 130, and the lower surface 129 of the semiconductor chip 120.

For example, to manufacture the semiconductor package 11 of FIG. 3, the structure shown in FIG. 2K is prepared, and the structure of FIG. 2K is polished until the lower surface 129 of the semiconductor chip 120 is exposed. can be performed. Through the polishing process, a portion of the semiconductor chip 120 is removed, and the semiconductor chip 120 may have a flattened lower surface 129. More specifically, through the polishing process, a portion of the semiconductor substrate 121 of the semiconductor chip 120 is removed, and the surface of the polished semiconductor substrate 121 may be flattened. The flattened lower surface 119 of the support panel 110, the flattened lower surface 139 of the encapsulant 130, and the flattened lower surface 129 of the semiconductor chip 120 (i.e., the flattened lower surface 129 of the semiconductor substrate 121). surface) may be on the same plane.

Additionally, the flattened lower surface 119 of the support panel 110 and the flattened lower surface 129 of the semiconductor chip 120 may be planarized together through a polishing process to have substantially the same surface roughness. That is, the planarized lower surface 119 of the support panel 110 and the planarized surface of the semiconductor substrate 121 may be planarized together through a polishing process to have substantially the same surface roughness.

Figure 4 is a cross-sectional view showing a semiconductor package 12 according to exemplary embodiments of the present invention. Hereinafter, the semiconductor package 12 shown in FIG. 4 will be described, focusing on differences from the semiconductor package 10 described with reference to FIG. 1 .

Referring to FIG. 4, the semiconductor package 12 includes a support panel 110, a semiconductor chip 120, an encapsulant 130a, a conductive pillar 153, a redistribution structure 140, and an external connection terminal. (151), and may include a rear protective layer (170).

The cavity 114 of the support panel 110 extends from the upper surface 118 of the support panel 110 and may partially penetrate the support panel 110. The cavity 114 of the support panel 110 includes a side wall of the support panel 110 facing the side wall of the semiconductor chip 120, and a bottom of the support panel 110 that supports the lower surface 129 of the semiconductor chip 120. It can be defined by side. The semiconductor chip 120 may be attached to the bottom surface of the support panel 110 through an adhesive member 161 such as a die attach film. In some cases, the adhesive member 161 may be omitted.

An encapsulant 130a is provided between the sidewall of the semiconductor chip 120 and the sidewall of the support panel 110, and a first sealant is provided on the top surface 128 of the semiconductor chip 120 and the top surface 118 of the support panel 110. An insulating layer 1411 may be provided. The encapsulant 130a and the first insulating layer 1411 may be formed of the same material to form one body. For example, the encapsulant 130a and the first insulating layer 1411 may be formed from the same insulating polymer. The encapsulant 130a may be formed together through a coating process to form the first insulating layer 1411. In this case, the encapsulant 130a and the first insulating layer 1411 may be continuously connected without any discontinuous points (eg, boundaries).

The conductive pillar 153 may be provided on the chip pad 123 of the semiconductor chip 120. The conductive pillar 153 may have a pillar shape extending in a vertical direction (eg, Z direction) from the chip pad 123 of the semiconductor chip 120. The lower surface of the conductive pillar 153 may contact the chip pad 123 of the semiconductor chip 120, and the upper surface of the conductive pillar 153 may contact the first conductive redistribution pattern 143. The first conductive redistribution pattern 143 is composed of a line pattern extending along the top surface 1419 of the first insulating layer 1411 and may be in contact with the top surface of the conductive pillar 153. The conductive pillar 153 may electrically connect the first conductive redistribution pattern 143 and the chip pad 123 of the semiconductor chip 120.

In example embodiments, the conductive pillar 153 may have the same material and/or the same combination of materials as the first conductive redistribution pattern 143 . In other example embodiments, the conductive pillar 153 may have a different material and/or a different combination of materials than the first conductive redistribution pattern 143 . For example, the conductive pillar 153 is made of copper (Cu), tungsten (W), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), ruthenium (Ru), and palladium (Pd). , platinum (Pt), cobalt (Co), nickel (Ni), or a combination thereof.

In example embodiments, the top surface of the conductive pillar 153 and the top surface 1419 of the first insulating layer 1411 may be on the same plane. For example, the top surface of the conductive pillar 153 and the top surface 1419 of the first insulating layer 1411 may be polished together through a planarization process such as a chemical mechanical polishing process, and may be on the same plane.

In exemplary embodiments, the surface roughness of the top surface 1419 of the first insulating layer 1411 is determined by the surface roughness of the other surface of the first insulating layer 1411 and the top surface 1419 of the first insulating layer 1411. The surface roughness of the lower surface of the second insulating layer 1413 in contact may be different.

When the upper surface 1419 of the first insulating layer 1411 is polished and flattened, the upper surface 1419 of the first insulating layer 1411 may be formed to have a relatively large surface roughness. In example embodiments, the surface roughness of the top surface 1419 of the first insulating layer 1411 may be greater than the surface roughness of the other surface of the first insulating layer 1411. In exemplary embodiments, the surface roughness of the top surface 1419 of the first insulating layer 1411 is determined by the surface roughness of the sidewall of the semiconductor chip 120 or another surface of the first insulating layer 1411 in contact with the sidewall of the support panel 110. may be greater than the surface roughness of . For example, the surface roughness of the top surface 1419 of the first insulating layer 1411 may be greater than the surface roughness of the other surface of the first insulating layer 1411 that contacts the top surface 128 of the semiconductor chip 120. . In exemplary embodiments, the surface roughness of the upper surface 1419 of the first insulating layer 1411 is the surface roughness of the lower surface of the second insulating layer 1413 that contacts the upper surface 1419 of the first insulating layer 1411. It can be bigger than As the upper surface 1419 of the first insulating layer 1411 is formed to have a relatively large surface roughness, the adhesion between the first conductive redistribution pattern 143 and the first insulating layer 1411 may be strengthened.

FIGS. 5A to 5K are cross-sectional views showing a method of manufacturing the semiconductor package 12 shown in FIG. 4 . Hereinafter, a method of manufacturing the semiconductor package 12 illustrated in FIG. 4 will be described with reference to FIGS. 5A to 5K.

Referring to FIG. 5A, the support panel 110 is prepared. The support panel 110 has an upper surface 118 and a lower surface 1193 that are opposed to each other, and may include cavities 114 extending from the upper surface 118. The cavities 114 extend from the upper surface 118 of the support panel 110 and may partially penetrate the support panel 110. For example, the cavities 114 of the support panel 110 may be formed through laser processing and/or etching processes on a flat silicon wafer. In FIG. 5A, the support panel 110 is shown as including two cavities 114, but this is an example and the support panel 110 may include tens to hundreds of cavities 114.

Referring to FIG. 5B, a semiconductor chip 120 including conductive pillars 153 attached to chip pads 123 is placed in the cavity 114 of the support panel 110. The semiconductor chip 120 may be attached to the support panel 110 through an adhesive member 161.

Referring to FIG. 5C, after the semiconductor chip 120 is placed in the cavity 114 of the support panel 110, a first insulating layer 1411 is formed to cover the support panel 110 and the semiconductor chip 120. . The first insulating layer 1411 may cover the support panel 110 and the upper surface 128 of the semiconductor chip 120, and the first insulating layer 1411 may be formed to cover at least a portion of the conductive pillar 153. You can. Additionally, the first insulating layer 1411 may be formed to fill the gap between the sidewall of the semiconductor chip 120 and the sidewall of the support panel 110. The encapsulant 130a may correspond to a portion of the first insulating layer 1411.

Referring to FIGS. 5C and 5D, a polishing process is performed on the first insulating layer 1411 and the conductive pillar 153 to remove a portion of the first insulating layer 1411 and a portion of the conductive pillar 153. can be removed. The polishing process may include chemical mechanical polishing, grinding process, etc. Through the polishing process, the upper surface of the conductive pillar 153 may be exposed. The top surface 1419 of the first insulating layer 1411 and the top surface of the conductive pillar 153 may be flattened through a polishing process, and the flattened top surface of the first insulating layer 1411 and the top surface of the conductive pillar 153 may be flattened. The upper surfaces may be on the same plane.

Referring to FIG. 5E, a first conductive redistribution pattern 143 is formed in contact with the upper surface of the conductive pillar 153. The first conductive redistribution pattern 143 may include a line pattern extending on the top surface 1419 of the first insulating layer 1411.

Referring to FIG. 5F, a second insulating layer 1413 is formed on the first insulating layer 1411 and the first conductive redistribution pattern 143. The second insulating layer 1413 may include an opening that exposes the first conductive redistribution pattern 143.

Referring to FIG. 5G, a second conductive redistribution pattern 145 is formed connected to a portion of the first conductive redistribution pattern 143 exposed through the opening of the second insulating layer 1413. The first insulating layer 1411, the first conductive redistribution pattern 143, the second insulating layer 1413, and the second conductive redistribution pattern 145 may constitute the redistribution structure 140.

Referring to FIG. 5H, after forming the second conductive redistribution pattern 145, an external connection terminal 151 is formed on the second conductive redistribution pattern 145.

Referring to FIG. 5I, the thickness of the support panel 110 can be reduced by performing a polishing process from the lower side of the result of FIG. 5H. The polishing process may include chemical mechanical polishing, grinding process, etc. The support panel 110 may have a lower surface 119 that is flattened through a polishing process.

Referring to FIG. 5J, a rear protective layer 170 is formed to cover the lower surface 119 of the support panel 110.

Referring to Figure 5k, a sawing process is performed on the result of Figure 5j. That is, the redistribution structure 140, the support panel 110, and the rear protective layer 170 are cut along the scribe lane (SL) of the support panel 110, and the result shown in FIG. 5J is divided into individual semiconductor packages. It can be separated by (12 in Figure 4).

As above, exemplary embodiments have been disclosed in the drawings and specification. In this specification, embodiments have been described using specific terms, but this is only used for the purpose of explaining the technical idea of the present disclosure and is not used to limit the meaning or scope of the present disclosure described in the claims. Therefore, those skilled in the art will understand that various modifications and other equivalent embodiments are possible therefrom. Therefore, the true technical protection scope of the present disclosure should be determined by the technical spirit of the attached claims.

10: semiconductor package 110: support panel
111: cavity 120: semiconductor chip
130: Encapsulation material 140: Rewiring structure
141: Redistribution insulation layer 143: First conductive redistribution pattern
145: Second conductive rewiring pattern 151: External connection terminal
170: Rear protective layer

Claims (12)

a support panel including a cavity;
a semiconductor chip provided in the cavity of the support panel and including a semiconductor substrate and a chip pad;
an encapsulant provided between a sidewall of the semiconductor chip and a sidewall of the support panel defining the cavity and in direct contact with the sidewall of the support panel;
an insulating layer on a top surface of the semiconductor chip and a top surface of the support panel;
a conductive redistribution pattern extending on the top surface of the insulating layer and electrically connected to the chip pad of the semiconductor chip; and
an insulating rear protective layer in contact with the lower surface of the support panel and the lower surface of the semiconductor chip;
Including,
The thickness of the support panel is greater than or equal to the thickness of the semiconductor chip,
The support panel and the semiconductor substrate of the semiconductor chip include the same material,
A semiconductor package in which a lower surface of the support panel and a lower surface of the semiconductor chip are on the same plane. According to claim 1,
A semiconductor package wherein the support panel and the semiconductor substrate of the semiconductor chip include silicon. a support panel including a cavity;
a semiconductor chip provided in the cavity of the support panel and including a semiconductor substrate and a chip pad;
an encapsulant provided between a sidewall of the semiconductor chip and a sidewall of the support panel defining the cavity;
an insulating layer on a top surface of the semiconductor chip and a top surface of the support panel;
a conductive redistribution pattern extending on the top surface of the insulating layer and electrically connected to the chip pad of the semiconductor chip; and
a rear protective layer in contact with the lower surface of the encapsulant and the lower surface of the support panel;
Including,
The thickness of the support panel is greater than the thickness of the semiconductor chip,
The semiconductor substrate of the support panel and the semiconductor chip includes silicon,
The encapsulant covers the lower surface of the semiconductor chip,
A semiconductor package wherein the lower surface of the support panel is on the same plane as the lower surface of the encapsulant. According to claim 1,
A semiconductor package wherein the surface roughness of the lower surface of the support panel and the surface roughness of the lower surface of the semiconductor chip are the same. delete delete According to claim 1,
A semiconductor package wherein the encapsulant includes an epoxy molding compound. Preparing a support panel including a pocket portion extending from the upper surface;
preparing a carrier substrate to which a semiconductor chip is attached, and attaching the carrier substrate to the upper surface of the support panel so that the semiconductor chip is accommodated in the pocket portion of the support panel;
forming a hole in the support panel extending from a lower surface of the support panel and communicating with the pocket portion;
forming an encapsulant to fill the hole of the support panel;
separating the carrier substrate from the semiconductor chip and the support panel;
forming a redistribution structure on the support panel and the semiconductor chip, including a conductive redistribution pattern electrically connected to a chip pad of the semiconductor chip; and
performing a polishing process from the lower side of the support panel and the lower side of the encapsulant until the lower surface of the semiconductor chip is exposed;
Including,
A method of manufacturing a semiconductor package in which the surface of the support panel flattened by the polishing process is on the same plane as the lower surface of the semiconductor chip. According to claim 8,
The support panel is a method of manufacturing a semiconductor package including silicon. delete According to claim 8,
A method of manufacturing a semiconductor package, wherein the surface roughness of the surface of the support panel flattened by the polishing process is the same as the surface roughness of the lower surface of the semiconductor chip. Preparing a support panel including a cavity extending from the upper surface;
placing a semiconductor chip with conductive pillars attached on chip pads within the cavity of the support panel;
forming an insulating layer covering the sidewall and top surface of the semiconductor chip, the sidewall and top surface of the support panel, and covering the sidewall and top surface of the conductive pillar;
polishing and removing a portion of the insulating layer and a portion of the conductive pillar so that the conductive pillar is exposed but the upper surface of the support panel is not exposed; and
forming a redistribution structure on the support panel and the semiconductor chip, including a conductive redistribution pattern electrically connected to a chip pad of the semiconductor chip through the conductive pillar;
Including,
In the step of polishing a portion of the insulating layer and a portion of the conductive pillar, the polished surface of the insulating layer and the polished surface of the conductive pillar are exposed to the outside,
The conductive redistribution pattern is a line pattern extending along the polished surface of the insulating layer and the polished surface of the conductive pillar,
A method of manufacturing a semiconductor package wherein the lower surface of the conductive redistribution pattern is on the same plane as the polished surface of the insulating layer and the polished surface of the conductive pillar.

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