KR20000015002U - Frequency Hopping System - Google Patents

Abstract

The present invention relates to a frequency hopping system using a phase-locked loop, and the conventional frequency hopping system solves the difficulty of synchronous detection when the frequency of the signal input to the phase detector is high. To this end, the frequency hopping system according to the present invention is configured to detect synchronization from the magnitude of the DC output voltage of the loop filter. In this case, since the DC output voltage has no frequency component, the DC output voltage is not affected even if the signal input to the phase detector is high speed. Therefore, synchronization can be detected even for a high speed input signal. In addition, it is possible to increase the reliability of the frequency hopping system by allowing the CPU to set the upper and lower reference voltages for the window comparison of the DC output voltages. The frequency hopping system according to the present invention can be applied to a place where frequency generation is required, such as a transceiver, a communicator, and a radio, and can also be applied to the inspection of a completed frequency generator.

Description

Frequency Hopping System

The present invention relates to a frequency synthesizer applied to various fields such as a transceiver, a communication device, a radio, a TV, a measuring instrument, and an electronic musical instrument. In particular, a frequency hopping capable of continuously changing a generation frequency at a predetermined time interval using a phase synchronization loop. (Frequency Hopping) system.

The frequency hopping system is very similar to the frequency synthesizer. Frequency synthesizer is usually a device that synthesizes a specific frequency. However, the frequency hopping system changes the oscillation frequency with time. The frequency hopping system is composed of a part for synthesizing the frequency and a part for setting the oscillation frequency to change. In the conventional frequency hopping system, the frequency synthesizing part uses a PLL (Phase Synchronous Loop) circuit. Synchronization is detected from the output of the phase detector of the PLL. However, since the frequency hopping system detects synchronization from the output of the phase detector of the PLL, synchronization detection is difficult when the frequency input to the phase detector is high speed. First, a frequency hopping system using a conventional PLL will be described with reference to FIG.

Referring to Figure 1, there is a reference frequency oscillator (Reference Oscillator) 1 and the output of the reference frequency oscillator 1 is input to the reference frequency counter (R counter; 2). Next, the output of the reference frequency counter 2 is input to a phase / frequency detector (3). The output of the phase detector 3 is input to a loop filter 4, and the output of the loop filter 4 is again input to a voltage controlled oscillator 5. The output of the voltage controlled oscillator 5 becomes the final output of the frequency hopping system, while again feeding back to the input of the phase detector 3 earlier. The output of the voltage-controlled oscillator 5 is fed back to the phase detector 3, and is input to the phase detector 3 via a prescaler 6 and a feedback frequency counter F counter 7. On the other hand, the output of the phase detector 3 is input not only to the loop filter 4 but also to the lock indicator 8. In addition, there is a central processing unit (CPU) 9 as a digital processor for setting the counter value and the prescale value of the feedback frequency counter 7 and the prescaler 6.

The reference frequency oscillator 1 is for generating a frequency serving as a reference input of the phase detector 3. The frequency generated by the reference frequency oscillator 1 is input to the reference frequency counter 2. The reference frequency counter 2 serves to count and divide the frequency generated by the reference frequency oscillator 1. When the reference frequency counter 2 is configured to count the input signal 10 times and output the signal, the reference frequency counter 2 outputs a frequency that is 1/10 of the output frequency of the reference frequency oscillator 1. Therefore, the reference frequency counter 2 divides the output of the reference frequency oscillator 1 by 1/10. The frequency divided by the reference frequency counter 2 is the reference frequency of the phase detector 3 of the next stage. Although the output of the reference frequency oscillator 1 can be used directly as a reference frequency without using the reference frequency counter 2, the reference frequency counter 2 can not be obtained directly by the output of the reference frequency oscillator 1 only. The frequency is divided using and the desired frequency is obtained. In this way, the reference frequency oscillator 1 and the reference frequency counter 2 are used to generate the desired reference frequency.

Next, the output of the reference frequency counter 2 becomes an input of the phase detector 3. As the input of the phase detector 3, the output of the voltage controlled oscillator 5 is input via the prescaler 6 and the feedback frequency counter 7.

First, the prescaler 6 and the feedback frequency counter 7 are necessary parts for the output of the voltage controlled oscillator 5 to be an integer multiple of the reference frequency. The prescaler 6 and the feedback frequency counter 7 function as a divider like the reference frequency counter 2 described above. do. The division ratio is determined by the CPU 9, and the CPU 9 changes this division ratio every fixed time to change the output of the oscillation frequency.

The phase detector 3 generates a voltage corresponding to the phase difference between two input signals, and is also called a phase comparator. The phase detector 3 outputs two signals, one of which is input to the synchronization indicator 8 and the other of which is input to the loop filter 4. The signals input from the phase detector 3 to the synchronization indicator 8 are the PD_U signal and the PD_D signal.

The phase detector 3 outputs the output signal of the reference frequency counter 2, i.e., when the reference frequency is lower than the output frequency of the feedback frequency counter 7 or is behind the phase, the PD_U output has a time corresponding to the phase difference. It goes low and the PD_D output stays high. On the contrary, when the reference frequency is higher than the output frequency of the feedback frequency counter or the phase is ahead, the PD_D output goes low and the PD_U output remains high for a time corresponding to the phase difference. By synchronizing the PD_U signal and the PD_D signal with the NOR (Not OR), the synchronization indicator 8 detects synchronization and outputs a signal whether synchronization is performed or not.

On the other hand, the PD_U signal and the PD_D signal are converted into an analog signal through a charge pump circuit. That is, in the charge pump circuit, the PD_U signal and the PD_D signal are converted into one analog signal by flowing or flowing a current corresponding to the phase difference. This analog signal is the output signal from the phase detector 3 to the loop filter 4. If there is no phase difference between the two input signals of the phase detector 3 and the output signal of the feedback frequency counter 7, there is no signal output from the phase detector 3 to the loop filter 4. That is, it outputs 0 [V].

Next, when the output signal of the phase detector 3 passes through the loop filter 4, the AC component included in the output signal is removed and subsequently input to the voltage controlled oscillator 5. The voltage controlled oscillator 5 is a control voltage in which a voltage corresponding to the phase difference output from the phase detector 3 varies the oscillation frequency before the oscillator whose oscillation frequency is changed by the control voltage.

The output of the voltage controlled oscillator 5 is fed back to the input of the phase detector 3 again. Looking at the part where the output of the voltage controlled oscillator 5 is fed back to the phase detector 3, the prescaler 6 and the feedback frequency It is input to the phase detector 3 via the counter 7. The prescaler 6 and the feedback frequency counter 7 divide the output frequency of the voltage controlled oscillator 5 by N into a feedback loop composed of the phase detector 3, the loop filter 4, and the voltage controlled oscillator 5. After synchronization is achieved, the voltage controlled oscillator 5 becomes N times the reference frequency. When the frequency ratio of the prescaler 6 and the feedback frequency counter 7 is adjusted in the CPU 9, the frequency output from the voltage controlled oscillator 5 also changes correspondingly.

As described above, the conventional frequency hopping system using the PLL detects synchronization by using the output signals PD_U and PD_D signals of the phase detector 3. However, when the input signal of the phase detector 3 becomes high, the time between the reference frequency and the rising edge of the output frequency of the voltage controlled oscillator 5 divided by the prescaler 6 and the feedback frequency counter 7 is obtained. The time interval between two signals corresponding to the time skew is shortened. Therefore, when the input signal becomes high speed, the frequency division is changed by the CPU 9 before the synchronization detection is performed on the synchronization display, and another frequency is input. As a result, if the input signal is high speed, there is a problem that the synchronous detection is difficult. In order to overcome this problem, the synchronization indicator must be high speed, but a very complicated additional circuit is required to realize this high speed.

In addition, the conventional frequency hopping system has a problem that the error occurrence rate during synchronization detection is high and the reliability is low.

Due to a malfunction of the CPU 9, an incorrect division value may be input to the feedback frequency counter 7 and the prescaler 6. In addition, self-defect of the phase synchronization loop may occur due to instability of the power supply. In addition to the above two causes, the frequency hopping system may generate signals different from the desired frequency components due to various causes. However, in the conventional synchronous detection circuit, when the NOR of the output signal of the phase detector 3 is synchronized, it indicates that the synchronization is performed regardless of the malfunction of the system. That is, there is a problem in that reliability is lowered because it detects only whether or not synchronization is performed from the output signal of the phase detector regardless of the malfunction of the phase synchronization loop.

Accordingly, an object of the present invention is to improve the synchronization detection circuit so that the synchronization can be accurately detected and the reliability is high even when the input signal of the phase detector of the frequency hopping system is high speed.

1 is a block diagram of a frequency hopping system using a conventional PLL.

2 is a block diagram of a frequency hopping system using a PLL according to an embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

1: reference frequency oscillator 2: reference frequency counter

3,10: phase detector 4: loop filter

5: voltage controlled oscillator 6: prescaler

7: feedback frequency counter 8: synchronization indicator

9,11 CPU 12 Power Divider

13: upper limit comparator 14: lower limit comparator

15: latch circuit

In order to achieve the above object, a frequency hopping system according to the present invention includes: a phase synchronizing loop including a phase detector, a loop filter, and a voltage controlled oscillator, and a distributing means for dividing an output of the voltage controlled oscillator fed back to the phase detector; And setting means for setting the division ratio of the distributing means, and synchronous detecting means for detecting the synchronization from the output of the loop filter and controlling the output of the voltage controlled oscillator.

Hereinafter, the present invention will be described in detail with reference to the embodiment of FIG. 2. 2 is configured to detect the synchronization by comparing the magnitudes of the DC output signals of the loop filter next to the phase detector without detecting the synchronization from the pulse output signals PD_U and PD_D signals of the phase detector as in the prior art. will be.

Referring to Figure 2, there is a reference frequency oscillator 1 for oscillating a frequency, the output of the reference frequency oscillator 1 is input to the reference frequency counter (2). The reference frequency counter 2 divides the frequency oscillated by the reference frequency oscillator 1 to generate a reference frequency of a desired frequency. That is, the reference frequency counter 2 is a divider. The output of the reference frequency counter 2 is input to the phase detector 10. In addition to the output of the reference frequency counter 2, another signal is input to the phase detector 10. This other input signal is inputted by dividing the output frequency of the voltage controlled oscillator 5 described later as a feedback signal.

When the phase detector 10 outputs a voltage corresponding to the phase difference between the two input signals, the output signal is converted into a DC voltage by the loop filter 4. That is, the loop filter 4 serves to remove the AC voltage included in the voltage corresponding to the phase difference. Next to the loop filter 4 is a power divider 12. The voltage controlled oscillator 5 and the window comparators 13 and 14 are connected to the next stage of the power divider 12.

The power divider 12 and the window comparators 13 and 14 are newly constructed in this embodiment and are provided to compare the magnitude of the DC output voltage of the loop filter 4. Conventionally, the synchronization was detected from the pulse output signal of the phase detector 3 as mentioned above. Therefore, when the input signal of the phase detector 3 becomes high, the time interval between the two input signals becomes very narrow, making it difficult to detect synchronously. However, in the present invention, even though the signal input to the phase detector 10 is a high speed, the voltage corresponding to the phase difference changed from the loop filter 4 to direct current has no frequency component unlike the input signal. It is configured to detect the synchronization from the DC output voltage. Therefore, in the present embodiment, the power divider 12 and the window comparators 13 and 14 are provided as a means for detecting synchronization from the DC output voltage of the loop filter 4.

The power divider 12 is a kind of voltage divider. In the case of the conventional frequency hopping system, the power divider 12 is not provided, and the output of the loop filter 4 is directly input to the voltage controlled oscillator 5. The signal input from the power divider 12 to the voltage controlled oscillator 5 acts as a control voltage of the voltage controlled oscillator 5. The output of the voltage controlled oscillator 5 also becomes the final output and is fed back to the input side of the phase detector 10 via the prescaler 6 and the feedback frequency counter 7. The prescaler 6 and the feedback frequency counter 7 serve as a divider, and the divide ratio is configured so that the CPU 11 sets it.

The output of the power divider 12 is input not only to the voltage controlled oscillator 5 but also to the window comparators 13 and 14. The power divider 12 can be configured to distribute the DC output voltage of the loop filter 4 simply by using two resistors. The reason for this configuration is that when the output voltage of the loop filter 4 is directly applied to the window comparators 13 and 14 without passing through the power divider 12, the output characteristics of the loop filter 4 or the window comparators 13 and 14 Since the input comparator 13 may not satisfy the input characteristics, and the window comparators 13 and 14 may have a load effect on the phase-locked loop, the present embodiment includes a power divider 12 to eliminate such a problem. will be. When the power divider 12 is configured as a voltage divider, a part of the divided voltage is input to the voltage controlled oscillator 5 and the other part is input to the window comparators 13 and 14. In the case of voltage division in this way, it is preferable that most of the voltage is input to the voltage controlled oscillator 5 and the small voltage is input to the window comparators 13 and 14. The reason is that when the power divider 12 divides the voltage, the control voltage of the voltage controlled oscillator 5 has a smaller control voltage than when the output voltage of the loop filter 4 is directly input to the voltage controlled oscillator 5. Because.

For example, assume that the characteristics of the voltage controlled oscillator 5 require 1 [V] as the control voltage to increase the oscillation frequency by 1 kHz. Suppose that the frequency difference between the two input signals of the phase detector 10 is 1 kHz and the voltage converted to direct current through the loop filter 4 is 1 [V]. Therefore, the voltage controlled oscillator 5 which inputs 1 [V] as the control voltage raises the oscillation frequency by 1 kHz so that the frequencies of the two input signals of the phase detector 10 will be synchronized. However, if the DC output voltage of the loop filter 4 is distributed and only about 0.9 [V] is input to the voltage controlled oscillator 5, the voltage controlled oscillator 5 raises the oscillation frequency by only 900 Hz. The frequency of the input signal shows a difference of 100 Hz. The phase difference of 100 Hz is 0.1 [V] when converted to DC voltage in the loop filter 4, and 0.09 [V] is inputted to the voltage controlled oscillator 5 when the voltage is divided. The input signal shows a frequency difference. This process is repeated several times, and eventually, the frequencies of the two input signals will match, but the repetition will delay the time taken for synchronizing than before voltage distribution. Therefore, when distributing the voltage, it is necessary to input most of the voltage as the control voltage of the voltage controlled oscillator 5 to minimize the effect of the window comparators 13 and 14 on the phase locked loop. In the power as well as the voltage, the effect of the window comparators 13 and 14 on the phase locked loop should be minimized.

Next, the window comparators 13 and 14 may be configured using a comparator dedicated for window comparison, or may be used as a comparator using two general op amps. The window comparators 13 and 14 consist of an upper limit comparator 13 and a lower limit comparator 14. The upper limit comparator 13 compares the upper limit reference voltage with a part of the output of the power divider 12, that is, the DC output voltage of the loop filter 4. The lower limit comparator 14 compares the lower limit reference voltage with the output of the power divider 12. In the present embodiment, the output of the window comparators 13 and 14 becomes high when the output of the power divider 12 is located between the upper limit reference voltage and the lower limit reference voltage, that is, when synchronization is performed. When the phase-locked loop enters the lock range, the synchronization is achieved. Therefore, when the DC output voltage of the loop filter 4 falls within a certain range, the synchronization is achieved. Therefore, when the range of the DC output voltage is detected through the window comparators 13 and 14 as in the present embodiment, it can be known whether synchronization is performed or not. Of course, the range of the DC output voltage of the loop filter 4 can be detected without using the window comparators 13 and 14 as in the present embodiment. For example, instead of setting the upper and lower reference voltages like the window comparators 13 and 14, one reference voltage is set and the DC output voltage of the loop filter 4 is detected to calculate the ± error with the set reference voltage. It is also possible to detect synchronization. However, since the circuit is much simpler to use the window comparators 13 and 14 than to directly detect the voltage and calculate the error, the window comparators 13 and 14 are used in this embodiment. Setting the upper limit and lower limit criteria, setting the error range from the reference voltage, or conceptually, both can be said to be window comparisons.

In the present embodiment, the upper limit reference voltage is applied to the non-inverting input terminal of the upper limit comparator 13 in the window comparators 13 and 14, and the output of the power divider 12 is applied to the inverting input terminal. In this case, if the output of the power divider 12 is greater than the upper limit reference voltage, the output of the upper limit comparator 13 becomes low. On the contrary, if the output of the power divider 12 is smaller than the upper limit reference voltage, the upper limit comparator 13 Output goes high. On the other hand, the output of the power divider 12 is applied to the non-inverting input terminal of the lower limit comparator 14, and the lower limit reference voltage is applied to the inverting input terminal. In this case, if the output of the power divider 12 is greater than the lower limit reference voltage, the lower limit comparator 14 outputs high. On the contrary, if the lower limit reference voltage is greater than the output of the power divider 12, the lower limit comparator 14 sets low. Output

The upper limit reference voltage and the lower limit reference voltage are configured to be set by the control of the CPU 11 in this embodiment. The frequency hopping system is configured to change the frequency within a certain range at a predetermined time, unlike a frequency synthesizer that outputs only a certain frequency. Therefore, when the frequency of occurrence is changed, the synchronization range of the phase synchronization loop also changes, so that the DC voltage output from the loop filter 4 also changes. Therefore, the upper and lower reference voltages of the window comparators 13 and 14 should also be reset whenever the frequency changes. In this embodiment, the CPU 11 is configured to reset such a reference voltage.

The output terminal of the upper limit comparator 13 and the output terminal of the lower limit comparator 14 are connected in FIG. As shown in Fig. 2, two general op amps should not be connected to output terminals. However, in the case of the dedicated ICs of the window comparators 13 and 14, an AND or OR circuit is built in. Therefore, when constructing the window comparators 13 and 14 using two general op amps without using the dedicated ICs of the window comparators 13 and 14, an AND or an OR circuit must be added to the output terminal of the comparator.

Next, the outputs of the window comparators 13 and 14 are input to a latch circuit 15. This latch circuit 15 is provided in this embodiment for the purpose of generating a synchronous detection signal from the outputs of the window comparators 13 and 14. That is, if the output of the latch circuit 15 is high, for example, the synchronization is performed. If the output of the latch circuit 15 is low, the synchronization is not performed. The relationship between the output of the latch circuit 15 and synchronization is irrelevant.

The output of the latch circuit 15 is input to the CPU 11. That is, the CPU 11 is configured to determine whether the synchronous state or the asynchronous state. However, it is also possible to directly apply the outputs of the window comparators 13 and 14 to the CPU 11 without using the latch circuit 15. Since the CPU 11 is operated by a program, when the output of the window comparators 13 and 14 is notified to the CPU 11 in advance through the program in the synchronous state and the asynchronous state, the latch circuit 15 as in the present embodiment is used. Does not have to be used.

Next, the CPU 11 will be described. The division ratio setting of the prescaler 6 and the feedback frequency counter 7 and the setting of the upper limit reference voltage and the lower limit reference voltage of the window comparators 13 and 14 are previously described. Is doing. In addition, the CPU 11 performs synchronous / asynchronous detection, and outputs the output frequency of the voltage controlled oscillator 5 to the outside when the synchronous detection is performed. When the frequency to be generated in the frequency hopping system is changed, the division ratio and the upper and lower reference voltages may be set in the CPU 11. If the division ratio is incorrectly input for some reason and synchronization is performed at an undesired frequency, if the upper and lower reference voltages are properly set in the process of detecting synchronization by the window comparators 13 and 14, the synchronization signal is not output. Do not. In the related art, since only the synchronous detection result is confirmed by the CPU 11 and does not participate in the synchronous detection process, the reliability is deteriorated. However, in this embodiment, the CPU 11 sets the upper and lower reference voltages at the time of synchronous detection, thereby increasing the reliability.

In this embodiment, the CPU 11 is used as described above. However, a microcomputer may be used without following the present embodiment, that is, without using a CPU, or may simply use programmable logic.

As described above, the frequency hopping system according to the present invention detects the synchronization through the window comparison of the magnitude of the DC output voltage of the loop filter without the frequency component without detecting the synchronization from the output signal of the phase detector. Therefore, the synchronization can be detected even when a high frequency signal is input to the phase detector. In addition, it is possible to increase the reliability of the frequency hopping system by allowing the CPU to set the upper and lower reference voltages for the window comparison of the DC output voltages. The frequency hopping system according to the present invention can be applied to a place where frequency generation is required, such as a transceiver, a communicator, and a radio, and can also be applied to the inspection of a completed frequency generator.

Claims (4)

A phase locked loop consisting of a phase detector, a loop filter, and a voltage controlled oscillator, A division means for dividing an output of the voltage controlled oscillator fed back to the phase detector; Setting means for setting a dispensing ratio of the dispensing means; And synchronous detection means for detecting synchronization from an output of the loop filter to control the output of the voltage controlled oscillator. 2. The frequency detecting apparatus according to claim 1, wherein said synchronous detecting means uses window comparing means in which the state of the output varies according to when the output of the loop filter is in the middle of both reference voltages and when the voltage is outside the range. Hopping system. The method of claim 2, wherein the window comparing means, First comparing means for comparing the output of the loop filter with an upper limit reference voltage; And a second comparing means for comparing the output of the loop filter with a lower limit reference voltage. The frequency hopping system according to claim 1, wherein the setting means uses a central processing unit.