KR970008806B1 - Apparatus for synchronizing a frequency and selecting a clock - Google Patents

Abstract

A frequency synchronization and clock selection apparatus performs a role of a frequency synchronization apparatus, and performs a function of a clock selector. The apparatus includes: a plurality of comparison means(21,22) for comparing a period; a plurality of frequency comparison gain limiter(23) for setting an output period according to a period of a latch clock pulse; frequency synchronization state output means(25,26) for displaying a synchronization state; a first divider(27) for dividing a clock; a second divider(28) for dividing a clock; a frequency comparison output control means(29,210) for generating a current gain control signal; a reference frequency synchronization monitoring means(211) for monitoring a synchronization of a system; a reference frequency synchronous state output means(212) for indicating a synchronous state; frequency state comparators(213,214) for generating a difference of the output pulse number; a frequency selection control means(215) for controlling a frequency synchronization; a frequency selection monitoring means(216,217) for selecting a reference clock pulse having a proper synchronization; a LPF and integrator(218); and a voltage-controlled oscillator(219).

Description

Frequency Sync and Clock Selector

1 is a block diagram of a conventional frequency synchronization and clock selection device.

2 is a block diagram of a frequency synchronization and clock selection device according to the present invention.

* Explanation of symbols for main parts of the drawings

11: clock selection means 12: clock control means

13: clock monitoring means 21: first frequency comparator

22: Nth frequency comparator 23: First frequency comparison gain limiter

24: Nth frequency comparison gain limiter 25: First frequency synchronization state machine

26th Nth frequency synchronization state 27N division

28: M divider 29: first frequency comparison output controller

210: Nth frequency comparison output controller 211: Reference frequency synchronization monitor

212: reference frequency synchronization state comparator 213: first frequency synchronization state comparator

214: Nth frequency synchronization state comparator 215: frequency selection controller

216: first frequency selective monitor 217: Nth frequency selective monitor

218: low pass filter and integrator 219: voltage controlled oscillator

According to the present invention, even when a clock source fails or an abnormality of an internal voltage controlled oscillator occurs, the oscillator oscillates a voltage controlled oscillator in synchronization with a multiple of a clock pulse frequency of an external clock source, thereby restoring a stable clock and performing frequency synchronization. The present invention relates to a frequency synchronization and clock selection device which maintains and simultaneously selects a clock source having good frequency synchronization.

1 is a configuration diagram of a conventional frequency synchronization and clock selection device. As shown in the drawing, 11 denotes a clock selection means, 12 denotes a clock control means, and 13 denotes a clock monitoring means.

The frequency selector receives the upper station clock by the network hierarchy and generates a synchronous clock as the input reference clock of the self-exchanger. The conventional frequency synchronous and clock selector selects one reference clock among several upper station clocks. Clock selection means (11), clock control means (12) for determining the priority of the input reference clocks and selecting one line according to the priority when the input reference clocks are normal; It consists of the clock monitoring means 13 which confirms whether it is input.

In the conventional frequency synchronization and clock selection device, if the input reference clock fails, the clock outputted from the synchronization device becomes unstable while selecting and changing a normal reference clock, and the clock coming from the upper station when an error of the internal voltage controlled oscillator occurs. There was a problem in that it could not monitor the role of the correct frequency selector.

In addition, the conventional frequency synchronization and clock selection device has a transient lock-in process when the DC gain of the low-pass filter or integrator constituting the phase-locked loop (PLL) circuit of the clock monitoring means 13 is increased. Because the output of the low pass filter or integrator outputs a maximum or minimum value at (the free run frequency of the voltage-controlled oscillator becomes unstable), the phase locked loop (PLL) tends to be unstable. In order to prevent the low DC filter of the low pass filter or the integrator, the locking range of the phase locked loop (PLL) is reduced, there is a problem that the input clock pattern is sensitive.

Accordingly, the present invention, which is designed to solve the problems of the conventional frequency synchronization and clock selection device, serves as a frequency synchronization device for reference clock pulses input from a plurality of clock sources. It is an object of the present invention to provide a frequency synchronization and clock selection device that performs a function of a clock selection device that can select a desired clock even when an error occurs in a voltage controlled oscillator.

In order to achieve the above object, the present invention includes a plurality of frequency comparison means for outputting a logic clock level and a latch clock pulse for latching the logic level by comparing the period of the voltage control oscillation frequency and a reference clock pulse from the outside; A plurality of frequency comparison gain limiting means connected to output terminals of the plurality of frequency comparing means, respectively, for receiving a predetermined first divided clock and setting an output period according to the period of the latch clock pulse; A plurality of frequency synchronous state output means for counting outputs of said plurality of frequency comparison gain limiting means to indicate a synchronous state; First dividing means for dividing the voltage controlled oscillation frequency to output the predetermined first divided clock; Second dividing means for dividing the predetermined first divided clock to output a predetermined second divided clock; A plurality of frequency comparison output control means connected to the output terminals of the plurality of frequency comparison gain limiting means, respectively, for receiving the predetermined second divided clock and outputting a current gain control signal; Reference frequency synchronization monitoring means for monitoring the synchronization of the entire system by adding output pulses of the plurality of frequency comparison output control means; Reference frequency synchronization state output means for counting an output of said reference frequency synchronization monitoring means and indicating a synchronization state; A plurality of frequency synchronous state comparison means for comparing the outputs of the reference frequency synchronous state output means and the plurality of frequency synchronous state output means, respectively, and outputting a difference in the number of output pulses; Frequency selection control means for receiving outputs of the plurality of frequency synchronization state comparison means and controlling frequency synchronization; A plurality of frequency selection monitoring means connected to an output terminal of the frequency selection control means, for receiving the clock enable signal from an external source and selecting the reference clock pulses in synchronization with each other; Low frequency filtering and integrating means for low frequency filtering and integrating the output of said reference frequency synchronization monitoring means as a voltage; And a voltage controlled oscillation means for outputting the voltage controlled oscillation frequency whose frequency is changed in accordance with the output voltage of the low pass filtering and integration means.

Hereinafter, with reference to the accompanying drawings will be described an embodiment according to the present invention;

2 is a configuration diagram of a frequency synchronization and clock selection device according to the present invention, in which 21 is the first frequency comparator, 22 is the N frequency comparator, 23 is the first frequency comparison gain limiter, and 24 is the first frequency comparator. N frequency comparison gain limiter, 25 is the first frequency synchronization state machine, 26 is the N frequency synchronization state machine, 27 is the N divider, 28 is the M divider, 29 is the first frequency comparison output controller, and 210 is the Nth A frequency comparison output controller, 211 is a reference frequency synchronization monitor, 212 is a reference frequency synchronization state, 213 is a first frequency synchronization state comparator, 214 is an N frequency synchronization state comparator, 215 is a frequency selection controller, and 216 is a first frequency selection Supervisor 217 represents the Nth frequency selective monitor, 218 the low pass filter and the integrator, and 219 the voltage controlled oscillator.

The first frequency comparator 21 receives a reference clock pulse input from a clock source 1 and an output of the voltage controlled oscillator 219 as an input, and an output terminal is connected to an input terminal of the first frequency comparison gain limiter 23. Whenever a rising or falling transition occurs in the reference clock pulse, n + 1 (n is an integer) of the period of the reference clock pulse, if the period of the reference clock pulse is K times with respect to the clock pulse period of the voltage controlled oscillator 219, The n + 1 period of the reference clock pulse is between nK + (K / 2) +1 times and nK + K-2 times the period of the clock pulse of the voltage controlled oscillator 219 (1 / K of the period of the reference clock pulse). When the voltage controlled oscillator clock pulse is smaller than the period of the pulse, i.e., the clock pulse frequency of the voltage controlled oscillator is lower than the frequency to be synchronized), the n + 1 period of the reference clock pulse is nK + relative to the period of the voltage controlled oscillator clock pulse. Between K + 2 and nK + (3K / 2) -1 times ( When 1 / K of the period of the reference clock pulse is larger than the period of the voltage controlled oscillator clock pulse, that is, when the clock pulse frequency of the voltage controlled oscillator is higher than the frequency to be synchronized, the result is divided into logic levels (UF, DF). And a latch clock pulse (UDFCP) for latching the logic level to the first frequency comparison gain limiter 23, where n + 1 periods of the reference clock pulses are nK + relative to the period of the voltage controlled oscillator clock pulses. K-1 times between nK + K + 1 times (when 1 / K of the period of the reference clock pulse is little difference compared to the period of the voltage controlled oscillator clock pulse, ie the clock pulse frequency of the voltage controlled oscillator Similar to the frequency to be synchronized), or n + 1 period of the reference clock pulse is nK + (K / 2) times the period of the voltage controlled oscillator clock pulse (1 / K of the period of the reference clock pulse is the voltage controlled oscillator clock). Compared to the period of the pulse If greater sure if unable to distinguish) does not output a latch clock pulse.

The N-th frequency comparator 22 receives a reference clock pulse input from a clock source N and an output of the voltage controlled oscillator 219, and an output terminal is connected to an input terminal of the N-th frequency comparison gain limiter 24. Whenever a rising or falling transition occurs in the clock pulse, n + 1 (n is an integer) of the period of the reference clock pulse. If the period of the reference clock pulse is K times with respect to the clock pulse period of the voltage controlled oscillator 219, The n + 1 period of the clock pulse is between nK + (K / 2) +1 times and nK + K-2 times the period of the clock pulse of the voltage controlled oscillator 219 (1 / K of the period of the reference clock pulse is When the period of the voltage-controlled oscillator clock pulse is smaller than that of the clock pulse frequency of the voltage-controlled oscillator, that is, the frequency of the voltage-controlled oscillator is lower than the frequency to be synchronized), the n + 1 period of the reference clock pulse is applied to the clock pulse of the voltage-controlled oscillator 219. NK + K + 2 times to nK + (3K / 2) -1 times (When 1 / K of the period of the reference clock pulse is greater than the period of the voltage controlled oscillator clock pulse, that is, when the clock pulse frequency of the voltage controlled oscillator is higher than the frequency to be synchronized), and divides the result into a logic level (UF). , DF) and a latch clock pulse (UDFCP) for latching the logic level, which is sent to the N-th frequency comparison gain limiter 24, where n + 1 periods of the reference clock pulses correspond to the periods of the voltage controlled oscillator clock pulses. is between nK + K-1 times and nK + K + 1 times (1 / K of the period of the reference clock pulse is little different compared to the period of the voltage controlled oscillator clock pulse, ie the clock pulse of the voltage controlled oscillator) When the frequency is similar to the frequency to be synchronized), or when n + 1 period of the reference clock pulse is nK + (K / 2) times the period of the voltage controlled oscillator clock pulse (1 / K of the period of the reference clock pulse is voltage controlled). Compared to the period of the oscillator clock pulse If you do not have a little larger if separated) does not output a latch clock pulse.

The first frequency comparison gain limiter 23 receives the output of the first frequency comparator 21 and the output of the N divider 27 and is connected to an input of the first frequency comparison output controller 29. When the transition of the latch clock pulse (UDFCP) output from the first frequency comparator 21 using the clock pulse of the N divider 27 that divides the clock pulse of the voltage controlled oscillator 219 by N is smaller than the set period. By processing the output of the first frequency comparator 21 at a set period in a set period so that the frequency gain output from itself does not change sensitively according to the number of clock pulse transitions input from the clock source 1, the first frequency comparator 21 If the transition of the latch clock pulse output from the output signal is greater than the set period, the output of the first frequency comparator 21 is processed as the transition interval of the latch clock pulse output from the first frequency comparator 21 is maintained. Does not limit the gain of the frequency comparator output from itself, and the waveform output from the self-output (UF, DF) is also shaped into a pulse waveform having a pulse width independent of the period of the clock source pulse being input to form a first frequency synchronization state. Device 25 and the first frequency comparison output controller 29.

The N-th frequency comparison gain limiter 24 receives an output of the N-th frequency comparator 22 and an N-divider 27 and is connected to an input of the N-th frequency comparison output controller 210. When the transition of the latch clock pulse UFCFC output from the N-th frequency comparator 22 using the clock pulse of the N divider 27 that divides the clock pulse of the voltage controlled oscillator 219 by N is smaller than the set period. The output of the N-th frequency comparator 22 is processed at a set period so that the frequency gain outputted from the N-th frequency comparator 22 is not changed sensitively according to the number of clock pulse transitions input from the clock source N. The N-th frequency comparator 22 If the transition of the latch clock pulse output from the () is greater than the set period, the output of the N-th frequency comparator 22 is processed at the transition interval of the latch clock pulse output from the N-th frequency comparator 22. Do not limit the gain of the frequency comparator output from itself, and the waveform output from the self output (UF, DF) is also shaped into a pulse waveform having a pulse width independent of the period of the input clock source pulse. Device 26 and the N-th frequency comparison output controller 210.

The first frequency synchronization state conditioner 25 is connected to an output of the first frequency comparison gain limiter 23 and an input of a first frequency synchronization state comparator 213 so that the first frequency comparison gain limiter 23 is provided. Input of the first frequency synchronization state comparator 213 for the synchronization state of the clock pulse of the voltage controlled oscillator 219 and the clock pulse provided by the clock source 1 by using the output (UF, DF) value of the output UF and DF. Will print

The N-th frequency synchronization conditioner 26 is connected to the output of the N-th frequency comparison gain limiter 24 and the input of the N-th frequency synchronization state comparator 214 so that the N-th frequency comparison gain limiter 24 The input state of the N-th frequency synchronization state comparator 214 inputs the synchronous state of the clock pulse of the voltage-controlled oscillator 219 and the clock pulse provided by the clock source N by using the output (UF, DF) value of the output UF and DF. Will print

The N divider 27 is an output of the voltage controlled oscillator 219, an input of the first frequency comparison gain limiter 23, an input of an Nth frequency comparison gain limiter 24, and an M divider 28. N (N is a natural number) to divide the output of the voltage-controlled oscillator 219 to the N divided clock pulse (NCP) and the first and N frequency comparison gain limiters (23, 24) and the To the input of the M divider 28.

The M divider 28 is connected to an output of the N divider 27, an input of the first frequency comparison output controller 29, and an Nth frequency comparison output controller 210 to the N divider 27. M (M is a natural number) and MN divided clock pulse (MNCP) that divides voltage-controlled oscillator clock pulse MN into first frequency comparison output controller 29 and Nth frequency. Are sent to the comparison output controller 210, respectively.

The first frequency comparison output controller 29 is connected to the output of the M divider 28 and the output of the first frequency comparison gain limiter 23 and is connected to an input of a reference frequency synchronization monitor 211 to provide a first frequency. When an output pulse occurs at the output of the comparison gain limiter 23 (if there is a transition from the input reference clock), the logic level is maintained within two periods of the MN division clock pulse (MNCP) within one period of the MN division clock pulse (MNCP). Is set to '1' or '0' so that the DC gain is largely selected in the low pass filter and the integrator 218 to widen the locking range of the phase locked loop PLL, and the first frequency comparison gain limiter 23. If the output pulse is not output more than one period of the MN division clock pulse (if there is no transition from the input reference clock), the logic level '0' or '1' is output to the low pass and integrator 218 to output the low pass. DC gain of filter and integrator 218 To select and stabilize the free-run (free-run) the frequency of the phase-locked loop (PLL) locked (locking), by narrowing the range of the voltage-controlled oscillator 219 of the reference frequency and outputs it to synchronization monitor 211.

The N-th frequency comparison output controller 210 is connected to the output of the M divider 28 and the output of the N-th frequency comparison gain limiter 24 and is connected to an input of the mood frequency synchronization monitor 211 to N-th frequency. When an output pulse occurs at the output of the comparison gain limiter 24 (if there is a transition from the input reference clock), the logic level is maintained within two periods of the MN division clock pulse (MNCP) in one or more periods of the MN division clock pulse (MNCP). Is set to '1' or '0' so that the DC gain is largely selected in the low pass and integrator 218 to widen the locking range of the phase locked loop PLL, and the N-th frequency comparison gain limiter 24. If the output pulse is not output for more than one period of the MN division clock pulse (if there is no transition in the input reference clock), the logic level '0' or '1' is outputted to the low pass filter and the integrator 218. Low pass filter and direct current of integrator 218 The gain is selected to be small to narrow the locking range of the phase locked loop PLL to stabilize the free-run frequency of the voltage controlled oscillator 219 and output the stabilized free-run frequency to the reference frequency synchronization monitor 211.

The reference frequency synchronization monitor 211 is an output of the first frequency comparison output controller 29 and the N-th frequency comparison output controller 210, the input of the reference frequency synchronization state 212, the low pass filter and the integrator 218 The clock pulses of the respective clock sources are summed by adding the logic level " 1 " and the logic level " 0 ", which are connected to the input and output from the first frequency comparison output controller 29 and the Nth frequency comparison output controller 210, respectively. This indicates the state of synchronization as a whole with respect to the clock pulse of the voltage controlled oscillator 219, where the number of logic level '1' and logic level '0' is larger than 1/2 times for N clock sources. The output value is sent to logic level '1' or logic level '0' under less than 1 condition (0.5N <UF, DF <N, N = total number of clock sources). If the number of logic level '1' or logic level '0' which is an input of the reference frequency synchronization monitor is less than (N / 2), the input value is ignored. This result is output to the input of the reference frequency synchronizer 212 and the low pass filter and the integrator 218.

The reference frequency synchronization state 212 is connected to an output of the reference frequency synchronization monitor 211 and an input of a first frequency synchronization state comparator 213 and an input of an Nth frequency synchronization state comparator 214 to the reference frequency. The number of logic level '1' and logic level '0' output from the synchronization monitor 211 is counted using an up / down counter to set the reference of the synchronization state for all clock sources, and the first frequency is set. It is sent to the input of the sync state comparator 213 and the N-th frequency sync state comparator 214.

The first frequency synchronizing state comparator 213 is connected to an output of the reference frequency synchronizing state 212, an output of the first frequency synchronizing state 25, and an input of a frequency selection controller 215 to provide the reference frequency. The output of the synchronous state machine 212 and the output of the first frequency synchronous state machine 25 are respectively compared to send a comparison difference to the frequency selection controller 215.

The N-th frequency synchronizing state comparator 214 is connected to the output of the reference frequency synchronizing state 212, the output of the N-th frequency synchronizing state 26, and the input of the frequency selection controller 216 to the reference frequency. The output of the synchronous state machine 212 and the output of the N-th frequency synchronous state machine 26 are compared, respectively, and a comparison difference is sent to the frequency selection controller 215.

The frequency selection controller 215 outputs the first frequency synchronization state comparator 213, the output of the Nth frequency synchronization state comparator 214, the input of the first frequency selection controller 216, and the Nth frequency. It is connected to the input of the selection monitor 217 to give a preset threshold value to the frequency selection controller 215 to compare the values of the N comparator outputs with the threshold value, respectively, the value of logic level '1' or logic level '0'. Are output to the inputs of the first frequency selection controller 216 and the Nth frequency selection monitor 217, respectively.

The first frequency selection controller 216 is connected to the output of the frequency selection controller 215, the clock enable 1 signal, and the input of the first frequency comparison output controller 29 to enable the clock enable 1 signal. And the first frequency comparison output controller 29 is operated only when the output of the frequency selection controller 215 is logic level '0', and when the logic level '1' is the first frequency comparison output controller 29 ) Inputs a non-operating signal to monitor the operation of the first frequency comparison output controller 29.

When the N-th frequency selection monitor 217 is connected to the output of the frequency selection controller 215, the clock enable N signal, and the input of the N-th frequency comparison output controller 210, the clock enable N signal is enabled. And the N-th frequency comparison output controller 210 is operated only when the output of the frequency selection controller 215 is logic level '0', and when the logic level '1' is the N-th frequency comparison output controller 210. ) Inputs a non-operating signal to monitor the operation of the N-th frequency comparison output controller 210.

The low pass filter and the integrator 218 are connected to the input of the voltage controlled oscillator 219 and the output of the reference frequency synchronization monitor 211 to obtain a DC gain of the low pass filter and the integrator 218 when there is a transition from the reference clock. The output of the reference frequency synchronization monitor 211 is low-pass filtered or integrated to be output to the voltage-controlled oscillator 219 with the voltage of only the low-frequency components including direct current, and the period of the MN division clock pulse (MNCP). If there is no transition even in the reference clock inputted during the above, the DC gain of the low pass filter and the integrator 211 is reduced to output the output voltage of the low pass filter and the integrator 218 so that the voltage controlled oscillator 219 is stably free run. free-run).

The voltage controlled oscillator 219 is connected to an output of the low pass and integrator 218 and an input of an N divider 27, an input of the first frequency comparator 21, and an input of the Nth frequency comparator 22, respectively. The first frequency comparator 21 and the N th frequency comparator 22 by changing the frequency of the output clock pulse according to the voltage input from the low pass filter and the integrator 218 to synchronize with the frequency of the input reference clock pulse. ) And the N divider 27 are output.

As described above, the present invention may serve as a frequency synchronization device for reference clock pulses input from multiple (N) clock sources, and select a desired clock even when the clock source fails or an error occurs in the internal voltage controlled oscillator. There is a unique effect that can perform the function of the clock selector.

Claims (5)

A plurality of frequency comparison means (21, 22) for outputting a logic level and a latch clock pulse for latching the logic level by comparing a voltage controlled oscillation frequency with a reference clock pulse from an external source; A plurality of frequency comparison gain limiting means connected to output terminals of the plurality of frequency comparing means 21 and 22, respectively, for receiving a predetermined first divided clock and setting an output period according to the period of the latch clock pulse; 23,24); A plurality of frequency synchronous state output means (25, 26) for counting outputs of the plurality of frequency comparison gain limiting means (23, 24) to indicate a synchronous state; First dividing means (27) for dividing the voltage controlled oscillation frequency to output the predetermined first divided clock; Second dividing means (28) for dividing the predetermined first divided clock to output a predetermined second divided clock; A plurality of frequency comparison output control means (29,210) connected to output terminals of the plurality of frequency comparison gain limiting means (23, 24), respectively, for receiving the predetermined second divided clock and outputting a current gain control signal; Reference frequency synchronization monitoring means (211) for monitoring the synchronization of the entire system by adding output pulses of the plurality of frequency comparison output control means (29,210); Reference frequency synchronization state output means (212) for counting the output of the reference frequency synchronization monitoring means (211) to indicate a synchronization state; A plurality of frequency synchronizing state comparing means (213,214) for outputting a difference in the number of output pulses by comparing the outputs of the reference frequency synchronizing state output means (212) and the plurality of frequency synchronizing state output means (25, 26), respectively; Frequency selection control means (215) for receiving the outputs of the plurality of frequency synchronization state comparison means (213, 214) to control frequency synchronization; A plurality of frequency selection monitoring means (216, 217) connected to an output terminal of the frequency selection control means (215) for receiving the clock enable signal from the outside and selecting the reference clock pulses in synchronization; Low frequency filtering and integrating means for outputting the low frequency filtering and integrating the output of the reference frequency synchronization monitoring means 211 as voltage; And a voltage controlled oscillation means (219) for outputting the voltage controlled oscillation frequency whose frequency is changed in accordance with the output voltage of the low pass filtering and integration means (218). 2. The apparatus according to claim 1, wherein the plurality of frequency comparing means (21, 22) compares the relationship between the first predetermined multiple of the reference clock pulse period input from the outside and the multiple of the clock pulse period of the voltage controlled oscillator. Is a predetermined second multiple of the period of the reference clock pulse input from S is between a predetermined third multiple and a fourth multiple of the clock pulse period of the voltage controlled oscillator; And outputting the result as a latch clock pulse for latching the logic level and the logic level, and otherwise not outputting the latch clock pulse. 2. The frequency-limiting gain limiting means (23, 24) according to claim 1, wherein the plurality of frequency comparison gain limiting means (23, 24) is a frequency when the period of the latch clock pulse output from the plurality of frequency comparing means (21, 22) is smaller than a preset value. The output of the comparing means is processed at a set period and outputted. When the period of the latch clock pulse is greater than a preset value, the plurality of frequency comparing means 21, 22 processes the output each time an output occurs, respectively. And a pulse waveform to be outputted to an output terminal by shaping a pulse waveform having a pulse width greater than a period of an input voltage controlled oscillation clock pulse. 2. The apparatus of claim 1, wherein the plurality of frequency comparison output control means (29, 210) outputs two of the predetermined second divided clock pulses when a pulse is output at one output of the plurality of frequency comparison gain limiting means (23, 24). Allow a large DC gain to be selected by the low pass filtering and integration means 218 within a period, and the outputs of the plurality of frequency comparison gain limiting means 23 and 24 are not less than one period of the predetermined second divided clock pulse. If none is outputted, the logic level '0' or '1' is output to select a small DC gain in the low pass and integrating means 218 so that the voltage output from the low pass and integrating means 218 is set to a maximum or minimum value. Frequency synchronization and clock selection device characterized in that configured to have a median rather than. 2. The apparatus of claim 1, wherein the plurality of frequency selection monitoring means (216, 217) is configured as an input by outputting the frequency selection monitoring means (216, 217) and an external clock enable signal using a logic of two input signals. Among the clock sources, a synchronized and enabled clock source enables the reference frequency synchronization monitoring means 211, and a non-synchronized or enabled clock source enables the plurality of frequency comparison output control means 29,210. And a clock source that is synchronized among the enabled clock sources so as not to be enabled, and outputs them to the plurality of frequency comparison output control means (29,210), respectively.