KR19990061323A - Semiconductor package - Google Patents

Abstract

The semiconductor package according to the present invention includes a substrate having a multi-layered structure including a guide groove having a stepped portion, a first semiconductor chip mounted in a guide groove of the substrate, a bonding pad on an upper surface of the first semiconductor chip, and an upper surface of the guide groove. A first metal wire electrically connecting the land pads, a second semiconductor chip mounted on a predetermined portion on the first semiconductor chip and having a smaller size than the first semiconductor chip, and a bonding pad on an upper surface of the second semiconductor chip; And a second metal wire for electrically connecting the land pads on the upper surface of the stepped portion formed in the guide groove, the first and second semiconductor chips, and the first and second metal wires to protect from the external environment. Molded resin encapsulated inside the guide groove of the substrate and metal pins attached to the metal pads on the lower surface of the substrate, Since more) of have a structure in which a semiconductor chip assembly, it is possible compared to the conventional case can be achieved the miniaturization of the product, it is possible to implement high-density mounting of the semiconductor package capable of high reliability.

Description

Semiconductor package

The present invention relates to a semiconductor package, and more particularly, to a semiconductor package having a PGA structure designed to enable high density mounting.

In accordance with the trend of lighter and shorter electronic devices, packaging technology for mounting semiconductor devices on a substrate also requires high-performance and high-density packaging technology. In response to these demands, it is a step further than the conventional quad flat package (QFP) technology. Even if 500 pins are arranged in the same body size with a lattice lattice, the pitch of the external terminals can be secured to 1.27 mm. In addition, PGA (ball grid array) or BGA (ball grid array) package technology, which is easy to mount with a printed board, has emerged.

Among the PGA packages directly related to the present invention, a land pad and a semiconductor chip on the upper surface of a printed circuit board (hereinafter referred to as PCB) are connected in advance, and then a plastic resin is encapsulated thereon, It is manufactured by attaching a pin to a metal pad of Fig. 1 is a cross-sectional view showing a conventional PGA package structure related thereto.

Referring to FIG. 1, in the conventional PGA package, a semiconductor chip 16 is mounted on a PCB substrate 10, and each bonding pad (not shown) of the upper surface of the semiconductor chip 16 and the upper surface of the substrate 10 are mounted. The formed land pads 12 are electrically connected by the metal wires 18, and the semiconductor chip 16 and the metal wires 18 are encapsulated by the molding resin (eg, epoxy resin) 20. The pins 22 are soldered to the metal pads 14 on the bottom surface of the substrate 10 which are integrally connected to the land pads on the upper surface of the substrate 10.

However, when manufacturing the PGA package to have the above structure, since only one semiconductor chip 16 is mounted in the package unit, there is a limit in reducing the area occupied by the package unit on the PCB, making it difficult to miniaturize the product. This leads to the disadvantage that the limit is followed in high-density mounting.

Accordingly, an object of the present invention is to form a PGA package in which a plurality of semiconductor chips are mounted in one package by changing the structure of the PCB substrate, thereby reducing the area occupied by the package unit on the PCB, thereby miniaturizing the product and The present invention provides a semiconductor package that enables high-density mounting.

1 is a cross-sectional view showing a conventional PGA package structure,

2 is a cross-sectional view showing a PGA package structure according to a first embodiment of the present invention.

3 is a cross-sectional view showing a PGA package structure according to a second embodiment of the present invention;

4 is a cross-sectional view showing a PGA package structure according to a third embodiment of the present invention.

In order to achieve the above object, in the first embodiment of the present invention, a multi-layered substrate having a guide groove having a stepped portion, a first semiconductor chip mounted in the guide groove of the substrate, and an upper surface of the first semiconductor chip are provided. A first metal wire for electrically connecting a bonding pad and a land pad on the upper surface of the guide groove, a second semiconductor chip mounted on a predetermined portion on the first semiconductor chip and having a smaller size than the first semiconductor chip; 2 A second metal wire electrically connecting the bonding pads on the upper surface of the semiconductor chip and the land pads on the upper surface of the stepped portion formed in the guide groove, and the first and second semiconductor chips and the first and second metal wires. In order to protect against, a half made of a molding resin encapsulated in the guide groove of the substrate and a metal pin attached to the metal pad on the lower surface of the substrate Conductor packages are provided.

In order to achieve the above object, in the second embodiment of the present invention, a multi-layered substrate having a guide groove having a stepped portion, a first semiconductor chip mounted in the guide groove of the substrate, and an upper surface of the first semiconductor chip are provided. A first metal wire electrically connecting a bonding pad and a land pad on an upper surface of the guide groove, an insulating film formed on a predetermined portion on the first semiconductor chip, a second semiconductor chip mounted on the insulating film, and the second semiconductor chip To protect the first and second semiconductor chips and the first and second metal wires from the external environment, the second metal wires electrically connecting the bonding pads on the upper surface and the land pads on the upper surface of the stepped portion formed in the guide groove. In order to achieve this, a semiconductor package is formed of a molding resin encapsulated in a guide groove of the substrate and a metal pin attached to a metal pad on a lower surface of the substrate. It is provided.

In order to achieve the above object, in a third embodiment of the present invention, a multi-layered substrate having a guide groove having a stepped portion, a first semiconductor chip mounted in a guide groove of the substrate, and an upper surface of the first semiconductor chip are provided. A first metal wire electrically connecting a bonding pad and a land pad on an upper surface of the guide groove, and a portion of the first semiconductor wire and the first metal wire to be sealed in a predetermined portion inside the guide groove of the substrate to protect the first semiconductor chip and the first metal wire from an external environment. An electrically connecting first molding resin, a second semiconductor chip mounted on a predetermined portion on the first molding resin, and a bonding pad on the upper surface of the second semiconductor chip and a land pad on the upper surface of the stepped portion formed in the guide groove. In order to protect the second metal wire and the second semiconductor chip and the second metal wire from the external environment, a rod is provided inside the guide groove of the substrate. There is provided a semiconductor package comprising a supported second molding resin and a metal pin attached to a metal pad on the lower surface of the substrate.

As a result of manufacturing the semiconductor package to have the above structure, since two semiconductor chips are mounted in one package, the product can be miniaturized as compared with the conventional case, and the high density mounting of the semiconductor package is possible.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

The present invention focuses on making a semiconductor package capable of high-density mounting by manufacturing a PGA package such that a plurality of semiconductor chips (for example, two) are mounted in one package through a structure change of a PCB substrate. As a technique, this will be described with reference to the drawings illustrated in FIGS. 2 to 4.

2 is a cross-sectional view illustrating a PGA package structure according to a first embodiment of the present invention, FIG. 3 is a cross-sectional view illustrating a PGA package structure according to a second embodiment of the present invention, and FIG. A cross-sectional view showing a PGA package structure according to a third embodiment of the invention is shown.

First, a first embodiment will be described with reference to the cross-sectional view shown in FIG. 2. The PGA package shown in the above embodiment is a case where a plurality of semiconductor chips of different sizes having different functions are stacked on a PCB substrate (for example, two). Referring to FIG. 2, in the first embodiment of the present invention, It can be seen that the proposed PGA package consists of the following structures.

In the center portion, a multi-layered substrate (for example, a PCB) 100 having a guide groove having a stepped portion I is prepared, and a first semiconductor chip 106a is formed in the guide groove of the substrate 100. Each of the bonding pads (not shown) on the upper surface of the first semiconductor chip 106a and the land pads 102 on the upper surface of the guide groove are electrically connected to each other by the first metal wire 108a. A predetermined portion of the semiconductor chip 106a (for example, a central portion of the chip on which the bonding pad is not formed) is mounted with a highly integrated second semiconductor chip 106b having a relatively smaller size than the first semiconductor chip 106a. Each of the bonding pads (not shown) on the upper surface of the second semiconductor chip 106b and the land pads 102 on the upper surface of the stepped portion I formed in the guide groove are electrically connected to each other by the second metal wire 108b. And the first and second semiconductor chips 106a and 106b and the first The first and second metal wires 108a and 108b are encapsulated by the molding resin 110 in the guide grooves, and the metal pads 104 on the lower surface of the substrate 100 connected integrally with the land pads 102. The metal pin 112 is attached.

Therefore, the PGA package having the above structure is manufactured through the following fifth step process. As a first step, first, a multi-layered substrate (for example, a PCB) 100 having a guide groove having a stepped portion I is prepared, and the first semiconductor chip 106a is placed in the guide groove of the substrate 100. Mount it.

As a second step, each of the bonding pads (not shown) of the first semiconductor chip 106a and the land pads 102 formed on the upper surface of the guide groove using the first metal wire 108a correspond one-to-one to each other. Wire bonding is performed so as to be connected.

As a third step, the first chip 106a which performs a function different from the first semiconductor chip 106a to a predetermined portion (eg, a center portion of the chip on which the bonding pad is not formed) on the first semiconductor chip 106a. Is mounted on the second semiconductor chip 106b of a smaller size.

As a fourth step, each land pad 102 formed on each bonding pad (not shown) of the second semiconductor chip 106b and the stepped portion I in the guide groove using the second metal wire 108b is formed. Wire bonding is performed to be electrically connected to each other in a one-to-one correspondence.

As a fifth step, in order to protect the first and second semiconductor chips 106a, 106b and the first and second metal wires 108a, 108b from the external environment, the inside of the guide groove in which they are formed is formed. After sealing with the molding resin (eg, epoxy resin) 110, the metal pins 112 are attached to the metal pads 104 on the lower surface of the substrate 100, thereby completing the manufacture of the PGA package.

At this time, an insulating resist (not shown) is applied to the surface exposed area of the bottom surface of the substrate 100 on which the metal pad 104 is formed, which is provided in a state of being pre-coated in manufacturing a substrate having a multilayer structure. .

The manufacture of the PGA package to have such a structure allows to mount a plurality of semiconductor chips that perform different functions in one package, thereby reducing the area of the package unit on the PCB, thereby enabling high-density packaging of the package. To do this.

Next, a second embodiment of the present invention will be described with reference to the cross-sectional view shown in FIG. 3. The PGA package presented in the above embodiment is a case where a plurality of semiconductor chips of the same size having the same function are stacked (eg, two) on a PCB substrate. Referring to FIG. 3, the PGA package described in the second embodiment of the present invention is described. It can be seen that the PGA package is composed of the following structures.

In the center portion, a multi-layered substrate (for example, a PCB) 200 having a guide groove having a stepped portion I is prepared, and a first semiconductor chip 206a is formed in the guide groove of the substrate 200. Each of the bonding pads (not shown) on the upper surface of the first semiconductor chip 206a and the land pads 202 on the upper surface of the guide groove are electrically connected to each other by the first metal wire 210a. An insulating film 208 having a predetermined thickness is formed on a predetermined portion of the semiconductor chip 206a (for example, a center portion of the chip on which the bonding pad is not formed), and the same size as the first semiconductor chip 206a on the insulating film 208. Of the second semiconductor chip 206b, each of the bonding pads (not shown) on the upper surface of the second semiconductor chip 206b and each of the land pads 202 on the upper surface of the stepped portion I formed in the guide groove. Are electrically connected to each other by a metal wire 210b, and these first The second semiconductor chips 206a and 206b and the first and second metal wires 210a and 210b are encapsulated by the molding resin 212 in the guide groove and integrally with the land pad 202. The metal pin 214 is attached to the metal pad 204 on the bottom surface of the connected substrate 200.

In this case, the insulating film 208 formed between the first semiconductor chip 206a and the second semiconductor chip 206b may have a first metal wire 210a and a second semiconductor connected to the bonding pads on the upper surface of the first semiconductor chip 206a. The edge surfaces of the lower surface of the chip 206b are formed to have a thickness such that they are not in contact with each other. This prevents a short phenomenon caused when the edge surfaces of the first metal wire 210a and the second semiconductor chip 206b are in contact with each other. For sake.

Therefore, the PGA package having the above structure is manufactured through the following fifth step process. As a first step, first, a multi-layered substrate (for example, a PCB) 200 having a guide groove having a stepped portion I is prepared, and the first semiconductor chip 206a is placed in the guide groove of the substrate 200. Mount it.

As a second step, each of the bonding pads (not shown) of the first semiconductor chip 206a and the land pads 202 formed on the upper surface of the guide groove are electrically connected to each other using the first metal wire 210a. Wire bonding is performed.

As a third step, an insulating film 208 is formed on a predetermined portion of the first semiconductor chip 206a (for example, the center portion of the chip on which the bonding pad is not formed), and the same as the first semiconductor chip 206a thereon. The second semiconductor chip 206b which performs a function is mounted.

As described above, the formation of the insulating film 208 having a predetermined thickness between the first semiconductor chip 206a and the second semiconductor chip 206b may be caused when mounting semiconductor chips of the same size as mentioned above. This is to prevent contact between the first metal wire 210a and the ground surface of the second semiconductor chip 206b.

As a fourth step, each land pad 202 formed on each bonding pad (not shown) of the second semiconductor chip 206b and the stepped portion I in the guide groove using the second metal wire 210b is formed. Wire bonding is performed to electrically connect with each other.

As a fifth step, in order to protect the first and second semiconductor chips 206a and 206b and the first and second metal wires 210a and 210b from the external environment, the inside of the guide grooves in which they are formed are formed. After sealing using the molding resin (for example, epoxy resin) 212, the metal pin 204 is attached to the metal pad 204 on the lower surface of the substrate 200, thereby completing the manufacture of the PGA package.

In this case, too, the area occupied by the package unit on the PCB can be reduced, thereby enabling high density mounting of the package.

Subsequently, a third embodiment will be described with reference to the cross section shown in FIG. The PGA package presented in the above embodiment is the same as the second embodiment in that a plurality of semiconductor chips of the same size having the same function are stacked (eg, two) on a PCB substrate. As a technique different from the second embodiment in that the 306a and the second semiconductor chip 306b are insulated by the molding resin, referring to FIG. 3, the PGA presented in the third embodiment of the present invention. It can be seen that the package consists of the following structures.

In the center portion, a multi-layered substrate (for example, a PCB) 300 having a guide groove having a stepped portion I is prepared, and a first semiconductor chip 306a is provided in the guide groove of the substrate 300. Each of the bonding pads (not shown) on the upper surface of the first semiconductor chip 306a and the land pads 302 on the upper surface of the guide groove are electrically connected to each other by the first metal wire 308a. The semiconductor chip 306a and the first metal wire 308a are encapsulated by the first molding resin 310a in the guide groove, and a predetermined portion on the first molding resin 310a is formed with the first semiconductor chip 306a. The second semiconductor chip 306b of the same size is mounted, and each bonding pad (not shown) on the upper surface of the second semiconductor chip 306b and each land pad 302 on the upper surface of the stepped portion I formed in the guide groove are formed. And are electrically connected to each other by the second metal wire 308b. 306b and the second metal wire 308b are encapsulated by the second molding resin 310b in the guide groove, and the metal pad 304 on the bottom surface of the substrate 300 connected integrally with the land pad 302 is made of metal. The pin 312 is attached.

Therefore, the PGA package having the above structure is manufactured through the following fifth step process. As a first step, a multi-layered substrate (for example, a PCB) 300 having a guide groove having a stepped portion I is prepared, and the first semiconductor chip 306a is mounted in the guide groove of the substrate 300. Let's do it.

As a second step, each of the bonding pads (not shown) of the first semiconductor chip 306a and the land pads 302 formed on the upper surface of the guide groove by using the first metal wire 308a correspond one-to-one to each other. Wire bonding is performed so as to be connected.

As a third step, in order to protect the first semiconductor chip 306a and the first metal wire 308a from the external environment, predetermined portions inside the guide grooves in which they are formed are formed with the first molding resin (for example, epoxy resin) 310a. ), And a second semiconductor chip 306b which performs the same function as the first semiconductor chip 306a is mounted on a predetermined portion thereon.

As a fourth step, each land pad 302 formed on each bonding pad (not shown) of the second semiconductor chip 306b and the stepped portion I in the guide groove using the second metal wire 308b is formed. Wire bonding is performed to be electrically connected to each other in a one-to-one correspondence.

As a fifth step, in order to protect the second semiconductor chip 306b and the second metal wire 308b from the external environment, the second molding resin (for example, epoxy resin) 310b is formed inside the guide groove in which they are formed. After encapsulating them, the metal pins 312 are attached to the metal pads 304 on the lower surface of the substrate 300, thereby completing the manufacture of the PGA package.

When manufacturing a PGA package having such a structure, since a plurality of semiconductor chips can be mounted in one package without difficulty in the process, it is possible to reduce the area occupied by a single component package on the PCB, thereby enabling high density mounting. .

As mentioned above, although this invention was demonstrated concretely through the Example, this invention is not limited to this, A deformation | transformation and improvement are possible by the common knowledge of the art within the technical idea of this invention.

As described above, according to the present invention, since two semiconductor chips are mounted in one package, it is possible to miniaturize a product as compared with the conventional case, and to implement a highly reliable semiconductor package capable of high density mounting. .

Claims (3)

A multi-layered substrate provided with a guide groove having a stepped portion, A first semiconductor chip mounted in the guide groove of the substrate; A first metal wire electrically connecting the bonding pad on the upper surface of the first semiconductor chip and the land pad on the upper surface of the guide groove; A second semiconductor chip mounted on a predetermined portion on the first semiconductor chip and having a smaller size than the first semiconductor chip; A second metal wire electrically connecting the bonding pad on the upper surface of the second semiconductor chip and the land pad on the upper surface of the stepped portion formed in the guide groove; In order to protect the first and second semiconductor chips and the first and second metal wires from the external environment, a molding resin encapsulated inside a guide groove of the substrate and a metal pin attached to a metal pad on the lower surface of the substrate. A semiconductor package, characterized in that made. A substrate having a multilayer structure provided with a guide groove having a stepped portion in the center thereof, A first semiconductor chip mounted in the guide groove of the substrate; A first metal wire electrically connecting the bonding pad on the upper surface of the first semiconductor chip and the land pad on the upper surface of the guide groove; An insulating film formed on a predetermined portion on the first semiconductor chip; A second semiconductor chip mounted on the insulating film; A second metal wire electrically connecting the bonding pad on the upper surface of the second semiconductor chip and the land pad on the upper surface of the stepped portion formed in the guide groove; Molded resin encapsulating the first and second semiconductor chips and the first and second metal wires, And a metal pin attached to a metal pad on a lower surface of the substrate. A multi-layered substrate provided with a guide groove having a stepped portion, A first semiconductor chip mounted in the guide groove of the substrate; A first metal wire electrically connecting the bonding pad on the upper surface of the first semiconductor chip and the land pad on the upper surface of the guide groove; A first molding resin encapsulated in a predetermined portion inside the guide groove of the substrate to protect the first semiconductor chip and the first metal wire from an external environment; A second semiconductor chip mounted on a predetermined portion on the first molded resin; A second metal wire electrically connecting the bonding pad on the upper surface of the second semiconductor chip and the land pad on the upper surface of the stepped portion formed in the guide groove; A second molding resin encapsulated inside a guide groove of the substrate to protect the second semiconductor chip and the second metal wire from an external environment; And a metal pin attached to a metal pad on a lower surface of the substrate.