JPH07307412A - Multilayer package with built-in bypass capacitor - Google Patents

Abstract

PURPOSE:To avoid the malfunction of an LSI by placing parallel flat plate type bypass capacitors in a cavity and placing integrated circuits directly just above the capacitors or above through support members. CONSTITUTION:A 3-stage structured cavity 13 is formed in a central part of a package 10 in which ground layers 34 and power source layers 35 are formed such that a part of the layer 35 is exposed on the surface of a bottom part 3a of the cavity 13 and part of the layer 34 is also exposed on a face 13b above by one stage from the bottom 13a of the cavity 13. To the bottom 13a of the cavity 13, parallel flat plate type capacitors 11 are entirely adhered through a conductive material 12 serving as an adhesive agent, and just above the capacitor 11 an LSI chip 33 is adhered similarly through the material 13. Thus, a bypass capacitor-mounted multilayer package difficult to cause a malfunction is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bypass capacitor mounted laminated package, and more particularly to a bypass capacitor mounted laminated package which operates at a high frequency.

[0002]

2. Description of the Related Art In recent years, integrated circuits such as ICs and LSIs (hereinafter collectively referred to as LSIs) have been increasing in speed and capacity, and signals used therefor have been increased in frequency, and internal circuits have been Highly integrated. Therefore, switching noise generated in the package in which the LSI is mounted due to these causes a problem as a factor that causes the LSI to malfunction. Therefore, in order to reduce such switching noise, a package equipped with a bypass capacitor has come to be widely used recently.

Since the size of switching noise of the package in which the bypass capacitor is mounted is proportional to the size of the inductance between the mounted LSI and the bypass capacitor, the inductance of the capacitor itself due to its structure. (ESL: Equivalent Serie
s Inductance), and minimizing the inductance of the wiring between the LSI and the bypass capacitor are important factors for reducing switching noise. Therefore, use a bypass capacitor with as small an ESL as possible, and make the current path for connecting the bypass capacitors with many power supply pads or ground pads normally provided on the LSI side as short as possible. Is desirable.

Conventionally used high-speed, large-capacity L
A package in which the SI is mounted has a multi-layer structure in which a power supply layer and a ground layer are formed in the package in order to maintain the electrical characteristics.

FIG. 5 is a cross-sectional view schematically showing the laminated package, and a large-capacity chip capacitor 31 is mounted on the laminated package as a bypass capacitor.

In the laminated package on which the bypass chip capacitor 31 is mounted, a cavity 47 having a two-step structure is formed in the central portion of the package 30, and the surface opposite to the surface on which the cavity 47 is formed (hereinafter, A bypass chip capacitor 31 is disposed near the end of the bottom surface). A ground layer 34 and a power supply layer 35 are formed inside the package 30, and the ground layer 34 is exposed on the surface of the bottom of the cavity 47. On the other hand, the LSI chip 33 is adhered to the front surface of the bottom of the cavity 47 by the conductive material 32 which also serves as an adhesive, whereby the ground layer 34 and the back surface of the LSI chip 33 are connected.

The bypass chip capacitor 31 disposed on the bottom surface of the package 30 is provided with a ground pad 45 at a part of a portion bonded to the package 30.
The ground pad 45 is connected to the ground layer 34 through one via hole 39 formed inside the package 30. On the other hand, the ground layer 34 is connected to the pin 43 of the package 30 through the via hole 48 and also to a large number of ground pads 37 formed on the surface of the middle of the cavity 47 of the package 30. 37 and ground pad of LSI chip 33 (not shown)
Are connected to each other by a wire 36.

When the connection state of the ground wiring between the LSI chip 33 and the bypass chip capacitor 31 is sorted out, first, a large number of ground pads (not shown) of the LSI chip 33 are formed on the wire 36 and the cavity 47. A large number of current paths led out via the ground pad 37 and the via hole 38 are connected to the ground layer 34 to be aggregated, and connected to the chip capacitor 31 via one via hole 39 led from the ground layer 34. Has been done.

On the other hand, the wiring for the power supply is also wired in the same state as the wiring for grounding, and is led out from the LSI chip 33 through the wire 40, the power supply pad 41 formed in the package 30, and the via hole 42. A large number of the generated current paths are connected to the power supply layer 35 and integrated, and the power supply layer 35 is connected to the package pin 43 through the via hole 49 and the power supply of the chip capacitor 31 through the single via hole 44. It is connected to the pad 46.

As described above, the connection between the chip capacitor 31 and the ground layer 34 or the power supply layer 35 is made by the via holes 39 and 44, respectively, which is because the chip capacitor 31 itself has a small size. This is because it is difficult to connect a large number of wirings (via holes) because the size of the external electrode terminal 31 is small.

[0011]

As described above, in the conventional bypass capacitor-equipped laminated package, the chip capacitor 31 is used for the LSI such as the bottom surface of the package 30.
Since the wires are arranged far from the chip 33, the wires from a large number of power pads or ground pads (not shown) prepared on the LSI chip 33 side are once aggregated in the power supply layer 35 or the ground layer 34, and the aggregated wiring. Is connected to the chip capacitor 31 for bypassing, and therefore the length of the wiring becomes long, resulting in a large inductance. Also, the ESL of the chip capacitor 31 itself is large, and due to the problem of the length of the wiring between the LSI chip 33 and the bypass chip capacitor 31 and the problem of the inductance of the chip capacitor 31 itself, its inductance is reduced. However, there is a problem in that switching noise and the like become large, which causes malfunction of the LSI.

Further, when the package 30 having the structure as shown in FIG. 5 is used, via holes 39 and 44 for connecting to the power supply layer 35 or the ground layer 34 are required, and the internal wiring layer is complicated. There is also a problem that the manufacturing cost of the package 30 itself increases.

The present invention has been made in view of the above problems, and has a small bypass inductance between the LSI and the bypass capacitor, which makes switching noise and the like extremely small and prevents the LSI from malfunctioning. It is intended to provide a laminated package at low cost.

[0014]

In order to achieve the above object, a bypass capacitor-equipped laminated package according to the present invention is a bypass capacitor-equipped laminated package having a cavity, in which an integrated circuit chip is mounted. A parallel plate type capacitor is placed inside the cavity, and the integrated circuit chip is arranged directly above the bypass parallel plate type capacitor or above the bypass parallel plate type capacitor.

[0015]

According to the bypass capacitor-equipped multilayer package having the above structure, a bypass capacitor-equipped multilayer package having a cavity and in which an integrated circuit chip (hereinafter referred to as an LSI chip) is mounted is provided. Is placed inside the cavity, and since the integrated circuit chip is arranged directly above the bypass parallel plate capacitor or above the bypass parallel plate capacitor, the external electrode area of the bypass parallel plate capacitor can be reduced. It becomes possible to take a large size, and the distance between the bypass parallel plate type capacitor and the LSI chip is shortened to connect a large number of power supply pads or ground pads prepared on the LSI chip side to the bypass capacitor. It is possible to shorten the current path for

Further, since the bypass capacitor is a parallel plate type, it is possible to make the bypass capacitor large, and the multi-layer electrodes inside thereof are connected by a large number of via holes, so that a current path flowing through the internal layer is obtained. Is shortened and dispersed in all directions, and as a result, the inductance of the capacitor itself is reduced, and it is also possible to directly connect the power supply layer or the ground layer in the laminated package to the external electrode terminal of the capacitor.

Therefore, the inductance between the LSI chip and the bypass capacitor is reduced, the inductance of the bypass capacitor itself is also reduced, and switching noise and the like are extremely reduced, so that malfunction of the LSI is less likely to occur.

Further, since the structure of the bypass capacitor-equipped laminated package is simple, it is possible to provide the bypass capacitor-equipped laminated package at a low cost.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a bypass capacitor mounted laminated package according to the present invention will be described below with reference to the drawings.

FIG. 1 is a cross-sectional view schematically showing a bypass capacitor mounting laminated package according to an embodiment.

In this bypass capacitor-equipped laminated package, a cavity 13 having a three-stage structure is formed in the central portion of the package 10, and a ground layer 34 and a power supply layer 35 are formed inside the package 10. A part of the layer 35 is exposed on the surface of the bottom 13a of the cavity 13, and a part of the ground layer 34 is also exposed on the bottom 13a of the cavity 13.
It is exposed on the upper surface 13b.

A parallel plate type capacitor 11 is adhered to the bottom portion 13a of the cavity 13 by a conductive material 12 which also serves as an adhesive, over almost the entire surface. The LSI chip 33 is bonded via the material 12.

External connecting electrodes 14 and 15 (FIG. 2) are formed on both main surfaces of the parallel plate type capacitor 11, and the power supply layer 35 and the lower surface of the parallel plate type capacitor 11 are connected to the outside through the conductive material 12. The electrode 15 is electrically connected, while
External electrode 14 on the upper surface of parallel plate type capacitor 11 and LSI
It is also electrically connected to the back surface of the chip 33. Also L
The conductive material 12 adhering the SI chip 33 and the parallel plate type capacitor 11 is also applied to a portion where the exposed ground layer 34 exists, whereby the LSI chip 33,
The parallel plate type capacitor 11 and the ground layer 34 are connected to each other.

The ground pad (not shown) of the LSI chip 33 is connected to the ground layer 34 via the wire 36, the ground pad 37 of the package, and the via hole 38.
4 is connected to the external electrode 14 of the parallel plate type capacitor 11 and is also connected to the pin 43 through the via hole 48. Similarly, the power supply pad (not shown) of the LSI chip 33 has the wire 40 and the power supply pad 4 of the package.
1. Connected to the power supply layer 35 via the via hole 42, the external electrode 15 of the parallel plate capacitor 11 from the power supply layer 35
Pin 4 via the via hole 49.
Connected to 3.

According to the present embodiment, unlike the conventional bypass capacitor mounting laminated package shown in FIG. 5, it is not necessary to integrate a large number of current paths and connect them to the bypass chip capacitor 31 by a long wiring. Since it is possible to connect to the parallel plate type capacitor 11 through the ground layer 34 or the power supply layer 35 through a short and thick current path, the inductance can be reduced.

Next, the parallel plate type capacitor 11 used in this embodiment will be described in more detail.

FIG. 2 is a sectional view schematically showing the parallel plate type capacitor 11, and FIG. 3 is an exploded perspective view thereof.
In the figure, 19a, 19b, 19c, 19d and 19e indicate dielectric layers.

The parallel plate type capacitor 11 is completely integrated by firing, and each dielectric layer 19a ...
, It is not possible to actually separate them, but in FIG. 3, for the sake of convenience, the respective dielectric layers 19a ...

As shown in FIGS. 2 and 3, internal electrodes 16b, 16c, 1 are provided inside the parallel plate type capacitor 11.
Although the layers 6d and 16e are formed, the internal electrode 16b
Is a part 18 in which a circular electrode is not formed
b, 18c, 18d, 18e are present, and the internal electrodes 16b ...
The via hole 17a or the via hole 17b is formed in a state where the via hole 17a or the via hole 17b is not contacted. Regarding the connection between the external electrodes 14 and 15 and the internal electrodes 16b ..., the external electrodes 14 on the upper surface are two internal electrodes 16c separated by one layer,
16e is connected via a via hole 17a, while the external electrode 15 on the lower surface is also connected via internal vias 17b to internal electrodes 16d, 16b which are also separated by one layer, and internal electrodes adjacent to each other are not connected. It is like this.

In the parallel plate type capacitor 11 having the above-mentioned structure, the currents flowing through the internal electrodes 16b ... Are dispersed so as not to be biased in a fixed direction, and a large number of via holes 17a, 17b formed form the current flow. The flow distance becomes shorter, and as a result, ESL becomes smaller and switching noise can be reduced. In this case, the size of the ESL of the parallel plate capacitor 11 is the via hole 17
Almost inversely proportional to the numbers of a and 17b, and via holes 17a and 1a
The larger the number of 7b, the smaller the ESL. Further, since the number of internal electrodes 16b ... Is proportional to the capacitance, the type of dielectric material is selected according to the required capacitance, and the number of internal electrodes 16b. do it.

The inductance of the bypass capacitor-equipped laminated package according to the above-described embodiment (referred to as Embodiment 1) having such a configuration was actually measured. In addition, the inductance was similarly measured for the conventional bypass capacitor mounted laminated package shown in FIG. 5 as Comparative Example 1. The inductance at each internal location and the total inductance are shown in Table 1 below.

In each of Example 1 and Comparative Example 1, the wire 36, the wire 40, and the ground pad 3 are used.
The number of 7 and the number of power supply pads 41 are 40, respectively, and the number of chip capacitors 31 used in the bypass capacitor mounting laminated package according to the comparative example is 4.

[0033]

[Table 1]

As is clear from the above results, the inductance of the bypass capacitor mounted laminated package according to the first embodiment is reduced to 1/3 of that of the conventional one (Comparative Example 1).

As described above, in the bypass capacitor mounting laminated package according to the above-described embodiment, the inductance is reduced because the LSI chip 33 is electrically connected to the bypass capacitor 11 through the short current path, and the bypass capacitor is further bypassed. Since the use capacitor 11 is the parallel plate type capacitor as shown in FIGS. 2 and 3, the ESL of the capacitor itself is also small, and as a result, switching noise and the like can be made extremely small, and the occurrence of malfunction in the LSI is prevented. can do.

Further, since the bypass capacitor mounting laminated package has a simple structure, it can be provided at a low cost.

Next, a bypass capacitor mounted laminated package according to another embodiment will be described. FIG. 4 is a cross-sectional view schematically showing a bypass capacitor mounted laminated package using flipped TAB (Tape Automated Bonding) as a mounting method. In this case, the pin 43 is a flipped TAB 21 on which the LSI chip 33 is mounted. It is arranged on the surface opposite to the surface on which it is mounted.

Also in the bypass capacitor mounting laminated package according to this embodiment, the cavity 23 is formed in the central portion, and of the ground layer 34 and the power supply layer 35 formed therein, a part of the ground layer 34 is the cavity. Exposed at 23.

On the other hand, inside the cavity 23, the parallel plate type capacitor 11 is adhered to the bottom of the parallel plate type capacitor 11 through the conductive material 12, and the external electrode 14 formed on the upper surface of the parallel plate type capacitor 11 is exposed. There is. A flip TAB 21 is arranged above the parallel plate type capacitor 11 via a support rubber 24.
An LSI chip 33 is mounted on the AB 21.

Regarding the connection state of the wiring, the ground pad (not shown) of the LSI chip 33 is flipped TAB21.
Is connected to the wiring formed on the
The first wiring is connected to the ground pad 25 formed on the surface of the package 22, and further connected to the ground layer 34 via the via hole 26.

On the other hand, the power supply pad (not shown) of the LSI chip 33 is connected to the power supply pad 27 of the package 22 through the wiring formed on the flipped TAB 21, and the power supply pad 27 is located at the center of the package 22. It is connected to the external electrode 14 on the upper surface of the parallel plate type capacitor 11 through a large number of wires 40 extending toward the outside. The power supply pad 27 of the package 22 is also connected to the power supply layer 35 via the via hole 28. In addition,
The connection to the pin 43 is made by the ground layer 34 and the power supply layer 3 respectively.
It is performed from 5 through the via hole 29.

Also in the bypass capacitor mounting laminated package shown in FIG. 4, the wiring between the LSI chip (not shown) and the parallel plate type capacitor 11 is short, and the current is not concentrated in one via hole, so that the inductance thereof is small. Since the parallel plate capacitor 11 itself has a small ESL, malfunction of the LSI is unlikely to occur.

With respect to the bypass capacitor mounted laminated package according to the present embodiment (referred to as the second embodiment), the inductance was measured as in the case of the first embodiment.

In this case, the number of wirings from the flipped TAB 21 to the ground pad 25, the wiring from the flipped TAB 21 to the power supply pad 27, the wire 40, the ground pad 25, and the power supply pad 27 are 40, respectively. The results are shown in Table 2 below.

[0045]

[Table 2]

As is clear from the above results, the inductance of the bypass capacitor mounted laminated package according to the second embodiment is further reduced to about 1/5 of that of the conventional one (Comparative Example 1).

As described above, in the bypass capacitor-equipped laminated package according to the embodiment, the inductance is small because the bypass parallel plate capacitor 11 is connected to the bypass chip parallel current path from the LSI chip 33. Further, since the bypass capacitor is the parallel plate capacitor 11, the ESL of the capacitor itself is also small, and as a result, switching noise and the like can be made extremely small, and the malfunction of the LSI can be prevented.

Furthermore, since the structure of the bypass capacitor-mounted laminated package is simple, the bypass capacitor-mounted laminated package can be provided at a low cost.

[0049]

As described in detail above, in the bypass capacitor mounting laminated package according to the present invention, the bypass capacitor mounting laminated package having the cavity and having the LSI chip mounted therein is a parallel plate type for bypass. Since the capacitor is placed inside the cavity and the LSI chip is arranged directly above the bypass parallel plate capacitor or above the bypass parallel plate capacitor, the bypass parallel plate capacitor and the LS are arranged.
By shortening the distance from the I chip, it is possible to shorten the current path for connecting a large number of power supply pads or ground pads prepared on the LSI chip side to the bypass capacitor.

Further, since the bypass capacitor is a parallel plate type, the inductance (E
SL) also becomes small, and the connection between the power supply layer or the ground layer in the laminated package and the external electrode terminal of the capacitor can be directly connected over the entire surface.

That is, in the bypass capacitor mounting laminated package according to the present invention, the inductance between the LSI chip and the bypass capacitor can be reduced, and the inductance (ESL) of the bypass capacitor itself can be reduced. Since it can be made small, switching noise and the like can be made extremely small, and it is possible to provide a bypass capacitor mounted laminated package in which malfunction of the LSI is unlikely to occur.

Further, since the bypass capacitor mounting laminated package has a simple structure, the bypass capacitor mounting laminated package can be provided at a low cost.

[Brief description of drawings]

FIG. 1 is a cross-sectional view schematically showing a bypass capacitor mounted laminated package according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view schematically showing a parallel plate type capacitor used in a bypass capacitor mounting laminated package according to an example.

FIG. 3 is an exploded perspective view schematically showing a parallel plate type capacitor used in the bypass capacitor mounted laminated package according to the embodiment.

FIG. 4 is a cross-sectional view schematically showing a bypass capacitor mounted laminated package according to another embodiment.

FIG. 5 is a cross-sectional view schematically showing a conventional bypass capacitor mounted laminated package.

[Explanation of symbols]

 11 Parallel Plate Type Capacitor 13 Cavity 24 Support Rubber 33 LSI Chip

Claims (1)

[Claims] 1. A bypass capacitor-equipped laminated package having a cavity, on which an integrated circuit chip is mounted, wherein a bypass parallel plate type capacitor is placed inside the cavity, and is directly above the bypass parallel plate type capacitor. Alternatively, the bypass capacitor-equipped laminated package in which the integrated circuit chip is disposed above the support member.