KR19990053512A - Interleaver for downstream transmission of cable transmission system - Google Patents

Abstract

The present invention relates to an interleaver that supports various interleaving modes (I, J) for downstream transmission of a cable transmission system.

In the present invention, 0 processing elements are connected to the 1st tap, 1 processing element is connected to the 2nd tap, 2 processing elements are connected to the 3rd tap in series, and so on. (M-1) processing elements are connected in series to the M-th tap, and the storage units are arranged in a vertical direction, and the storage units are shared and used in each mode according to a control signal. In order to share the storage unit, an input / output commutator for properly distributing a symbol according to a corresponding mode of a control signal is provided.

In the related art, various interleavers were implemented separately, but inefficient. However, the present invention supports all the various interleavers, but has an effect of simplifying the design and reducing the area and the amount of hardware.

Description

Interleaver of the cable transmission system in the downstream direction

The present invention relates to a cable transmission system, and more particularly, to an interleaver that simultaneously supports a reduced interleaving mode and an extended interleaving mode for downstream transmission.

Cable modem network provides various services such as telecommuting, video conferencing, and web search to subscribers by connecting to internet and intranet together with Integrated Information Communication Network (ISDN) and Multi-Digital Subscriber Line (xDSL).

1 is a reference diagram of a cable modem network that supports broadband service. A headend 110 including a cable modem terminal system (111, hereinafter referred to as CMTS) is connected to a backbone network 100 including a private network or a public network provided by a communication network operator. The cable modem (130, Cable Modem: hereinafter referred to as CM) is connected. Between the head end 110 and the CM (130) is located a photoelectric converter (120, Optic / Electro Converter) is connected by the optical cable to convert the optical signal and the electrical signal, the photoelectric converter 120 and the CM (130), The CM 130 and the subscriber side 140 are connected by coaxial cable. Bi-directional communication is possible between the service provider and the subscriber side, and the two bidirectional communication paths are combined at the headend 110. The headend 110 includes a CMTS 111 that enables bidirectional communication, an operation support system for the CMTS 111 (not shown), and a combiner 112 that transmits various application services of an information provider by combining data signals. And a transmission buffer 114, a reception buffer 115 and a distributor 113 for receiving and distributing subscriber request data, and a security and access control unit 116. The CMTS 111 includes a network terminal 111-1 in charge of the CMTS and a network interface, a modulator 111-2 for modulating application service data (downstream data) of an information provider, and request data of a subscriber ( Demodulation section 111-3 for demodulating upstream data). The cable modem network shown in FIG. 1 is a broadband system using RF signals, and an RF interface exists between the CM and the cable network, between the CMTS and the cable network downstream, and between the CMTS and the cable network upstream.

The downstream channel transmitted from CMTS to each CM broadcasts broadband service data at a transmission rate of 50 to 860 MHz, and the upstream channel transmitted from CM to CMTS is 5 to 42 MHz. Send in a point-to-point fashion

The downstream protocol of the cable transmission system is as defined in ITU-T Recommendations J.83, Annex B. The downstream signal processing is shown in FIG. The downstream modulation process is performed by framing the MPEG-2 data stream input in the packet unit from the MPEG frame unit 200, and then performing a forward error correction algorithm in the FEC encoder 210 to perform a channel ( To obtain reliable data. The FEC code output from the FEC encoder 210 is QAM modulated by the QAM modulator 220 and then transmitted through the cable channel 230 as an RF signal. The downstream demodulation is performed through the QAM demodulator 240, the FEC decoder 250, and the MPEG frame unit 260 in a reverse process to modulation. The MPEG framing process provides a parity check pattern for packet synchronization between the transmitter and the receiver. The QAM modulation process supports 64QAM mode and 256QAM mode. The FEC encoding process uses a concatenated coding technique, and an outer coder uses a Reed-Solomon code having T error correction capabilities, and an inner coder. By using the TCM codeword to generate the coded modulation code, the error that is not corrected by the internal decoder is usually corrected by the external decoder so that the error rate is almost zero.

3, the FEC encoder 210 (see FIG. 2) is composed of a Reed Solomon encoder 300, an interleaver 310, a randomizer 320, and a trellis encoder 330. The FEC decoder 250 includes a trellis decoder 350, an inverse randomizer 360, a deinterleaver 370, and a Reed Solomon decoder 380.

The Reed Solomon encoder 300 encodes the MPEG transport stream using a (128,122) RS block code. (128, 122) The RS block code consists of 128 symbols per block, of which only 122 symbols are information symbols and 6 symbols are parity for error correction, so up to 3 symbols per RS block are error corrected. The RS block code is used identically in the 64QAM mode and the 256QAM mode.

The interleaver 310 convolutionally interleaves the (128, 122) RS block codes to rearrange the data streams. The interleaver 310 is for efficiently coping with successive error symbols (cluster errors, burst errors) generated during channel transmission. The convolutional interleaver structure supports a programmable structure, that is, various interleaving modes in 64QAM mode and 256QAM mode.

The randomization unit 320 randomizes the interleaved data so that the interleaved data does not have a specific pattern, thereby preventing the RF-modulated signal from interfering with other channels and extracting synchronization from the receiver. Randomized data is output by generating a pseudo noise code promised with the receiver and adding it to the input data.

The trellis encoder 330 performs trellis coded modulation (TCM). TCM is a channel coding technique for obtaining a high coding gain in a bandwidth-limited channel and is implemented by combining a coding technique and a modulation technique. The TCM structure is composed of a convolutional encoder having a finite state and a QAM modulator (64 / 256QAM).

A process of convolutional interleaving by receiving an RS block code in symbol units in the interleaver 310 will be described with reference to FIG. 4.

4 is a circuit diagram illustrating a convolutional interleaver and a deinterleaver. The convolutional interleaver 400 includes an input commutator 410, a plurality of shift register stages 1 to I, and an output commutator 420. The convolutional deinterleaver 450 is composed of an input commutator 460, a plurality of shift register stages 1 to I having an opposite structure to the convolutional interleaver, and an output commutator 470.

In the shift register structure of the convolutional interleaver, the top tab 1 is directly connected to an input and an output without a shift register, and the shift register length is " 0 ", and from the next taps 2 to I, the " J " "2J", "3J",... , As long as "(I-1) J". The memory difference between successive register tabs stores more "J" symbols than the registers in the previous tab. The register width is 7 bits, which is the same as that of the RS symbol since the RS block code is processed in symbol units.

The shift register structure of the convolutional deinterleaver 450 has a structure opposite to that of the shift interleaver 400. In other words, the top tab 1 has a shift register length of "(I-1) J", and from the next tabs 2 to I, "(I-2) J",... , "2J", "J", "0" has a length as long as.

The input commutator 410 of the convolutional interleaver 400, the output commutator 420, the input commutator 460 of the deinterleaver 450, and the output commutator 470 all operate in synchronization. Data is interleaved by switching sequentially from the first tap to the last I-1 tap according to the symbol clock, and then repeatedly switching from the first tap. Through this switching operation, the first data of the I cycle input to the first tap of the convolutional interleaver 400 is output without a delay, and the second data of the I cycle input to the second tap is input to the third tap after an IJ delay. The third data is after a 2IJ delay,... , The last data of cycle I input to tap I is output after (I-1) IJ delay.

As a result, in the interleaver 400 on the transmitting side, IJ arbitrary symbol data is inserted between two neighboring symbol data in the input data string and transmitted to the convolutional deinterleaver 450 on the receiving side through the channel 430.

The first data of the I cycle input to the first tap of the convolutional deinterleaver 450 is output after (I-1) IJ delay, and the second data of the I cycle to the second tap is (I-2) IJ delay ,… , The last second data of cycle I entered through tap I-1 is output after J delay, and the last data of cycle I entered into tap I is output without delay.

As a result, after the system is operated, the original data stream that was input to the convolutional interleaver 400 after the (I-1) IJ delay is obtained.

In general, the specification of the convolutional interleaver is represented by the (I, J) parameter, where I represents the number of taps in the shift register, which is called an interleaving interval, and J is an interleaving depth representing a register increment between neighboring taps. This is called interleaving depth.

Meanwhile, in the cable transmission system, the interleaver specification supports the reduced interleaving mode and the extended interleaving mode. Among them, the reduced interleaving mode supports five types: (I, J) = (128,1), (64,2), (32,4), (16,8), (8,16). have. There are eight types of extended interleaving modes: (I, J) = (128,1), (128,2), (128,3), (128,4), (128,5), (128,6) , (128,7), (128,8) are supported. Each of the interleavers shown in FIG. 4 according to 13 modes is required. The minimum amount of memory required to design one interleaver as shown in FIG. (symbols).

Therefore, in designing the interleaver according to each mode, the reduced interleaver has 8,128 symbols in (128,1) mode, 4,032 symbols in (64,2) mode, and 1,984 symbols in (32,4) mode. 8) The mode requires 960 symbols and the (8,16) mode requires a register to store 448 symbols. In case of extended interleaver, (128,1) mode is 8,128 symbol, (128,2) mode is 16,256 symbol, (128,3) mode is 24,384 symbol, (128,4) mode is 32,512 symbol, (128,5) mode is 40,640 symbols, (128,6) mode requires 48,768 symbols, (128,7) mode requires 56,896 symbols, and (128,8) mode requires registers to store 65,024 symbols, respectively. In addition, each input / output commutator is required for each interleaver.

This has a problem that the amount of the hardware can not be ignored if implemented in the general logic (LOGIC) or ASIC (custom semiconductor).

Accordingly, the present invention has been made to solve the above problems, the present invention is to provide a multi-mode interleaver that simultaneously supports the reduced mode and extended mode by using a part of the shared memory according to the mode. There is this.

In order to achieve the above object, the present invention provides an interleaving interval I (an integer of I≤M, M is a maximum value of a multimode interleaving interval) and an interleaving depth J (an integer of 1≤J). In interlacing interleaving in various interleaving modes (I, J), the input commutator for distributing and outputting the input symbols according to the control signal for distinguishing the interleaving mode; 0 processing elements are connected to the 1st tap, 1 processing element is connected to the 2nd tap, 2 processing elements are connected to the 3rd tap in series,... (M-1) processing elements are connected in series to the M th tap, and the symbols output from the input commutator are stored in the processing element of the corresponding tap and stored in the vertical direction. A storage unit for selectively outputting a corresponding symbol accordingly; And an output commutator for receiving and outputting symbols of the storage unit according to the control signal.

1 is a reference configuration diagram of a cable modem network supporting broadband services;

2 is a block diagram showing a downstream signal processing procedure of a cable transmission system;

3 is a detailed block diagram of a forward error correction unit of FIG. 2;

4 is a detailed circuit diagram of the interleaver / deinterleaver of FIG.

5 is a block diagram of an interleaver for downstream transmission according to the present invention;

FIG. 6 is a detailed circuit diagram of the processing element of FIG. 5.

Explanation of symbols on the main parts of the drawings

500: input commutator 510: storage unit

520: output commutator PE: processing element

R1 to R8: Shift register MUX: Multiplexer

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

This embodiment relates to reduced and extended interleaving modes supported in both 64QAM / 256QAM modes of a cable transmission system. The parameters of reduced and extended interleaving modes and corresponding mode control signals are shown in Table 1.

Mode symbol Control signal (4 bits) I (# of taps) J (increment) Burst Defense R1_MODE 0001 128 One 95㎲ / 66㎲ R2_MODE 0011 64 2 47㎲ / 33㎲ R3_MODE 0101 32 4 24㎲ / 16㎲ R4_MODE 0111 16 8 12㎲ / 8.2㎲ R5_MODE 1001 8 16 5.9㎲ / 4.1㎲ E1_MODE 0000 128 One 95㎲ / 66㎲ E2_MODE 0010 128 2 190㎲ / 132㎲ E3_MODE 0100 128 3 285㎲ / 198㎲ E4_MODE 0110 128 4 379㎲ / 264㎲ E5_MODE 1000 128 5 474㎲ / 330㎲ E6_MODE 1010 128 6 569㎲ / 396㎲ E7_MODE 1100 128 7 664㎲ / 462㎲ E8_MODE 1110 128 8 759㎲ / 528㎲

In Table 1 above, the interleaving parameters I and J are appropriately selected for a given channel, and these parameter values are also related to burst defenses. It can be seen from Table 1 that the reduced interleaving modes (R1_MODE to R5_MODE) decrease I when the value of I × J is constant and burst defense decreases as J increases. In the extended interleaving mode (E1_MODE to E8_MODE), when I is constant, the burst defense increases as J increases. The control signal (4 bits) of the interleaving mode is transmitted to the receiving side during the FEC frame synchronization interval, and the receiving side performs deinterleaving of the corresponding mode for a given channel.

5 is a block diagram of an interleaver supporting reduced and extended modes for downstream transmission according to the present invention. The interleaver uses an RS block data stream consisting of 128 RS symbols in reduced (128, 1), (64, 2), (32, 4), (16, 8), (8, 16) mode or Extended mode (128,1), (128,2), (128,3), (128,4), (128,5), (128,6), (128,7), (128,8) It consists of an input commutator 500, a storage unit 510 and an output communicator 520 to weaving interleaving to any one.

Since the maximum interleaving interval in the thirteen modes is 128 (= M), the storage unit 510 has 128 tabs arranged in a vertical direction, and each i-th tab stores (i-1) for storing an input symbol. Processing elements PE are arranged in series. That is, there is no processing element PE at the first tap, one processing element PE is connected at the second tap, two processing elements PE are connected at the third tap in series, and so on. On the 128th tap, 127 processing elements (PEs) are connected in series.

As shown in FIG. 6, eight registers R1 to R8 that store one input symbol per register are connected in series, and the input symbol is input to R1 as shown in FIG. 6. Whenever the next symbol is input, one symbol is sequentially shifted, and among the symbols output from the R1, R2, R3, R4, R5, R6, R7, and R8 registers through the multiplexer (MUX) according to the control signal, A symbol delayed by the interleaving depth J is selected and output. The first processing element of each tap receives and outputs a symbol from the input commutator 500, and its output is passed to the next connected processing element, and the output of the last processing element is passed to the output commutator 520. The registers R1 to R8 of the processing elements PE may be implemented as serial input parallel output shift registers.

The input commutator 500 and the output commutator 520 are synchronized with each other according to a control signal to switch to the same tap (tap of the storage unit 510). The control signal uses four bits that distinguish the thirteen modes (reduced 5 mode + extended 8 mode) shown in the table. The reduced mode or the extended mode is distinguished according to the LSB bit of the control signal. If LSB = 1, it is reduced mode. If LSB = 0, it is extended mode. Storage unit connected to input / output commutator 500,520 according to (128,1), (64,2), (32,4), (16,8), (8,16) mode in reduced mode The tab number of 510 is determined. On the other hand, in the extended mode, the tap order of the storage unit 510 connected to the input / output commutators 500 and 520 regardless of the mode type is sequentially connected while increasing from 1 to 128 taps. Repeat from tab one again.

First, a case in the reduced mode of the present embodiment will be described with reference to FIGS. 5 and 6, and a case in the extended mode will be described next.

１. Miniature mode

1-ⅰ. First embodiment

Referring to FIG. 5, the tap number order of the input / output commutators 500 and 520 determined according to the control signal in the reduced mode is as follows. In taps 1 to 128 in (128,1) mode, taps 1 to 64 in (64,2) mode, taps 1 to 32 in (32,4) mode, (16,8) In the mode, the input symbols are allocated by sequentially switching to taps 1 to 16 according to the symbol clock. In the case of (8,16) mode, it is allocated in the order of 1, 3, 5, 7, 9, 11, 13, 15. The tap number order is an order of switching for each period using the interleaving interval I as one period.

Referring to FIG. 6, among the symbols stored in the eight registers R1 to R8 of each processing element PE are selected according to the control signal as follows. Symbol of R1 in (128,1) mode, symbol of R2 in (64,2) mode, symbol of R4 in (32,4) mode, symbol of R8 in (16,8) mode, (8 (16) In mode, select and output the symbol of R8.

The operation of the embodiment for the (128,1) and (64,2) modes will be described by applying the above rules.

① (128,1) mode

In the (128,1) mode, the input / output commutator 500 or 520 increases by 1 from the first tap to the 128 tap of the storage unit 510 with the 128 symbol clock as one cycle by the control signal (0001). The connected taps in sequence. The input / output commutator 500,520 switches to the next tap in synchronization with the symbol clock, and repeats it starting from the first tap after 128 symbol clocks (1 → 2 → 3,…, 128 → 1 → 2…). ).

Each processing element PE of the storage unit 510 selects and outputs the contents of the register R1 delayed by one symbol from the eight registers by the control signal 0001. The first symbol data of the period input to the first tap of the storage unit 510 is output without delay, the second symbol data to the second tap is 128 × 1 delay, and the third symbol data to the third tap is 128 After the delay of × 2,... The last symbol data of the cycle input to the 128 tap is output after the delay of 128 × 127. As a result, interleaving is performed in which (128 × 1) arbitrary symbol data are inserted between two neighboring symbol data in the original input data stream.

② (64, 2) mode

In the (64, 2) mode, the input / output commutators 500 and 520 set the 64 symbol clocks as one cycle by the mode control signal (0011), one by one from the first tap to the 64 tap of the storage unit 510. The increased taps are switched in sequence. At this time, the input / output commutator 500, 520 switches to the next tap in synchronization with the symbol clock, and repeats the operation starting from the first tap again after 64 symbol clocks (1 → 2 → 3,…, 64 → 1 →). 2…).

Each processing element PE of the storage unit 510 selects and outputs the contents of the register R2 delayed two symbols from the eight registers by the control signal 0011. The first symbol data of the period input to the first tap of the storage unit 510 is output without a delay, the second symbol data to the second tap is 64 × 2 delay, and the third symbol data to the third tap is 64 After the delay of × 4,... , The last data of the cycle entered into tap 64 is output after the 64 × 126 delay. As a result, on the transmitting side, interleaving is performed in which (64 × 2) arbitrary symbol data are inserted between two adjacent symbol data in the input data string.

As shown in the ① and ② modes, the switching order of the input / output commutators 500 and 520 and the respective processing elements (PE) are also described in the remaining (32, 4), (16, 8) and (8, 16) modes. The same procedure is followed according to the output symbol rule of. As a result, in (32,4) mode, interleaving is performed by inserting (32 × 4) arbitrary symbol data between two neighboring input symbol data, and in (16,8) mode (16 × 8) random In the symbol data, in the (8, 16) mode, interleaving is performed in which (8x16) arbitrary symbol data are inserted.

1-ii: Second embodiment

In the reduced mode, the tap number order of the input / output commutators 500 and 520 determined according to the control signal is as follows.

5, the (128,1) mode is 1,2,3,4,... , 127,128,1,2... Tab, and the (64, 2) mode is 1, 3, 5, 7,... , 125,127,… , 1,3,… Connected to the second tap. 32, 4 modes are 1, 5, 9, 13,. , 121,125,1,5... Tab, and (16,8) modes are 1, 9, 17, 25,... , 113,121,1,9,... Connected to the second tap. (8,16) modes are 1,17,33,49,... , 97,113,1,17... Connected to the second tap. That is, switching starts from the first tap for one period corresponding to the interleaving interval I and is connected to the tap increased by the interleaving depth J of each mode, and then the next cycle is repeated again from the first tap.

Referring to FIG. 6, in the reduced mode, a symbol of register R1 is selected and output from the symbols stored in eight registers R1 to R8 of each processing element PE regardless of five modes.

The operation of the embodiment for the (32,4) mode will be described by applying the above rules.

In the (32, 4) mode, the input / output commutators 500 and 520 use the 32 symbol clocks as one cycle by the mode control signal 0101, and the taps increased by 4 from the first tap of the storage unit 510. Switching connection in sequence. At this time, the input / output commutator 500, 520 switches to the next tap in synchronization with the symbol clock, and starts repeatedly from the first tap after 32 symbol clocks (1 → 5 → 9,…, 125 → 1 →). 5…).

The first symbol data of the period input to the first tap of the storage is output without delay, the second symbol data to the 5th tap is 32 × 4 delayed, and the third symbol data to the 9th tap is 32 × 8 delayed. ,… , The last data of the cycle entered into tap 32 is output after 32 × 124 delay. As a result, on the transmitting side, interleaving is performed in which (32 x 4) arbitrary symbol data is inserted between two adjacent symbol data in the input data string.

As shown in the (32,4) mode, the rest of the (128, 1), (64, 2), (16, 8), and (8, 16) modes also have Since the same goes according to the switching order and the output symbol rule of each processing element (PE), description of each mode is omitted.

2. Expandable mode

Referring to FIG. 5, in the extended mode, the input / output commutators 500 and 520 increase by one tap according to the symbol clock from the 1st to 128th taps with a period of interleaving interval 128 (= I) by a control signal. The input symbols are distributed by sequentially switching the taps.

Referring to FIG. 6, among the symbols stored in the eight registers R1 to R8 of each processing element PE are selected by the control signal as follows. Symbol of R1 in (128,1) mode, symbol of R2 in (128,2) mode, symbol of R3 in (128,3) mode,... In the (128,8) mode, a symbol delayed by the interleaving depth J is selected and output in each processing element PE.

The operation of the embodiment for the (128,1) and (128,2) modes will be described by applying the above rules.

① (128,1) mode

In the (128,1) mode, the input / output commutator 500 or 520 increases by 1 from the 1st tap to the 128th tap of the storage unit 510 with the 128 symbol clock as one cycle by the control signal 0000. The connected taps in sequence (1 → 2 → 3,…, 128 → 1 → 2…). The input / output commutators 500 and 520 switch to the next tap in synchronization with the symbol clock, and start repeatedly from the first tap after 128 symbol clocks.

Each processing element PE of the storage unit 510 selects and outputs the contents of the register R1 delayed by one symbol from the eight registers by the control signal 0000. The first symbol data of the period input to the first tap of the storage unit 510 is output without delay, the second symbol data to the second tap is 128 × 1 delay, and the third symbol data to the third tap is 128 After × 2 delay,... The last symbol data of the cycle input to the 128 tap is output after the delay of 128 × 127. As a result, interleaving is performed in which (128 × 1) arbitrary symbol data are inserted between two neighboring symbol data in the original input data stream.

② (128,2) mode

In the case of (128, 2) mode, the input / output commutator 500, 520 in accordance with the control signal (0010) in order from the tab 1 to the tap 128 of the storage unit 510 according to the symbol clock during 128 symbol clock (1 period) Switch to distribute the input symbols.

By the mode control signal 0010, each processing element PE selects and outputs the output of the register R2. The first data of the cycle input to the first tap of the storage unit 510 is output without a delay, the second data of the cycle input to the second tap is 128 × 2 delay, and the third data to the third tap is 128 × 4 After the delay,… The last data of the cycle entered into the 128 tap is output after the delay of 128 × 254. As a result, on the transmitting side, interleaving is performed in which (128 x 2) arbitrary symbol data is inserted between two adjacent symbol data in the input data string.

As shown in the ① and ② modes, the switching order of the input / output commutators 500 and 520 and the respective processing elements (PE) are also described in the remaining I = 128, J = 3,4,5,6,7,8 modes. Since the process proceeds similarly according to the output symbol rule (symbol delayed by the interleaving depth J), the operation for each mode is omitted below.

As described above, the present invention shares a memory (storage unit 510) to support both the reduced and extended interleaving 13 modes of the cable transmission system, and the memory selectively selects a symbol of the corresponding mode according to a control signal. It consists of a number of processing elements that are output. In addition, the input commutator 500 properly distributes the input symbols to the input side of the storage unit by the control signal, and the output commutator 520 is provided to the output side of the storage unit to perform interleaving in each mode. That is, the present invention is designed to program each processing element (PE) of the input / output commutator (500, 520) and the storage unit 510 so that (I × J) between two adjacent symbol data for each (I, J) mode J) Interleaving is performed in which arbitrary symbol data is inserted.

As a result of the memory sharing, the amount of memory is much reduced compared to the conventional method. In fact, the total register capacity used when the 13 modes were separately designed was 408,160 symbols, but the total register capacity required in the embodiment of the present invention was used. Is 65,024 symbols.

In the present specification, the present invention has been described only in connection with specific embodiments. However, the present invention can be applied to a programmable interleaver employing various interleaving modes, and those skilled in the art can variously implement the technology within the scope of the claims and embodiments. have.

In the related art, various interleavers were implemented separately, but inefficient. However, the present invention has implemented one interleaver that supports both the reduced and extended interleaving 13 modes of the cable transmission system. According to the present invention, the memory is shared by appropriately distributing the symbols of the corresponding mode according to the control signal, so that the design is simple and the area and hardware amount can be reduced. Compared to the conventional interleaver, there is an effect of reducing 1/6 times in terms of memory.

Claims (6)

A block data stream consisting of N symbols is divided into various interleaving modes (I, J) having an interleaving interval I (an integer of I≤M, M is a maximum value of a multimode interleaving interval) and an interleaving depth J (an integer of 1≤J). In weaving interleaving, An input commutator for distributing and outputting an input symbol according to a control signal for distinguishing an interleaving mode; 0 processing elements are connected to the 1st tap, 1 processing element is connected to the 2nd tap, 2 processing elements are connected to the 3rd tap in series,... (M-1) processing elements are connected in series to the M th tap, and the symbols output from the input commutator are stored in the processing element of the corresponding tap and stored in the vertical direction. A storage unit for selectively outputting a corresponding symbol accordingly; And And an output commutator for receiving and outputting the symbols of the storage unit according to the control signal and outputting the symbols. 2. The apparatus of claim 1, wherein each of the processing elements comprises: a serial input parallel output shift register sequentially shifting one symbol each time an input symbol is input while predetermined registers for storing the input symbols are connected in series; And And a multiplexer for selecting and outputting a symbol delayed by an interleaving depth of a corresponding mode according to a control signal among parallel output symbols of the shift register. The interleaver of claim 1, wherein the input commutator and the output commutator are connected by switching to the same one of the M taps of the storage unit every symbol clock. The tap of claim 3, wherein when the parameter IJ = N of the interleaving mode (I, J) is constant, the connected taps are sequentially increased by +1 tap starting from the first tap of every cycle with the interleaving interval I as one period. Interleaver for downstream transmission of a cable transmission system, characterized in that it switches to the last I-th tap, such as a According to claim 3, When the parameter IJ = N of the interleaving mode (I, J), the connected tap is increased by the interleaving depth + J starting from the first tap of every cycle with the interleaving interval I as one period Associated with the tab; And selecting a symbol delayed by one symbol among contents of a predetermined register of the processing element. 4. The method according to claim 3, wherein when the parameter I = N of the interleaving mode (I, J) is constant, the connected taps include a tap that is increased by +1 starting from the first tap of every cycle with the interleaving interval I as one period. Connected; And selecting a symbol delayed by an interleaving depth J symbol from contents of a predetermined register of the processing element.