GB2332836A - Adaptive convolutional interleaver and deinterleaver - Google Patents

Abstract

A sequence of symbols is adaptively interleaved based on a control word corresponding to one of a plurality of interleaving modes. The interleaver 100 comprises a storage block 150 providing taps P 1 -P 128 , with an ith tap having (i-1) processing elements PE. Each processing element consists of eight storage units connected in series (R1-R8, figure 5) and a multiplexer (300) for selecting, as an output, a symbol from one of the storage units. The control word dictates the number of taps utilised during the interleaving process and the symbol delay in each processing unit. The symbols are interleaved through the sequential and iterative switching operations of input and output commutators 110, 120 to the selected number of taps. A corresponding deinterleaver is disclosed (figure 4). The interleaver/deinterleaver is applicable to digital cable television systems using 64-ary or 256-ary QAM.

Description

ADAPTIVE CONVOLUTIONAL INTERLEAVER AND DEINTERLEAVER The present invention relates to a digital communication system ; and, more particularly, toaconvolutional interleaver and deinterleaver for use in a digital communication system.

In a digital communication system, there may occur transmission errors caused by channel impairments, e. c., noise, fading and jamming.

In order to remove or reduce the transmission errors, therefore, various channel coding methcds have been developed as error correction coding methods. The error correction coders to correct the transmission errors are typically classified into two groups, i. e., block coders and convolutional coders.

It is well-known in the art that the so-callec forward error correction (FEC) coding method provided with both a block coding technique and a convolutional coding technique is very effective to detect and correct transmission errors, thereby achieving a fast real-time processing thereof.

A FEC coding process is usually carried out by using a concatenated coder which employs two levels of coders, i. e., both an inner coder and an outer coder, to achieve the desired error correction performance. The inner coder, the one that interfaces with a modulator and a channel, is usually configure to correct : most of the channel errors. The outer coder, usually a higher-rate (lower-redundancy ; coder, then reduces the probability of errors a a specified level.

-ne of the e most popular concatenated coding systems dses a convolutional inner coder and a Reed-Solomon (R-S) outer coder as a block coder.

A block coder, e.g., a R-S coder, is a coder mapping K input binary symbols into L output binary symbols, wherein L and K are positive integers, respectively, L being greater than K. The block coder provides redundancies, such as Parity bits, which are used by a decoder to provide some error detection and error correction ab lity.

With the block coder, however, it is very difficult tc correct burst errors including a relatively large number of correlated errors amcng successive symbols. A solution to the burst error problem is to interleave data symbols, prior to the transmission thereof, so that burst errors affecting a succession of the interleaved data symbols will be spread apart when the data symbols are-deinterleaved at a receiver.

That is, by interleaving an output data sequence from the block coder and deinterleaving the data sequence prior to decoding, the burst errors are distributed more uniformly at an input data sequence of a decoder.

Referring to Fig. 1, there is shown a schematic block diagram o cable transmission processing in a conventional digital cable television system, wherein the system comprises a transmitter including a motion picture expert group (MPEG) framing block 21, a forward error correction (FEC) encoder 22, a quadrature amplitude modulation (QAM) modulator 23, a channel 24, and a receiver including a QAM demodulator 25, a -nC decoder 26 and a MPEG t=aminc b-oc : 1 27.

The MPEG framing block 21 receives the so-called MPEG-2 transport data stream consisting of continuous digital data stream of a fixed length, e. g., 188 byte packets. For carriage of transport protocols, e. g., asynchronous transfer mode (ATM), other than the MPEG-2 transport, the MPEG framing block 21 can be bypassed.

The FEC encoder 22 uses various types of error correcting algorithms and interleaving techniques such as R-S coding, interleaving, randomization and trellis coding ; and the QAM modulator 23 uses 64-ary QAM or 256-ary QAM. The receiver performs operations of the transmitter in a reverse order.

(For the sake of simplicity, a detailed description on the operation of the receiver is omitted.) More specifically, the FEC encoder 22 includes a R-S encoder 22-1, an interleaver 22-2, a randomizer 22-3 and a trellis encoder 22-4 ; and the FEC decoder 26 includes a trellis decoder 25-1, a derandomizer 26-2, a deinterieaver 26- 3 and a R-S decoder 26-4.

The R-S encoder 22-1 performs R-S encoding by using a (128, 122) R-S code which is capable of correcting up to three symbol errors per one R-S block, wherein each R-S block contains 128 R-S code symbols and each code symbol consists of 7-bits.

The interleaver 22-2 evenly disperses the R-S code symbolsintheR-Sblockinordercoprotectthemagainsta burst of symbol errors.

The randomizer 22-3 randomizes the interleaved data outputted from the interleaver 22-2 in time distribution to thereby ailow the QAM demodulator 25 to syncnron-ze e fec-ively The trellis encoder 22-4 encodes the randomized data through the use of a convolutional encoding technique.

In the FEC encoder 22, the interleaver 22-1 will be described in terms ouf ils burst error correction performance.

An interleaver is a device that rearrances or permutes a sequence of R-S code symbols in a predetermined manner.

Referring to Fig. 2, there is provided an interleaving functional block diagram employing an interleaver 40, a deinterleaver 50 and a channel 60 (see ITU-T Recommendation J 83, Digital Multi-Programme Systems for Television Sound and Data Services for Cable Distribution, Television and Sourd d Transmission, International Telecommunication Union Telecommunication Standardization Sector, October 1995).

The interleaver 40 has an input commutator 42, T number of taps Ti to Tl, I being a predetermined inteaer and an output commutator 44 ; and the deinterleaver 50 has an input commutator 52, I number of taps P to ?. and an output commutator 54.

R-S coded data, containing a sequence o~ R-S code symbols which are encoded by an encoder, e. g., the R-5 encoder 22-1 in Fig. l, is inputted to the interleaver 40. The interleaver 40 performs an interleaving process on the R-S coded data to thereby provide interleaved data to he channel 60.

On the other hand, the deinterleaver 5C performs an deinierleaving process on the interleaved data transmitted thereto via the channel 60 to thereby provide deinterleaved data to an outer coder, e. g., the R-S decoder 26-4.

Hereinafter, the convolutional interleaving and deinterleaving processes are illustrated with reference to the interleaver 40 in Fig. 2.

The R-S code symbols are sequentially shifted into a bank of taps ; each successive tap provides a storage bigger by a J number of more symbols than a preceding one, J being a positive integer. The top-most tap provides no storage, i. e., the first symbol is transmitted immediately. with each new code symbol, the input commutator 42 switches to a new tap, and the new code symbol is shifted thereinto wh-le the oldest code symbol in that tap is shifted out to a next circuit.

After switching to an Ith tap, the input commutator 42 returns to the top-most tap and starts again. The deinterleaver 50 performs an inverse operation in comparison with the operation in the interleaver 40 and the input and output commutators for both interleaving and deinierleaving must be synchronized.

Through the interleaving and deinterleaving processes, burst noises in the channel 60 causing a series or bad symbols are spread over many R-S blocks by the deinterleaver 50 such that the resultant symbol errors per R-S block are within a range of the R-S decoder correction capability.

With regard to the interleaving capability, two distinct operating modes are specified, hereafter being referred to as level 1 and level 2.

The level 1 is specified for 64-ary QAM transmission only and accommodates the installed base of legacy 64-ary QAM-only digital set tops. While operating in level 1, a single interleaving depth is supporte ; namely I=128 and J=l, I and J representing interleaving parameters, respectively.

The level 2 encompasses 64-ary QAM and 256-ary QAM transmission and is capable of supporting var-able interleaving for both modulation schemes. This includes both enlarged and reduced interleaving depths relative to, e. g., the nominal 54-ary QAM (level li configuration. For the enlarged and reduced interleaving aepths, four data bits are used to convey the interleaving parameters to the receiver for a given channel, the four data bits specifying, e. g., 13 interleaving modes associated with the interleaving depths.

In Table ~, there are described the interleaving modes classified by the interleaving parameters (I, J) for level 2 operation, and also associated with burst protectionand latency, wherein I represen-s the number of taps and @ depicts a symbol storage difference between two successive taps (see ITU-T recommendation J. 83, October 1995, p. 16) Table 1

ControlBurseLatency WordIJProtection64QAM/256QAM 64QAM/256QAM 001 128 1 95 s/66 s 4.0ms/2. 8ms 0011 64 2 47 s/33 s 2.0ms/1. 4ms 0101 32 4 24 s/16 s 0.98ms/0.68ms 0111 16 8 12ps/8. 2Ss 0. 48ms/0. 33ms 1001 8 16 5.9 s/4.1 s 0.22ms/0.15ms 000 128 1 95 s/66 s 4.0ms/2. 8ms 0010 128 2 190 s/132 s 8,0ms/5. 6ms 0100 128 3 285 s/198 s 12ms/8.4ms 0110 128 4 379 s/264 s 16ms/11ms 1000 128 5 474 s/330 s 20ms/14ms 1010 128 6 569 s/396 s 24p/17ms 1100 128 7 664 s/462 s 28ms/19ms 1110 128 8 759 s/528 s 32ms/22ms In Table 1, the 4-bit control words whose least signficant bits (LSBs) show a binary value'1'represent the reduced interleaving modes, i. e., (128, 1), (64, 2), (32,4), (16, 8) and (8, 16) modes ; and those whose LSBs show a binary value'0'depict the enlarged interleaving modes, 1. e., (128, 1), (128, 2), (128, 3), (128, 4), (128, 5), (128, 6), (128, 7) and (128, 8) modes.

An interleaver (and a deinterleaver) performing an operation of each of the interleaving modes shown in Table 1 can be constructed by6 applying the interleaving parameters I and J which are adjusted according to the interleaving modes to the interleaver 40 (and deinterleaver 50) That is, for (128, 1) mode represented by a control word 'OOC1'or'0000', since it has the interleaving parameters of I=128 and J-1, it includes 128 taps and its symbol storage difference becomes a one symbol size, i. e., 7 bits. In the interleaving process of the above mode =or one R-S block containing 128 R-S code symbols, the first R-S code symbol among the 128 R-S code symbols is outputted without delay via the input commutator 42, the first tap T1 contalning no register and the output commutator 44 ; the second symbol is inputted to che second tap T and delayed by a registrer, storing one symbol, included in the second tap T2 so that it has I*J, i. e., 128*1, symbol periods of delay ; the third symbol is delayed by a register, storing two symbols, within the third tap T3 so that it has 2*I*J, i. e., 2*128*1, symbo- periods of delay, and so on, up-to the 128th R-S code symbol which has (I-1)*I*J, i. e., 127*128*1 symbol periods of delay occurring at a register, storing (1-1) *J, ;. e., 127*1, symbols, positioned a the Ith, i. e., 128th, tap.

Accordingly, two successive R-S code symbols in the R-S block are separated from each other by 128 interleaving symbols inserted therebetween.

For (64, 2) mode represerted by a control word'0011', since it has the interleaving parameters of I=64 and J=2, it includes 64 caps and its symbol storage differencebecomesa two symbol size, i. e., 2*7 bits. In the inter eavinJ process of the above mode for one R-S block containing ~28 R-S code symbols, the f-rst R-S code symbo among the : 28 R-S ccde symbols is outputted without delay via the input commutator 42, the first tap T and the output commutator 44 ; the second c. symbol is delayed by a register, storing two symbols, located at the second tap T2 so that it has I*J, i.e., 64*2, symbol periods of delay ; the third symbol is delayed by a register, storing four symbols, positioned at the third tap T3 so that it has 2*I*J, i. e., 2*64*2, symbol per-ods of delay, and so on, up to the 128th R-S code symbol which has (I-1) *I*J, i. e., 63*64*2 symbol periods of delay occurring at a register, storing-'L. e., 63*2, symbols, positioned at the Ith, e. g., 64th, tap. Accordingly, two successive R-S code symbols in the R-S block are also separated from each other by 128 interleaving symbols inserted therebetween as well as in (128, 1) mode. However, an end-to-end delay, i. e., 63*64*2 symbols, for interleaving 128 R-S code symbols is reduced compare with 127*128*1 of (128, 1) mode. Therefore, it can be seen that the end-to-end delay of each of the reduced interleaving modes decreases as the mode changes from (128, 1) mode to (8, 15) mode.

Meanwhile, for the enlarged interleaving modes, e. g., (12S, k, mode, since it : has the interleaving parameters of I=128 and J=k, k ranging from 1 to 8, it includes 12S laps and its symbol storace difference becomes a k symbol size, i. e.

K*7 bits. In the interleaving process of the above mode ofr one R-S block containing 128 R-S code symbols, the first R-S code symbol among the-28 P-S code symbols is outpuited without delay via the input commutator 42, the first tap T1 containing no register and the output commutator 44 ; the second symbol is inputted to the second tap Tz and delayed by a register, storing k symbols, included in the second tap T2 so that it has I*J, i. e., 128*k, symbol periods of delay ; the third symbol is delayed by a registrer, storing 2*k symbols, within the third tap T3 so that it has 2*I*J, i. e., 2*128*k, symbol periods of delay, and so on, up to the 128th R-S code symbol which has (I--) *I*J, i. e., 127*128*k symbol periods of delay occurring a a register, storing (I-1)*J, i.e., 127*k, symbols, positioned at the Ith, e. g., 128th, tap.

Accordingly, two successive R-S code symbols in the R-S block are separated from each other by 128*k interleaving symbols inserted therebetween. There-fore, as k increases, two successive R-S symbols are separated from each other by a larger number of interleaving symbols and the end-to-end delay, i. e., 127*128*k, also becomes longer.

As shown in the above, since the interleaving modes are dependent on the interleaving parameters I and J, the interleavers and deinterleavers corresponding to the respective interleaving modes have cifferen structures in order to perfore their respective interleaving processes.

Since, however, in order to adaptively perform the interleaving modes, the digital communication system should have an interleaver and a deinierleaver for each of the : e reduced and enlarged interleaving modes ; and, therefore, the digital communication system may be unnecessarily complicated.

If is, therefore, an object of the present invention to provide an adaptive convolutional interleaver and deinterleaver capable of selectively performing reduced and enlarged interleaving modes in response to a 4-bit control word representing each of the interleaving modes.

In accordance with the present invention, there is provided an apparatus for adaptively interleaving a sequence of symbols in response to a control word corresponding to any one of (I, J) interleaving modes, wherein I represents the number of taps and J depicts a symbol storage difference between two successive taps, which comprises : storage means for providing ? number of taps, P being larger than or equal to I, to interleave the sequence of symbols, wherein an ith tap contains (i-1) number of processing elements, i ranging from 1 to P, and each processing element stores T symbols and outputs each stored symbol aster a Q symbol delay, T being a positive integer smaller than P and Q being a positive integer smaller than or equal to T; input commutating means for sequentially and iteratively switxching to I nbumber of taps selected from th P number of G:StOV=Ci EuCSVT.'JJ11'~~"1 S2CL:::.^~2CliSt processing element of a currently switched tap; and output commutating means for sequentially and iteratively switching to the I number of taps to read out a symbol stored at a last processing element of the currently switched tap, wherein the operations of the storage means and the input and output commutating means are commonly controlled by the contrcl word and Q is changed in response to the control word.

The above and other objects and features of the present invention will become apparent from the following description of preferred embodiments given in conjunction with the accompanying drawings, in which : Fig. 1 shows a schematic block diagram of a conventional cable transmission network ; Fig. 2 provides an interleaving functional block diagram ; Fig. 3 represents an interleaver in accordance with the present invention ; Fig. 4 offers a deinterleaver in accordance with the present invention ; and Fig. 5 supplies an exemplary block diagram of the processing element shown in Figs. 3 and4.

Referring to Figs. 3 and 4, there are provided an interleaver and a deinterleaver in accordance with the present invention, respectively. The interleaver and deinterleaver are applied for reduced interleaving modes, i. e. (128, 1), (64, 2), (32, 4), (16, 8) and (8, 16) modes, and enlarged interleaving modes, i. e., (128, 1), (128, 2), (128, 3), (128, 4), (128, 5), (128, 6), (128, 7) and (128, 8) modes, which are specified by control words having 4-bit data as shown in Table 1. Therefore, hereinafter, the operations and structures of the interleaver and deinterleaver will be described in connection with the aforementioned modes.

In Fig. 3, an interleaver 100 comprises an input commutator 110, a storage block 150 and an output commutator 120, which are commonly controlled by a control signal corresponding to any one of the control words described in Table 1.

For (I, J) mode representing any one of the above 13 modes, since the maximum interleaving interval is 128, the storage block 150 includes 128 taps, e. g., T, to T28, vertically aligned and an ith tap has (i-1) number of processing elements connected in series, i ranging from 1 to 128. Therefore, the top-most tap, i. e., the first. ap T1, has no processing element and the bottom-most tap,-. e., the 128th tap T128 has 127 processing elements connected in series.

Referring to Fig. 5, there is offered an exemplary block diagram of the processing element PE shown in Figs. 3 and4.

The processingelementPEhascstorageunits,e.g.,Rl to R8, connected in series and a ru ~lplexer 3CC, each storace unitstoringonesymboltherein.Inaccordancewithan embodiment of the present invention, the storage unit empolys a register performing a serial input, and a parallel outpst.

An input symbol fed to the first storage unit Rl is shifted into a next storage unit whenever another input symbol is coupled to the first storage unit Ri, and is outputted via the multiplexer 300 after being delayed by a preset number of symbols. That is, in response to the control signal, the multiplexer 300 selects one of the outputs of the 8 storage units Rl to R8 which is delayed by the preset number of symbols, to thereby provide the selected symbol as an output symbol.

Therefore, referring back to Fig. 3, the processing element of each tap receives the input symbol from the input commutator 110 and outputs its delayed symbol to an adjacently connected processing element ; and the last processing element of each tap outputs its delayed symbol to the output commutator 120.

The input and output commutators 110 and 120 are synchronized te switch to a same tap in the storage block 15C in response to the control signal. In this case, taps selected by the commutators 110 and 120 controlled by the control signal vary dependent upon an interleaving T. ode corresponding to the control signal. That is, the number of the selected taps is identical to the variable T, i. e., one of 128, 64, 32, 16 and 8. Furthermore, as shown above,the symbol delay at the processing element depends on the control signal.

Therefore, by controlling the multiplexer 300 in each processing element and the commutators 110 and 120 in response to the control signal, the interleaver 100 can adaptively perform the interleaving processes of the reduced and enlarged interleaving modes.

Hereinafter, the operation of the interleaver 100 will be illustrated for several modes with referer~ce to Figs. 3 and 5.

First of all, for (128, 1) mode, for which I=128 and J=1, the input and output commutators 110 and 120 sequentially switch to 128 number of taps, i. e., T to Ta28 in the storage block 150 and the multiplexer 300 in each processing element provides the output of the first storage unit R1 as its output symbol. Therefore, an R-S code symbol fed to the first tap Ti via the input commutator 110 is outputted via the output commutator 120 without delay ; and a subsequent symbol is inputted to the second tap T2 and then outputted via the output commutator 120 when the input commutator 110 switches to the second tap T2 at a next time. That is, after 128*1 symbol periods o delay, the symbol stored at the second ~ap T2 is outputted via theoutputcommutator123.Throughthe same procedure as shown above, the respective R-S code symbols fed to the respective taps in the storage block 150 are delayed by (i-1)*128*1 symbol periods before being outputed via the output commutator 120 as-nterleaved data. As a result, two successive symbols are separated from each other by 128 interleaving symbols inserted therebetween.

For (64, 2) mode, since it has the interleaving parameters of I=54 and J=2, it needs 64 taps and the R-S code symbol inputted o an ith tap should be delayed by a storage capable of storing (j-l) *2 symbols wherein, j ranging from 1 to 64. In order to satisfy the above conditions, there are two choices : one is to select taps T1, T2, T3, . T64 in which the multiplexer 300 ine ach processing element chooses an output of the second storage uni, R2 as its output symbol ; and the other is to select taps T1, T3, T5, ..., T127 in which the multiplexer 300 selects an output of the first storage uni.

R1 as its output symbol. The above tap selection is carried out by controlling the operations of the input and output commutators 110 and 120 through the use of the control signal.

In the above two cases, although their tap selections are different from each other, their symbol delays are identical sir. ce the processing element in the tap T2 of the first case delays an inputted symbol by two symbols and each processing element in the cap T3 which contains two processing elements wherein and is selected in the second case delays ar. inputted symbol by one symbol. That is, in the first case, a symbol fed to the selected pth tap T is delayed by (p-l) *64'2 symbols, ? being 1, 2, 3, ., 64. On the other hand, in the second case, a symbol coupled to the selected qth tap Tq is delayed by (q-l) *64*1 symbols, q being 1, 3, 5, 127 The above tap selection rule can be appl-ed to other modes such as (32, 4), 123*k interleaving symbols inserted therebetween. Therefore asik increases, two successive R-S symbols are separated from each other by a larger number of interleaving symbols and the end-to-end delay, i.e., 127*128*K symbols, also becomes longer.

The R-S code symbols sequentially interleaved through one of the 3 interleaving g modes at the inteleaveer 100 are transferred to a next circuit as interieaved data.

As can be seen from the description above, the 13 interleaving modes for interleaving R-S code symbols provided from an R-S encoder can be adaptively performed through the use of the interleaver in accordance with the present invention which has x number of taps vertically aligned and a yth tap has (y-1) number of processing elements connected in series, x being a positive integer and y ranging from 1 to x.

Referring to Fig. 4, there is provided a deinterleaver 200 in accordance with the present invention. The deinterleaver 200 comprises an input commutator 210, a storage block 250 and an output commutator 220 which are commonly controlled by the control signal transferred from a transmitter.

Int he deinterleaver 200, taps within the storage block 250 are aligned in reverse order compare with those in the storage block 150 in Fig. 3. That is, the top-mot cap Pg has ar.-dentical number o-processing elements to the bottom- most tap T128 of the storage block 150 and the bctton-most tap P1 is identical to the top-most tap T1, wherein the structure or a processing element : is identical to that used in the interleaver 100 as shown in Fig. 5.

Therefore,inordertodeinterleavet:heinterleaveddata transferred from the transmitter, the deinterleaver 200 performs an inverse operation in comparison with the operation of the interleaver 100. The input and output commutators 210 and 220 must be synchronized as illustrated in connection with Fig. 3 and iteratively switch to the taps in the storage block 250 from upper taps to lower taps, e. g., from ? 128 to P.

In the deinterleaving processes corresponding to the above 13 modes, the tap selection by the input and output commutators 210 and 220 and the output selection of the multiplexer 300 in each processing element are carried out in the same manner in the interleaver 100 except the tap selection is started from the bottom-most tap P1. That is, for example, for the case of (64, 2) mode, the commutators 210 and 220 select a first set of taps P64 ..., P3, P2, P or a second set of taps P127,...,-P5, P3, P1 as described in conr. ection with Fig. 3. Since the remaining modes follow the same manner used in the interleaver 100, the tap selections for the remaining modes are not illustrated for the purpose of the simplicity of the explanation.

Accordingly, through the use of the deinterleaver 200 set to adaptively respond to the control signal, the interleaved data is deinterleaved and then provided to a next circuit as deinterleaved data.

As illustrated above, the 13 m odes for interleaving and deinterleaving a sequence of symbols can be adaptively performed through the use of the interleaver and deinterleaver in accordance with the present invention. As a result, the amount of memoris used to construct the interleaver and deinterleaver can be considerably reduced compared with the case when the 13 modes employ their respective inierleavers and deinterleavers.

While the present invention has been described with respect to the particular embodiments, it will be apparent to those skilled in the an that various changes and modifications may be made without departing from the sccpe of the invention as defined in the following claims.

Claims (11)

1. Claims : 1. An apparatus for adaptively interleaving a sequence of symbols in response to a control werd corresponding to ar. y one of (I, J) interleaving modes, wherein I represents the number of taps and J depicts a symbol storage differer. between two successive taps, which comprises : storage means for providing ? number of taps, P being larger than or equal to I, to interleave the sequence of symbols, wherein an ith tap contains (i-1) number of processing elements, i ranging from 1 to P, and each processing element stores T symbols and outputs each stored symbol after a Q symbol delay, T being a positive integer smaller than P and Q being a positive integer smaller than or equal to T ; input commutating means for sequentially and iteratively switching to I number of taps selected from the P number of taps to provide each symbol in the sequence to a first processing element of a currently switched tap ; and output commutating means for sequentially and iteratively switching to the I number of taps to read out a symbol stored at a last processing element of the currently switched tap, wherein the operations of the storage means and the input and output commutating means are commonly controlled by the control word and Q is changed in response to the control word.
2. 2. The apparatus according to claim 1, wherein the processing element includes : T number of storage units connected in series, each selecting means for orin a Q one symbol, and amongtheoutputsfromtheTnumberofstorageunitsin response to the control word.
3. 3. The apparatus according to claim 2, wherein said I number of taps are selected from the P number of taps to satisfya condition that each successive tap provide a storage bigger by said J number of more symbols than a preceding one.
4. 4. The apparatus according to claim 3, wherein the storage unit employs a register performing a serial input and a parallel output.
5. 5. The apparatus accordirg to claim 5, wherein T is 8.
6. 6. An apparatus for adaptively deinterleaving interleaved data contain-ng a sequence of symbols in response to a control word corresponding to any one of (, J) interleaving modes, wherein I represents the number of taps and J depiccs a symbol storage difference becween two successive taps, which comprises : storage means for providinc P number of taps, P being marger than or equal to I, to deir-terleave the sequence of symbols, wherein an ith tap contains (i-l) number of processing elements, i ranging from 1 to ?, and each processing element stores T symbols and outputs each storesd symbol after a Q symbol delay, T being a positive integer smal~er ller than P and Q being a positive integer smaller than or equal to T ; input commutating means for sequentially and iteratively switching to I number of taps selected from the ? number of taps to provide each symbol in the sequence to a first processing element of a currently switched tap ; and output commutating means for sequentially and iteratively switching to the I number of taps to read out a symbol stored at a last processing element of the currently switched tap, wherein the operations of the s. orage means and the input and output commutating means are commonly controlled by the control word and Q is changed in response to the control word.
7. 7. The apparatus as recited in claim 6, wherein the processing element includes : T number of storage units connected in series, each storage unit storing one symbol ; and selecting means for choosing a Q symbol delayed output among the outputs from the T number of storage units in response to the control word.
8. 8. The apparatus as recited in claim 7, wherein said I number of taps are chosen from the P number of taps to satisfy a condition that each successive tap provide a storage bigger by said J number of more symbols than a preceding one.
9. 9. The apparatus as recited in claim 8, wherein t s-orage unit employas a register performing a serial input and a parallel output.
10. 10. The apparatus as recited in claim 9, wherein T is 8.
11. 11. An apparatus constructed and arrange substantially as herein described with reference to or as shown in Figures 3 to 5 of the accompanying drawings.