KR19990021592A - Method for forming contact hole in semiconductor device - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

Semiconductor device manufacturing method.

2. Technical problem to be solved by the invention

In the manufacture of a semiconductor device that maintains the electrical connection of the device through the contact hole, a semiconductor device capable of preventing leakage current due to etching of the field oxide film formed during the etching process for forming the contact hole, loss of the junction region, etc. It is an object of the present invention to provide a method for forming a contact hole.

3. Summary of the Solution of the Invention

Forming a conductive film pattern on the semiconductor substrate and the device isolation film; Forming a first insulating layer on an upper portion of the device isolation layer and the sidewalls of the conductive layer pattern where the first step is completed; A third step of forming an interlayer insulating film on the resultant product of which the second step is completed; And etching the interlayer insulating layer between the device isolation layer and the conductive pattern pattern gap adjacent thereto.

4. Important uses of the invention

Used in metallization process in semiconductor device manufacturing process.

Description

Method for forming contact hole in semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, such as a DRAM (Dynamic Random Access Memory), and more particularly, to a method for forming a contact hole in a semiconductor device.

In general, the conductive film has a function of electrical communication or interconnection of the elements. Therefore, the contact hole forming process, which is the basis of the conductive film formation, is a critical process that has the greatest influence on the yield and reliability of the integrated circuit.

Therefore, aluminum (Al) has excellent adhesion to silicon (Si) and silicon oxide film (SiO ₂ ) and exhibits ohmic resistance upon contact with highly doped diffusion layers (N ⁺ , P ⁺ ), thereby providing semiconductor devices. It is most widely used as a buried material of metal contacts for metallization in manufacturing processes. In recent years, as integrated devices become more integrated, the size of contact holes for electrical connection between devices becomes smaller. Accordingly, aluminum having poor step coverage is not completely embedded in the contact hole having a large aspect ratio, resulting in a landfill failure.

In order to improve the problem that such a conductive material causes a poor filling in the contact hole, there is, for example, a method of forming a sidewall oxide spacer (SOSCON), which is an improved method of forming a contact hole.

In a typical source cone process, a contact hole is formed by dry etching an interlayer insulating film on a silicon substrate. An oxide layer spacer is formed on the sidewalls of the pre-formed contact holes so as to improve the embedding properties of the conductive material such as aluminum embedded in the contact holes. However, such a source cone process reduces the contact hole by the thickness of the oxide spacer formed on the contact hole sidewalls, and the contact hole having a reduced size shows a large contact resistance.

As a further improved contact hole formation method, a self-aligned contact hole formation method (SAC) using an insulating film as an etch barrier is used, which is not significantly affected by misalignment of the mask and is always fixed at a constant position. A contact hole of size can be obtained.

1A to 1D are cross-sectional views illustrating a method of forming a contact hole according to the prior art.

First, as shown in FIG. 1A, a field oxide film 12 is formed on a silicon substrate 11 to designate an element formation region. A gate oxide film and a polysilicon film 13 are sequentially formed on the entire structure, and an etch mask pattern 101 is formed using an exposure mask for a gate electrode.

Next, as shown in FIG. 1B, the polysilicon layer 13 and the gate oxide layer are etched using the previously formed etching mask pattern 101 as an etch barrier to expose the silicon substrate 11. To form. The oxide film spacer 14 is formed on the side surface of the gate electrode 13 pattern. Then, a junction region is formed on the silicon substrate 11. An oxide film spacer for forming a MOS transistor of an LDD structure is formed on the sidewall of the gate electrode. An interlayer insulating film 15 for planarization is formed thereon. An etching mask pattern 102 for forming a bit line is formed thereon.

Next, as shown in FIG. 1C, the interlayer insulating layer 15 is etched using the etch mask pattern 102 as an etch barrier to expose the junction region, and a conductive layer is formed to form the bit line 16. An interlayer insulating film 17 for insulating and planarizing the device is formed thereon, and an etch mask pattern 103 for forming a charge storage electrode of the capacitor is formed thereon.

Next, as shown in FIG. 1D, the interlayer insulating layers 15 and 17 are etched using the etch mask pattern 103 to expose the junction region. In some cases, the field oxide layer 12 may be exposed while being etched.

Accordingly, it is necessary to develop a method for forming a contact hole in a semiconductor device capable of securing a process margin when forming a contact hole in a semiconductor device.

The present invention has been made to solve the above problems, in the manufacture of a semiconductor device that maintains the electrical connection of the device through the contact hole, the etching of the field oxide film formed during the etching process for forming the contact hole, and the junction region SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a contact hole in a semiconductor device capable of preventing a leakage current due to a loss of the semiconductor device.

1A to 1D are cross-sectional views illustrating a method for forming a contact hole according to the prior art.

2A to 2D are cross-sectional views illustrating a method of forming a contact hole according to an embodiment of the present invention.

3A to 3E are cross-sectional views illustrating a method of forming a contact hole according to another exemplary embodiment of the present invention.

Explanation of symbols for the main parts of the drawings

21 silicon substrate 26 interlayer insulating film

22: local oxide film 27: bit line

23 polysilicon film for word line 28 interlayer insulating film

24: first nitride film

25: second nitride film

In order to achieve the above object, a method of forming a contact hole in a semiconductor device of the present invention includes: a first step of forming a conductive film pattern on a semiconductor substrate and an isolation layer; Forming a first insulating layer on an upper portion of the device isolation layer and the sidewalls of the conductive layer pattern where the first step is completed; A third step of forming an interlayer insulating film on the resultant product of which the second step is completed; And etching the interlayer insulating layer between the device isolation layer and the conductive pattern pattern gap adjacent thereto.

In addition, a method of forming a contact hole in a semiconductor device according to another embodiment of the present invention may include forming an etch stop layer on an isolation layer on a semiconductor substrate; Forming a conductive layer pattern having insulating layer spacers on side surfaces of the entire structure including the isolation layer on which the etch stop layer is formed; Forming an interlayer insulating film on the resultant product on which the conductive film pattern is formed; And etching the interlayer insulating layer between the device isolation layer and the conductive pattern pattern gap adjacent thereto.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2A through 2D are cross-sectional views illustrating a method of forming a contact hole according to an exemplary embodiment of the present invention.

First, as shown in FIG. 2A, a local oxide film 22 is formed on the silicon substrate 21 to designate an element formation region. A gate oxide film, a word silicon polysilicon film 23, and a first nitride film 24 are sequentially formed on the entire structure, and an etch mask pattern 201 for forming a gate electrode is formed.

Next, as shown in FIG. 2B, the first nitride film 24, the polysilicon film 23, and the gate oxide film are partially etched using the previously formed etching mask pattern 201 as an etch barrier. And a gate electrode 23 pattern exposing the silicon substrate 21. After the second nitride film 25 is stacked on the entire structure, an etch mask pattern 202 is formed on the upper part of the structure, and the etch mask pattern 202 is used to form a pre-formed field oxide film 22. It forms using a mask (not shown), and forms it in the shape which covers the field oxide film 22 upper part. Accordingly, anisotropic etching is performed using the previously formed etching mask pattern 202 to form a second nitride layer 25 spacer on the side of the gate electrode pattern formed on the element formation region.

The junction region is then formed by ion implantation into the exposed silicon substrate 21 in the element formation region.

Next, as shown in FIG. 2C, the residual etching mask pattern 202 is removed, and an interlayer insulating film 26 is formed on the entire structure. The interlayer insulating layer 26 is etched using the bit line forming etching mask to form a bit line contact hole exposing the junction region formed on the silicon substrate 21.

Next, as shown in FIG. 2D, the polysilicon layer 27 is embedded in the bit line contact hole to form the bit line 27, and the interlayer insulating layer 28 is formed to maintain the planarization process and device insulation. do. An etching process for forming a contact hole for the charge storage electrode is performed to expose the junction region formed on the silicon substrate 21.

3A to 3E are cross-sectional views illustrating a method of forming a contact hole according to another exemplary embodiment of the present invention.

First, as shown in FIG. 3A, a field oxide film 32 is formed on the silicon substrate 31 to designate an element formation region. After the first oxide film 22 and the first nitride film 34 are sequentially formed on the entire structure, the field oxide film 32 is formed by using an exposure mask (not shown) used to form the previously formed field oxide film 32. An etching mask pattern 301 having a shape covering the upper portion is formed.

Next, as illustrated in FIG. 3B, the silicon nitride layer 31 is exposed by removing the first nitride layer 34 and the first oxide layer 33 of the element formation region using the previously formed etching mask pattern 301 as an etch barrier. Let's do it. After the gate oxide layer and the word silicon polysilicon layer 34 are formed on the entire structure, an etch mask pattern 301 for forming the gate electrode is formed.

Next, as illustrated in FIG. 3C, the polysilicon layer 35 and the gate oxide layer are etched using the previously formed etching mask pattern 302 as an etch barrier to partially etch the first nitride layer 34 and the silicon substrate 31. A gate electrode 35 pattern is formed to expose the gate electrode 35. After the second oxide layer 36 is stacked on the entire structure, anisotropic etching is performed to form the second oxide layer 36 spacers on the side surfaces of the gate electrode patterns 35 and the pattern sides forming the vertical structures. . The junction region is then formed by ion implantation into the exposed silicon substrate 21 in the element formation region.

Since the nitride film 34 formed on the field oxide film 32 exhibits a large etching selectivity with the polysilicon film 35, the nitride film 34 is sufficient to be used as an etch stop film, and the field oxide film 32 during such an etching process. It is enough to prevent the etching.

Next, as shown in Fig. 3D, an interlayer insulating film 37 is formed over the entire structure. The interlayer insulating layer 37 is etched using a bit line forming etching mask to form a bit line contact hole exposing a junction region formed on the silicon substrate 31. In some cases, side spacers may be formed to improve buried characteristics of materials embedded in the bit line contact holes. The polysilicon layer 38 is embedded in the bit line contact hole to form the bit line 38.

Finally, as shown in Fig. 3E, an interlayer insulating film 39 is formed over the entire structure to maintain the planarization process and insulation of the device. Then, an etching process for forming a contact hole for the charge storage electrode is performed to expose the junction region formed on the silicon substrate 31. The conductive film is embedded in the contact hole for the charge storage electrode formed therein to form the charge storage electrode of the capacitor.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and various substitutions, modifications, and changes are possible within the scope of the present invention without departing from the technical idea. It will be evident to those who have knowledge of.

In the present invention as described above, the formation of the semiconductor device to maintain the electrical connection by using a contact hole, forming an etch stop layer on the field oxide layer, for example, during the etching process proceeds on the field oxide layer, for example, the charge storage of the capacitor When forming a contact hole for an electrode or the like, the field oxide film is prevented from being etched to prevent leakage current of the device, thereby increasing the yield of the device.

Claims (5)

Forming a conductive film pattern on the semiconductor substrate and the device isolation film; Forming a first insulating layer on an upper portion of the device isolation layer and the sidewalls of the conductive layer pattern where the first step is completed; A third step of forming an interlayer insulating film on the resultant product of which the second step is completed; And Etching the interlayer dielectric layer between the device isolation layer and the conductive layer pattern gap adjacent thereto; A contact hole forming method of a semiconductor device comprising a. The method of claim 1, The second step is A fifth step of forming the first insulating layer on the entire structure where the first step is completed; A sixth step of forming an etch mask pattern completely covering the device isolation layer; A seventh step of anisotropically etching and removing the exposed first insulating layer after the sixth step; And And forming an eighth step of removing the etch mask pattern. The method of claim 2, The conductive film pattern is A method for forming a contact hole in a semiconductor device comprising at least a polysilicon film and a second insulating film. Forming an etch stop layer on the device isolation layer on the semiconductor substrate; Forming a conductive layer pattern having insulating layer spacers on side surfaces of the entire structure including the isolation layer on which the etch stop layer is formed; Forming an interlayer insulating film on the resultant product on which the conductive film pattern is formed; Etching the interlayer dielectric layer between the device isolation layer and the conductive layer pattern gap adjacent thereto; A contact hole forming method of a semiconductor device comprising a. The method of claim 4, wherein The etch stop layer is Sequentially forming an oxide film and a nitride film on the semiconductor substrate including the device isolation film; Forming an etching mask on the device isolation layer; And Exposing the semiconductor substrate by sequentially etching the nitride layer and the oxide layer using the etching mask; A contact hole forming method of a semiconductor device comprising a.