KR100303438B1 - Device isolation method of semiconductor device - Google Patents

Abstract

PURPOSE: A method for isolating device is provided to minimize a stress due to bird's beak by forming a field oxide using an over-etch in forming sidewalls. CONSTITUTION: After sequentially depositing a pad oxide(22) and a nitride layer(23) on a substrate(21), the nitride layer(23) is patterned by a photo-etching and the exposed pad oxide(22) is then removed. At this time, cavities(24) are resulted from the pad oxide(22) removal step. A thin oxide(25) is formed on the entire exposed area of the substrate(21). Then, a poly-crystalline silicon layer(26) is deposited on the entire surface of the resultant structure. Poly-crystalline silicon sidewalls(27) are formed on both sidewalls of the nitride layer(23) by etching the poly-crystalline silicon layer(26). The cavities(24) are filled with the poly-crystalline silicon layer(26). The poly-crystalline silicon sidewalls(27) have a less thickness than the nitride layer(23) using an over-etch. At this time, a stress due to bird's beak is minimized.

Description

Device Separation Method of Semiconductor Device

1 (a) to 1 (g) are cross-sectional views of a process procedure showing a device isolation method of a semiconductor device according to the prior art.

2 is a plan view showing a pattern of an active region and an inactive region of a semiconductor device.

3 (a) to 3 (h) are cross-sectional views of a process procedure showing a device separation method of a semiconductor device according to the present invention.

4 is a cross-sectional view taken with a scanning electron microscope (SEM) picture immediately after the device isolation process is completed, and FIG. 4 (a) is a cross-sectional view showing a device isolation profile according to the present invention;

Figure 4 (b) is a cross-sectional view showing the oxide film projections generated when the polycrystalline silicon sidewall is not over-etched in the present invention;

4 (c) is a cross-sectional view showing a profile when a polycrystalline is buried in a cavity formed in FIG. 3 (d) to grow a field oxide film.

5 is a plan view of a spring photograph showing the actual shape according to the second FIG. Pattern.

* Explanation of symbols for main parts of the drawings

21 silicon substrate 22 pad oxide film

23 nitride film 24 cavity

25 thin oxide film 26 polycrystalline silicon film

27 polycrystalline silicon sidewall 38 field oxide film

29: oxide film projection

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device isolation method of a semiconductor device, and more particularly, to form a sidewall without using a process of depositing and etching back a planarization film in order to planarize an oxide projecting portion generated during the device isolation process. The present invention relates to a method of isolating elements of a semiconductor device in which over-etching is performed in a timely manner to form a good field oxide film.

To date, various techniques have been developed for isolating devices in integrated circuits. One reason is that different IC types (eg NMOS, CMOS, and bipolar) require somewhat different isolation techniques. Moreover, various separation techniques show different aspects in terms of minimum width, surface planarization, process complexity, and the density of defects occurring during the processing of the isolation structure. Advantageous of these features can be used when selecting a separation technique for a particular circuit application. In particular, the most important technique developed in the MOS structure is LOCOS isolation (LOCal Oxidation of Silicon), which includes the formation of an oxide film that is half hollow in the inactive (or field) region of the substrate.

However, in such a LOCOS structure, a thin pad oxide film is formed on a silicon substrate, a nitride film is formed on the silicon substrate, the active region is patterned, and field oxidation is performed. At this time, since the oxide film hardly grows on the nitride film, a so-called Bird's beak phenomenon occurs in which the oxide film has a beak shape between the active region and the inactive region. The Buzz Big is stressed in later years as the process progresses, causing leakage currents and seriously affecting device reliability.

Various device isolation methods have been proposed to remedy these shortcomings, a representative of which is a "manufacturing method of device isolation" published in Japanese Patent Application Laid-open No. 1-282839. Figure 1 shows one embodiment of the manufacturing method is as follows. First, as shown in FIG. 1A, a thin oxide film 2 and a nitride film 3 are formed on the silicon substrate 1. The device isolation region 4 is then patterned through a photolithography process. (Fig. 1 (b)) Then, as shown in Figs. 1 (c) and (d), the polycrystalline silicon 5 is deposited and the polycrystalline silicon sidewall 6 is formed on the side of the nitride film 3 by the anisotropic etching method. Then, the silicon substrate 1 is thermally oxidized. (Field oxidation) Thermal oxidation is performed so that the polycrystalline silicon sidewall 6 is completely oxidized. Buzz big does not occur between the nitride film 3 and the substrate 1 as the polycrystalline silicon sidewalls are oxidized. At this time, as the polycrystalline silicon sidewall 6 is oxidized in the oxide film 7, protrusions 9 are formed. (FIG. 1 (e)) Next, in FIG. 1 (f) and (g), the protrusions generated in the process are shown. The planarized oxide film 10 is formed by depositing and etching back the planarization film 8 to the entire surface of the wafer for removal.

However, the prior art as described above has some problems in the performance of the process, which is difficult to apply to the production of the actual product.

First, the growth of the buzz big depends on the thickness of the pad oxide layer under the masking layer, which prior art controls the buzz big only by the polycrystalline silicon sidewalls. That is, since the pad oxide film having a limit in thickness downward is used as it is, there is a limitation in the buzz big control, and the length of the buzz big is not constant because the thickness of the pad oxide film under the side wall is not uniform.

Second, in order to remove the protruding oxide projections, the planarization film is deposited on the entire surface of the wafer and etched back. In addition, there is no uniformity of the etch back process itself, and the etching rate of the planarization film and the thermal oxide film is the same so as to etch it flat. This is difficult to apply to product production because it is practically difficult and there is no process margin.

Finally, when the level of the final field oxide profile after the planarization is severe, all of the gate polysilicon remains unetched when the subsequent gate is formed, which is a main cause of a single bit failure.

SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art as described above, and an object of the present invention is to over-etch an oxide film under a nitride film sidewall when defining an active region to form a good field oxide film, thereby reducing stress caused by buzz big. An object isolation method of a semiconductor device can be minimized. Another object of the present invention is to simplify the process by eliminating the complicated process of depositing a separate planarization film and performing an etch back process to planarize the protrusions caused by sidewall oxidation. It is to provide a device isolation method.

In order to achieve the object described above, the present invention is a device of a semiconductor device in which a pad oxide film and a nitride film are sequentially stacked on a silicon substrate, followed by a photolithography process, patterning the nitride film and performing selective oxidation to form device isolation regions. A separation method, comprising: forming a cavity under the nitride film, growing a thin oxide film, stacking a polycrystalline silicon film, and forming a polycrystalline silicon sidewall surrounding the nitride film side by anisotropic etching to selectively oxidize the silicon substrate. An element isolation method of a semiconductor device is provided.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 shows the active region 11 and the inactive region 12 of the semiconductor device. The active region 11 is disposed under the nitride film pattern, and the inactive region 12 forms a field oxide film to separate the devices from each other.

FIG. 3 is a cross-sectional view taken along line X-X 'of FIG. 2, which shows a device isolation method of a semiconductor device according to the present invention. As shown in FIG. 3A, a thin pad oxide film 22 is grown on the silicon substrate 21, and a nitride film of about 1000 to 2000 microseconds is deposited thereon. Next, the active region and the inactive region are defined by the photo-etching process as shown in FIG. 3 (b). Now, as shown in FIG. 3 (c), the pad oxide layer of the inactive region is removed by a wet etch. In this case, a certain amount of the pad oxide layer under the active region is also etched due to the property of isotropic etching, thereby forming a cavity (24) along the active region. ) Subsequently, as shown in FIG. 3 (d), an oxide film 25 thinner than the pad oxide film is grown. The thin oxide film 25 is formed to have a uniform thickness over the entire inactive region, and the thickness is freely controlled and the buzz big control is very high. It becomes easy.

In general, the pad oxide film under the nitride film has a fundamental limitation in decreasing its thickness because it causes dislocations in the lower silicon when the thickness is less than or equal to the thickness of the nitride film. have. Therefore, in the present invention, a cavity is formed in such a way as to overcome this limitation, and then a thin oxide film is grown and a polycrystalline silicon sidewall free of stress influence as a masking layer is formed thereon.

Then, the polycrystalline silicon film 26 is laminated as shown in FIG. 3 (e). The polycrystalline silicon sidewall 27 is formed on the sidewall of the nitride film by anisotropic etching. At this time, the selectivity between the oxide film and the polycrystalline silicon is very good (usually poly Si: oxide = 20: 1), and the sidewalls are formed well and there is no erosion effect on the lower silicon. In the present invention, the deposition of polycrystalline silicon of about 500 ~ 1500Å and to form a sidewall by anisotropic etching, the sidewall is formed lower than the thickness of the nitride film by etching over 20 ~ 30% after etching the deposited thickness. If an appropriate amount of over-etching is not performed, the oxidized protrusions on the sidewall of the polycrystalline silicon are not etched as shown in FIG. 4 (b), and subsequent processes cannot be performed, and the excessive etching is performed to remove the protrusions. The oxide film becomes thin and a step is generated in the field edge, which causes the device to degrade the electrical characteristics. In the present invention, a planar oxide film can be formed by appropriately over-etching the polysilicon sidewalls without the complicated process of depositing a separate planarization film to etch back to planarize the protrusions.

In addition, the formed polycrystalline silicon sidewall fills the cavity formed in FIG. 3 (d), and the embedded polycrystalline silicon is not oxidized during field oxide film growth and remains as shown in FIG. 4 (c). This phenomenon can be explained by poor oxidation in the convex and concave portions of the polycrystalline silicon. This isolated polycrystalline silicon, along with the regrown thin oxide film, acts as a key element in controlling Buzz Big.

When the field oxide film 28 is grown in the following process, the third (f) also has a shape similar to that of the third (g). During the oxidation of the polycrystalline silicon, the oxidation to the substrate level or less decreases the stress, thereby reducing the leakage current of the device. In addition, the projections 29 of the oxide film formed on the nitride film sidewalls are also significantly lower than those of the prior art, thereby overcoming the difficulty of the step difference.

Thereafter, the cap oxide film, the nitride film, and the pad oxide film are sequentially removed to obtain a final oxide film profile as shown in FIG. 3 (h). In fact, the device isolation profile implemented by the above process procedure is well illustrated in FIGS. 4 (a) and 5. As shown in the figure, it shows a good vertical structure having no problem in the subsequent gate process, and it is very easy to adjust the buzz big to realize a cell structure in which the active region and the inactive region are well defined.

The device isolation method of the present invention can minimize the stress caused by the buzz big to improve the reliability, such as the electrical characteristics of the device, and the advantages can be expected to reduce the cost and improve the throughput by simplifying the process .

Claims (5)

In the device isolation method of the semiconductor device in which the pad oxide film 22 and the nitride film 23 are sequentially stacked on the silicon substrate 21, the nitride film is patterned through a photolithography process and subjected to selective oxidation to form an isolation region. In addition, the pad oxide layer 22 exposed by patterning the nitride layer 23 is removed to form a cavity 24 under the nitride layer 23, a thin oxide layer 25 is grown, and then the polycrystalline silicon layer 26 is formed. And stacking and forming a polycrystalline silicon sidewall (27) surrounding the nitride film (23) side by anisotropic etching to selectively oxidize the silicon substrate. 2. The method of claim 1 wherein a polycrystalline silicon film (26) fills the cavity (24). The method of claim 1, wherein when forming the polycrystalline silicon sidewall (27), an overetch is formed to be lower than the thickness of the nitride film (23). 2. The device isolation method according to claim 1, wherein polycrystalline silicon is used as a buffer between the thin oxide film and the nitride film. 2. The method of claim 1 wherein isotropic etching is performed to remove the pad oxide layer (22).