KR102684707B1 - Semiconductor package - Google Patents

Abstract

The technical idea of the present invention is to include a package substrate including a conductive layer; a semiconductor chip on the package substrate; a sealing layer provided on the package substrate to cover the semiconductor chip and including a first through hole; a vertically connected conductor including a portion buried in a first through hole of the sealing layer and a portion protruding from an upper surface of the sealing layer, and electrically connected to the conductive layer of the package substrate; A conductor extending along a sidewall of the sealing layer defining a first through hole of the sealing layer and disposed between the vertical connection conductor and the sealing layer and between the vertical connection conductor and the conductive layer of the package substrate. connection pattern; a cover insulating layer provided on the sealing layer and in contact with the vertical connection conductor; and a redistribution structure provided on the cover insulating layer and including a conductive wiring structure electrically connected to the vertical connection conductor.

Description

Semiconductor package {SEMICONDUCTOR PACKAGE}

The technical idea of the present invention relates to a semiconductor package.

In accordance with the rapid development of the electronics industry and user demands, electronic devices are becoming increasingly smaller and lighter. Accordingly, semiconductor packages are required to have high-density input/output terminals while being small in size. Recently, research and development on a semiconductor package with a fan-out structure that forms input/output terminals outside the area where the semiconductor chip is placed and connects the input/output terminal to the semiconductor chip through rewiring has been continuously conducted.

The problem to be solved by the technical idea of the present invention is to provide a semiconductor package and a manufacturing method thereof.

In order to solve the above-described problem, the technical idea of the present invention is to include a package substrate including a conductive layer; a semiconductor chip on the package substrate; a sealing layer provided on the package substrate to cover the semiconductor chip and including a first through hole and a second through hole; a vertically connected conductor including a portion buried in a first through hole of the sealing layer and a portion protruding from an upper surface of the sealing layer, and electrically connected to the conductive layer of the package substrate; a first portion extending along a sidewall of the sealing layer defining the first through hole of the sealing layer, a second portion connected to a chip pad of the semiconductor chip through the second through hole of the sealing layer, and a third portion extending along the upper surface of the sealing layer, wherein the first portion is disposed between the vertical connecting conductor and the sealing layer and between the vertical connecting conductor and the conductive layer of the package substrate, conductive connection pattern; a cover insulating layer provided on the sealing layer and in contact with the vertical connection conductor; and a redistribution structure provided on the cover insulating layer and including a conductive wiring structure electrically connected to the vertical connection conductor.

In exemplary embodiments, the vertical connection conductor includes a recess, and further includes a buried insulating layer provided within the recess of the vertical connection conductor and in contact with the conductive wiring structure of the redistribution structure, The buried insulating layer and the cover insulating layer are characterized in that they contain the same material.

In example embodiments, the surface of the cover insulating layer in contact with the redistribution structure, the surface of the vertical connection conductor in contact with the redistribution structure, and the surface of the buried insulating layer in contact with the redistribution structure. are characterized in that they are on the same plane.

In exemplary embodiments, the upper surface of the vertical connection conductor is characterized as an overall flat plane.

In order to solve the above-described problem, the technical idea of the present invention is to include a package substrate including a conductive layer; a semiconductor chip on the package substrate; a via frame provided on the package substrate and including a frame body having a cavity in which the semiconductor chip is accommodated, and a vertical connection conductor penetrating the frame body; a sealing layer filling the cavity of the frame body; a redistribution structure provided on the sealing layer and including a conductive wiring structure electrically connected to the vertical connection conductor and a chip pad of the semiconductor chip; and a conductive connection pillar disposed on the chip pad of the semiconductor chip and configured to electrically connect the chip pad of the semiconductor chip and the conductive wiring structure of the redistribution structure, wherein the vertical connection conductor is a lower portion whose horizontal width gradually increases in a direction away from the package substrate; and an upper portion whose horizontal width gradually increases in a direction away from the package substrate, wherein the upper surface of the conductive connection pillar, the upper surface of the sealing layer, and the upper surface of the via frame are on the same plane. .

In order to solve the above-described problem, the technical idea of the present invention is to include a package substrate including a conductive layer; a semiconductor chip on the package substrate; a conductive connection pillar disposed on a chip pad of the semiconductor chip; a sealing layer provided on the package substrate to cover the semiconductor chip; a vertically connected conductor passing through the sealing layer and connected to a conductive layer of the package substrate; a redistribution structure provided on the sealing layer and including a conductive wiring structure electrically connected to the vertical connection conductor and the conductive connection pillar; and a conductive adhesive layer provided between the vertical connection conductor and the conductive layer of the package substrate, wherein the top surface of the sealing layer, the top surface of the vertical connection conductor, and the top surface of the conductive connection pillar are on the same plane. Provides semiconductor packages.

In order to solve the above-described problem, the technical idea of the present invention includes the steps of mounting a semiconductor chip on a package substrate including a conductive layer; A sealing layer covering the semiconductor chip and the package substrate and including a first through hole exposing at least a portion of the conductive layer of the package substrate and a second through hole exposing at least a portion of a chip pad of the semiconductor chip. forming step; a first portion extending along a sidewall of the sealing layer defining the first through hole of the sealing layer, a second portion connected to a chip pad of the semiconductor chip through the second through hole of the sealing layer, and forming a conductive connection pattern including a third portion extending along the upper surface of the sealing layer; It includes a portion buried in a first through hole of the sealing layer and a portion protruding from an upper surface of the sealing layer, and is electrically connected to the conductive layer of the package substrate and the chip pad of the semiconductor chip through the conductive connection pattern. forming a vertically connected conductor; forming a cover insulating layer on the sealing layer, covering the sealing layer and contacting the vertical connection conductor; and forming, on the cover insulating layer, a redistribution structure including a conductive wiring structure electrically connected to the vertical connection conductor.

In example embodiments, forming the cover insulating layer may include forming a preliminary insulating layer covering the sealing layer and the vertical connection conductor; and a polishing step of removing a portion of the preliminary insulating layer so that the vertical connection conductor is exposed, wherein the preliminary insulating layer remaining after the polishing step fills the concave portion of the cover insulating layer and the vertical connection conductor. It is characterized by forming a buried insulating layer.

In exemplary embodiments, the surface of the cover insulating layer, the surface of the vertical connection conductor, and the surface of the buried insulating layer are on the same plane.

1 is a cross-sectional view showing a semiconductor package according to exemplary embodiments of the present invention.
FIGS. 2A to 2G are cross-sectional views showing a method of manufacturing the semiconductor package of FIG. 1.
3A to 3C are cross-sectional views showing a method of manufacturing a semiconductor package according to exemplary embodiments of the present invention.
FIGS. 4A to 4E are cross-sectional views showing a method of manufacturing the via frame shown in FIG. 2A.
5 is a cross-sectional view showing a semiconductor package according to exemplary embodiments of the present invention.
FIGS. 6A to 6G are cross-sectional views showing a method of manufacturing the semiconductor package of FIG. 5.
7A to 7C are cross-sectional views showing a method of manufacturing a semiconductor package according to exemplary embodiments of the present invention.
8 is a cross-sectional view showing a semiconductor package according to exemplary embodiments of the present invention.
FIG. 9 is an enlarged view showing an enlarged area marked “AA” in FIG. 8.
FIGS. 10A to 10H are cross-sectional views showing a method of manufacturing the semiconductor package of FIG. 8.
11A and 11B are cross-sectional views showing a method of manufacturing a semiconductor package according to exemplary embodiments of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the embodiments of the present invention concept may be modified into various other forms, and the scope of the present invention concept should not be construed as being limited to the embodiments described in detail below. It is preferable that the embodiments of the present invention be interpreted as being provided in order to more completely explain the present invention to a person with average knowledge in the art. Identical symbols refer to identical elements throughout. Furthermore, various elements and areas in the drawings are schematically drawn. Accordingly, the inventive concept is not limited by the relative sizes or spacing depicted in the accompanying drawings.

Terms such as first, second, etc. may be used to describe various components, but the components are not limited by the terms. The above terms are used only for the purpose of distinguishing one component from another. For example, a first component may be named a second component, and conversely, a second component may be named a first component without departing from the scope of the present invention concept.

The terms used in this application are only used to describe specific embodiments and are not intended to limit the inventive concept. Singular expressions include plural expressions unless the context clearly dictates otherwise. In this application, expressions such as “comprises” or “has” are intended to indicate the presence of features, numbers, steps, operations, components, parts, or combinations thereof described in the specification, but are not intended to indicate the presence of one or more other features or It should be understood that this does not preclude the presence or addition of numbers, operations, components, parts, or combinations thereof.

Unless otherwise defined, all terms used herein, including technical terms and scientific terms, have the same meaning as commonly understood by those skilled in the art in the technical field to which the concept of the present invention pertains. Additionally, commonly used terms, as defined in dictionaries, should be interpreted to have meanings consistent with what they mean in the context of the relevant technology, and should not be used in an overly formal sense unless explicitly defined herein. It will be understood that this is not to be interpreted.

1 is a cross-sectional view showing a semiconductor package 100 according to exemplary embodiments of the present invention.

Referring to FIG. 1 , the semiconductor package 100 may include a package substrate 110, a semiconductor chip 120, a via frame 130, a sealing layer 151, and a redistribution structure 140. The semiconductor package 100 may be, for example, a semiconductor package with a fan-out structure.

The package substrate 110 may be a mounting substrate on which the semiconductor chip 120 is mounted. The package board 110 is one of a redistribution board, a printed circuit board (PCB), a metal core PCB (MCPCB), a metal PCB (MPCB), and a flexible PCB (FPCB) formed through a redistribution process. It may apply to either one. Hereinafter, the package substrate 110 is described as a redistribution substrate.

In example embodiments, the package substrate 110 may include a plurality of first wire insulating layers 111 and a first conductive wire structure 113.

The plurality of first wire insulating layers 111 may be stacked on each other in a vertical direction (eg, Z direction). For example, the plurality of first wire insulating layers 111 may be formed of insulating polymer, epoxy, or a combination thereof.

The first conductive wiring structure 113 includes first conductive layers 1131 extending along one of the upper and lower surfaces of each of the plurality of first wiring insulating layers 111, and a plurality of first wiring insulating layers 113. It may include first conductive via patterns 1133 extending in a vertical direction (eg, Z direction) through at least one layer among the layers 111 . The first conductive layers 1131 may be disposed at different vertical levels to form a multi-layer structure. The first conductive layers 1131 may each include a line pattern extending in the form of a line on one of the upper and lower surfaces of each of the plurality of first wire insulating layers 111. The first conductive via patterns 1133 may electrically connect the first conductive layers 1131 disposed at different vertical levels. For example, first conductive layers 1131 are disposed on the lower surface of each of the plurality of first wiring insulating layers 111, and first conductive layers 1131 are disposed at different vertical levels. They may be electrically connected by via patterns 1133. The first conductive layer 1131 extending along the lower surface of the lowest first wire insulating layer 111 among the plurality of first wire insulating layers 111 is exposed to the outside and forms a pad for connection to external devices. can do.

The first conductive wiring structure 113 includes tungsten (W), copper (Cu), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), ruthenium (Ru), palladium (Pd), It may be made of platinum (Pt), cobalt (Co), nickel (Ni), or a combination thereof. The material of the second conductive wiring structure 143 of the redistribution structure 140, which will be described later, may be substantially the same as or similar to the material of the first conductive wiring structure 113.

The semiconductor chip 120 may be placed on the package substrate 110 . The semiconductor chip 120 may include upper and lower surfaces that are opposed to each other. A chip pad 121 may be provided on the upper surface of the semiconductor chip 120, and the lower surface of the semiconductor chip 120 may face the package substrate 110. The semiconductor chip 120 may be attached to the package substrate 110 by an adhesive film 153 provided between the lower surface of the semiconductor chip 120 and the package substrate 110 . The adhesive film 153 may include, for example, a die attach film.

In example embodiments, the semiconductor chip 120 may be a memory chip. The memory chip is, for example, a volatile memory chip such as Dynamic Random Access Memory (DRAM) or Static Random Access Memory (SRAM), or Phase-change Random Access Memory (PRAM), Magnetoresistive Random Access Memory (MRAM), or FeRAM ( It may be a non-volatile memory chip such as Ferroelectric Random Access Memory (RRAM) or Resistive Random Access Memory (RRAM).

In example embodiments, the semiconductor chip 120 may be a logic chip. For example, the semiconductor chip 120 may be a Central Processor Unit (CPU), Micro Processor Unit (MPU), Graphic Processor Unit (GPU), or Application Processor (AP).

In FIG. 1 , one semiconductor chip 120 is illustrated as being disposed on the package substrate 110 , but a plurality of semiconductor chips 120 may be disposed on the package substrate 110 . For example, a plurality of semiconductor chips 120 spaced apart in the horizontal direction may be disposed on the package substrate 110 . Two or more semiconductor chips 120 included in the semiconductor package 100 may be the same type of semiconductor chip or may be different types of semiconductor chips. In example embodiments, the semiconductor package 100 may be a system in package in which different types of semiconductor chips and various electronic components are electrically connected to each other and operate as one system.

The via frame 130 may be disposed on the package substrate 110 . The via frame 130 may be spaced apart from the sidewall of the semiconductor chip 120 so that a space is formed between the via frame 130 and the semiconductor chip 120. The via frame 130 may include a frame body 131 and a vertical connection conductor 133.

The frame body 131 may include an insulating material. For example, the frame body 131 may include ceramic, plastic, polymer, glass, etc. For example, the frame body 131 may include epoxy molding compound (EMC).

The vertical connection conductor 133 may penetrate the frame body 131. The lower surface of the vertically connected conductor 133 is connected to the first conductive wiring structure 113 of the package substrate 110, and the upper surface of the vertically connected conductor 133 is connected to the second conductive wiring structure of the redistribution structure 140. It can be connected to (143). The vertical connection conductor 133 may electrically connect the first conductive wiring structure 113 of the package substrate 110 and the second conductive wiring structure 143 of the redistribution structure 140. For example, the vertical connection conductor 133 includes copper (Cu), aluminum (Al), solder, tin (Sn), zinc (Zn), lead (Pb), silver (Ag), gold (Au), and palladium. (Pd) and/or doped polysilicon.

In example embodiments, the horizontal width of the vertical connection conductor 133 may be maximum at the middle portion between the bottom and top of the vertical connection conductor 133. For example, the lower part 1331 of the vertically connected conductor 133 has a horizontal width that gradually increases as it moves away from the package substrate 110, and the upper part 1333 of the vertically connected conductor 133 is closer to the package substrate 110. As the distance from (110) increases, the horizontal width gradually decreases, and at the boundary where the lower part 1331 of the vertically connected conductor 133 and the upper part 1333 of the vertically connected conductor 133 contact, the vertically connected conductor ( 133) may have the maximum horizontal width. In example embodiments, when viewed from a cross section of the semiconductor package 100, the cross section of the vertical connection conductor 133 may be hexagonal.

In example embodiments, the via frame 130 may include a cavity 135 that accommodates the semiconductor chip 120, and the via frame 130 may have a ring shape surrounding the semiconductor chip 120 in plan view. You can have The cavity 135 of the via frame 130 may be defined by the sidewall of the frame body 131 facing the sidewall of the semiconductor chip 120. The cavity 135 may penetrate the frame body 131 in a vertical direction (eg, Z direction).

The sealing layer 151 is disposed on the package substrate 110 and may contact the semiconductor chip 120 and the via frame 130. The sealing layer 151 is formed to fill the cavity 135 of the via frame 130 and can fill the gap between the sidewall of the semiconductor chip 120 and the via frame 130. Additionally, the sealing layer 151 may cover the sidewall and top surface of the semiconductor chip 120. In example embodiments, the top surface 1511 of the sealing layer 151 may be on the same plane as the top surface 130U of the via frame 130. In example embodiments, the sealing layer 151 may be formed of EMC. In other exemplary embodiments, the sealing layer 151 may include a photosensitive material such as polyimide (PI) or polybenzoxazole (PBO).

The redistribution structure 140 may be disposed on the via frame 130 and the sealing layer 151. The redistribution structure 140 may include a plurality of second wiring insulating layers 141 and a second conductive wiring structure 143.

A plurality of second wiring insulating layers 141 are provided on the upper surface 1511 of the sealing layer 151 and may be stacked on each other in a vertical direction (eg, Z direction). The plurality of second wiring insulating layers 141 may be formed of insulating polymer, epoxy, or a combination thereof.

The second conductive wiring structure 143 includes a second conductive layer 1431 extending along one of the upper and lower surfaces of each of the plurality of second wiring insulating layers 141, and a plurality of second wiring insulating layers ( 141) may include a second conductive via pattern 1433 extending in the vertical direction (eg, Z direction) through at least one layer. The second conductive layers 1431 may be disposed at different vertical levels to form a multi-layer structure. Each of the second conductive layers 1431 may include a line pattern extending in the form of a line on one of the upper and lower surfaces of each of the plurality of second wire insulating layers 141 . The second conductive via patterns 1433 may electrically connect the second conductive layers 1431 disposed at different vertical levels. For example, second conductive layers 1431 are disposed on the upper surface of each of the plurality of second wiring insulating layers 141, and second conductive layers 1431 are disposed at different vertical levels. They may be electrically connected by via patterns 1433. The second conductive layer 1431 extending along the upper surface of the uppermost second wire insulating layer 141 among the plurality of second wire insulating layers 141 may form a bump pad to which the connection bump 190 is attached. . For example, the connection bump 190 may be formed from a solder ball or solder bump.

The second conductive wiring structure 143 is electrically connected to the vertical connection conductor 133 of the via frame 130, and is electrically connected to the chip pad 121 of the semiconductor chip 120 through the conductive connection pillar 155. can be connected The second conductive wiring structure 143 is formed between the chip pad 121 of the semiconductor chip 120 and the vertical connection conductor 133 of the via frame 130, and between the chip pad 121 of the semiconductor chip 120 and the connection bump. It may be configured to electrically connect between 190 and between the vertical connection conductor 133 of the via frame 130 and the connection bump 190.

In example embodiments, a conductive connection pillar 155 may be disposed on the chip pad 121 of the semiconductor chip 120. The second conductive wiring structure 143 may be electrically connected to the chip pad 121 of the semiconductor chip 120 through the conductive connection pillar 155. The conductive connection pillar 155 may have a pillar shape extending in a vertical direction from the chip pad 121 of the semiconductor chip 120, and a side wall of the conductive connection pillar 155 may be covered with the sealing layer 151. In exemplary embodiments, the top surface of the conductive connection pillar 155 and the top surface 1511 of the seal layer 151 are planarized surfaces, and the top surface of the conductive connection pillar 155 and the top surface 1511 of the seal layer 151 are planarized surfaces. ) may be on the same plane. The conductive connection pillar 155 may include, for example, copper (Cu), aluminum (Al), solder, etc.

FIGS. 2A to 2G are cross-sectional views showing a method of manufacturing the semiconductor package 100 of FIG. 1 .

Referring to FIG. 2A, a via frame 130 including a frame body 131 and a vertical connection conductor 133 is prepared. The via frame 130 has a flat or panel shape and may include an upper surface 130U and a lower surface 130L that are opposed to each other.

Referring to FIG. 2B, the package substrate 110 is formed on the lower surface 130L of the via frame 130. For example, the package substrate 110 may be formed by performing a rewiring process on the lower surface 130L of the via frame 130. For example, in order to form the package substrate 110, an insulating layer forming step of forming a first wiring insulating layer 111 including a via hole on the lower surface 130L of the via frame 130, and the first wiring Repeating the metal wiring process several times to form the first conductive via pattern 1133 that fills the via hole of the insulating layer 111 and the first conductive layer 1131 extending along the lower surface of the first wiring insulating layer 111. can do.

Referring to FIG. 2C, a portion of the frame body 131 is removed to form a cavity 135 in the frame body 131. The cavity 135 is formed to penetrate the frame body 131, and a portion of the upper surface of the package substrate 110 may be exposed through the frame body 131.

Referring to FIG. 2D, the semiconductor chip 120 is mounted on the package substrate 110 exposed through the cavity 135 of the frame body 131. The semiconductor chip 120 may be fixed on the package substrate 110 by an adhesive film 153 . After the semiconductor chip 120 is placed on the package substrate 110, a conductive connection pillar 155 may be formed on the chip pad 121 of the semiconductor chip 120.

Referring to FIG. 2E, a preliminary sealing layer 151p is formed to cover the semiconductor chip 120 and the via frame 130. The preliminary sealing layer 151p may be filled in the cavity 135 of the frame body 131 and cover the sidewall of the semiconductor chip 120. Additionally, the preliminary sealing layer 151p may cover the upper surface of the semiconductor chip 120 and the conductive connection pillar 155.

Referring to FIGS. 2E and 2F , a polishing process is performed to remove a portion of the preliminary sealing layer 151p so that the conductive connection pillar 155 and the vertical connection conductor 133 are exposed to the outside. Another part of the preliminary sealing layer 151p remaining after the polishing process may form the sealing layer 151. Through the polishing process, a portion of the conductive connection pillar 155 and/or a portion of the via frame 130 may be removed along with a portion of the preliminary sealing layer 151p. The polishing process may include a planarization process such as chemical mechanical polishing. The polished top surface 1511 of the sealing layer 151, the polished top surface of the conductive connection pillar 155, and the polished top surface 130U of the via frame 130 may be on the same plane.

Referring to FIG. 2G, the redistribution structure 140 is formed on the top surface 1511 of the sealing layer 151 and the top surface 130U of the via frame 130. For example, the redistribution structure 140 may be formed by performing a redistribution process on the top surface 1511 of the sealing layer 151 and the top surface 130U of the via frame 130. For example, to form the redistribution structure 140, a second wiring insulating layer 141 including a via hole is formed on the upper surface 1511 of the sealing layer 151 and the upper surface 130U of the via frame 130. A step of forming an insulating layer, a second conductive via pattern 1433 filling the via hole of the second wire insulating layer 141, and a second conductive layer 1431 extending along the upper surface of the second wire insulating layer 141. ) can be repeated several times. After forming the redistribution structure 140, a connection bump 190 is formed on the redistribution structure 140. For example, the connection bump 190 may be formed through a solder ball attach process and a reflow process.

Afterwards, a sawing process is performed on the structure of Figure 2g. That is, the structure manufactured at the panel level can be cut along the scribe lane to separate the structure manufactured at the panel level into individual semiconductor packages 100 as shown in FIG. 1 .

3A to 3C are cross-sectional views showing a method of manufacturing a semiconductor package according to exemplary embodiments of the present invention. Hereinafter, the description will focus on differences from the semiconductor package and its manufacturing method described with reference to FIGS. 1 and 2A to 2G.

Referring to FIG. 3A, the package substrate 110 is formed on the carrier substrate CA. The package substrate 110 includes a first conductive wiring structure 113 including a plurality of first wiring insulating layers 111, first conductive layers 1131, and first conductive via patterns 1133. can do. The package substrate 110 may be formed through a rewiring process similar to that previously described with reference to FIG. 2B.

Referring to FIG. 3B, after forming the package substrate 110, a via frame 130 in the form of a flat plate or panel is placed on the package substrate 110. In some example embodiments, between the via frame 130 and the package substrate 110, a physical connection between the via frame 130 and the package substrate 110 and a vertical connection conductor 133 of the via frame 130 An anisotropic conductive film or an anisotropic conductive paste may be disposed for electrical connection between the first conductive wiring structure 113 of the package substrate 110 and the first conductive wiring structure 113 of the package substrate 110 .

Referring to FIG. 3C, a portion of the frame body 131 is removed to form a cavity 135 in the frame body 131. The cavity 135 is formed to penetrate the frame body 131, and the package substrate 110 may be exposed through the cavity 135 of the frame body 131.

After forming the cavity 135 in the frame body 131, the semiconductor chip 120 is mounted, the sealing layer 151 is formed, and the redistribution structure 140 is formed, similarly to those described with reference to FIGS. 2D to 2G. , attaching the connection bump 190, and sawing steps are performed sequentially, and then the carrier substrate (CA) is removed to form a semiconductor package.

FIGS. 4A to 4E are cross-sectional views showing a method of manufacturing the via frame 130 shown in FIG. 2A. Hereinafter, a method of manufacturing the via frame 130 will be described with reference to FIGS. 4A to 4E together with FIG. 1 .

Referring to FIG. 4A, a conductive layer 310 is prepared. The conductive layer 310 may have a flat plate shape or a panel shape, and may include an upper surface 310U and a lower surface 310L that are opposed to each other. The conductive layer 310 may include a lower conductive layer 311 and an upper conductive layer 313 divided based on a virtual center line or center plane. For example, the conductive layer 310 may be copper or an alloy containing copper.

Referring to FIGS. 4A and 4B, a patterning process may be performed on the lower conductive layer 311. As a result of the patterning process for the lower conductive layer 311, the lower portion 1331 of the vertically connected conductor 133 of FIG. 1 may be formed. In example embodiments, the patterning process for the lower conductive layer 311 may include a wet etching process. Through a wet etching process performed from the lower surface 310L of the conductive layer 310, the lower portion 1331 of the vertically connected conductor 133 is formed to have an inclined sidewall, and the lower portion 1331 of the vertically connected conductor 133 is formed. The lower part 1331 may be formed so that its horizontal width gradually becomes wider as it moves upward.

4B and 4C, after forming the lower part 1331 of the vertically connected conductor 133, the side wall of the lower part 1331 of the vertically connected conductor 133 is formed on the lower side of the upper conductive layer 313. A covering lower insulating body 1311 is formed. For example, to form the lower insulating body 1311, an insulating material covering the lower part 1331 of the vertical connection conductor 133 is formed on the lower side of the upper conductive layer 313, and the vertical connection conductor 133 ) The insulating material can be polished so that the lower part 1331 is exposed. For example, the lower insulating body 1311 may be made of EMC.

Referring to FIGS. 4C and 4D, a patterning process may be performed on the upper conductive layer 313. As a result of the patterning process for the upper conductive layer 313, the upper portion 1333 of the vertically connected conductor 133 of FIG. 1 may be formed. In example embodiments, the patterning process for the upper conductive layer 313 may include a wet etching process. Through a wet etching process performed from the upper side of the upper conductive layer 313, the upper part 1333 of the vertically connected conductor 133 is formed to have an inclined sidewall, and the upper part of the vertically connected conductor 133 ( 1333) can be formed so that the horizontal width gradually widens downward. The lower part 1331 and the upper part 1333 of the vertically connected conductor 133 may be connected to each other to form the vertically connected conductor 133.

Referring to FIG. 4E, after forming the upper part 1333 of the vertical connecting conductor 133, the upper insulating body covers the side wall of the upper part 1333 of the vertical connecting conductor 133 on the lower insulating body 1311. Forms (1313). For example, to form the upper insulating body 1313, an insulating material covering the upper part 1333 of the vertical connecting conductor 133 is formed on the lower insulating body 1311, and the vertical connecting conductor 133 The insulating material may be polished so that the upper portion 1333 is exposed. For example, the upper insulating body 1313 may be formed of the same material as the lower insulating body 1311, for example, EMC. The upper insulating body 1313 and the lower insulating body 1311 may form the frame body 131.

Figure 5 is a cross-sectional view showing a semiconductor package 101 according to exemplary embodiments of the present invention. Hereinafter, the semiconductor package 101 shown in FIG. 5 will be described, focusing on differences from the semiconductor package 100 described with reference to FIG. 1 .

Referring to FIG. 5 , the semiconductor package 101 may include a package substrate 210, a semiconductor chip 120, a sealing layer 251, a vertical connection conductor 230, and a redistribution structure 140. . The semiconductor package 101 may be, for example, a semiconductor package with a fan-out structure.

The package substrate 210 may be a printed circuit board. The package substrate 210 includes, for example, a substrate insulating layer 211 containing at least one material selected from phenol resin, epoxy resin, and polyimide, and an upper conductive layer 213 on the upper surface of the substrate insulating layer 211. ) and a lower conductive layer 215 on the lower surface of the substrate insulating layer 211. The upper conductive layer 213 and the lower conductive layer 215 may be electrically connected through internal wiring of the package substrate 210. The lower conductive layer 215 may form a pad for connection to external devices. In FIG. 5 , the package substrate 210 is illustrated as corresponding to a printed circuit board, but, like the package substrate 210 of FIG. 1 , it may have a structure corresponding to a redistribution substrate.

The semiconductor chip 120 may be placed on the package substrate 210 . The semiconductor chip 120 may include upper and lower surfaces that are opposed to each other. A chip pad 121 may be provided on the upper surface of the semiconductor chip 120, and the lower surface of the semiconductor chip 120 may face the package substrate 210. The semiconductor chip 120 may be attached to the package substrate 210 by an adhesive film 153 provided between the lower surface of the semiconductor chip 120 and the package substrate 210 .

The sealing layer 251 is disposed on the package substrate 210 and may cover the semiconductor chip 120. The sealing layer 251 may cover the top surface of the package substrate 210 and the top surface and sidewalls of the semiconductor chip 120. Additionally, the sealing layer 251 may cover the sidewall of the conductive connection pillar 155 attached to the chip pad 121 of the semiconductor chip 120. In example embodiments, the top surface 2519 of the sealing layer 251 may be on the same plane as the top surface of the conductive connection pillar 155. In example embodiments, sealing layer 251 may be formed of EMC. In other example embodiments, the sealing layer 251 may be formed of a photosensitive material such as polyimide.

The vertical connection conductor 230 has a pillar shape extending in the vertical direction (eg, Z direction) and may penetrate the sealing layer 251 in the vertical direction (eg, Z direction). The lower surface of the vertically connected conductor 230 is connected to the upper conductive layer 213 of the package substrate 210, and the upper surface of the vertically connected conductor 230 is connected to the second conductive wiring structure 143 of the redistribution structure 140. ) can be connected to. In example embodiments, the top surface of the vertical connection conductor 230 may be on the same plane as the top surface 2519 of the sealing layer 251. The vertical connection conductor 230 may electrically connect the upper conductive layer 213 of the package substrate 210 and the second conductive wiring structure 143 of the redistribution structure 140. For example, the vertical connection conductor 230 is copper (Cu), aluminum (Al), solder, tin (Sn), zinc (Zn), lead (Pb), silver (Ag), gold (Au), palladium. (Pd) and/or doped polysilicon.

The redistribution structure 140 may be disposed on the sealing layer 251 . The redistribution structure 140 includes a plurality of second wiring insulating layers 141 stacked on the upper surface 2519 of the sealing layer 251 in a vertical direction (e.g., Z direction), and a second conductive layer ( 1431) and a second conductive wiring structure 143 including a second conductive via pattern 1433. The second conductive wiring structure 143 may be electrically connected to the vertical connection conductor 230 and to the chip pad 121 of the semiconductor chip 120 through the conductive connection pillar 155. The second conductive wiring structure 143 is between the chip pad 121 of the semiconductor chip 120 and the vertical connection conductor 230, between the chip pad 121 of the semiconductor chip 120 and the connection bump 190, and It may be configured to electrically connect the vertical connection conductor 230 and the connection bump 190.

FIGS. 6A to 6G are cross-sectional views showing a method of manufacturing the semiconductor package 101 of FIG. 5.

Referring to FIG. 6A, a package substrate 210 is prepared. The package substrate 210 may be a printed circuit board. After preparing the package substrate 210, a photosensitive material layer 610 is formed on the package substrate 210. The photosensitive material layer 610 may include an opening 611 that exposes the upper conductive layer 213 of the package substrate 210. For example, applying a photosensitive film on a package substrate 210 to form a photosensitive material layer 610, and performing a patterning process on the photosensitive film to expose the upper conductive layer 213. The steps for forming (611) may be performed sequentially.

Referring to FIG. 6B, a vertically connected conductor 230 is formed that at least partially fills the opening 611 of the photosensitive material layer 610. In example embodiments, vertical connection conductor 230 may be formed by a plating method. In other exemplary embodiments, the vertical connection conductor 230 may be formed through a printing method or a nano-paste process using a conductive material such as copper (Cu).

Referring to FIGS. 6B and 6C, after forming the vertical connection conductor 230, the photosensitive material layer 610 is removed. The photosensitive material layer 610 may be removed through a strip process.

Referring to FIG. 6D, the semiconductor chip 120 is mounted on the package substrate 210. The semiconductor chip 120 may be fixed on the package substrate 210 through an adhesive film 153 . After the semiconductor chip 120 is placed on the package substrate 210, a conductive connection pillar 155 may be formed on the chip pad 121 of the semiconductor chip 120.

Referring to FIG. 6E, a preliminary sealing layer 251p is formed covering the semiconductor chip 120 and the vertical connection conductor 230.

Referring to FIGS. 6E and 6F , a polishing process is performed to remove a portion of the preliminary sealing layer 251p so that the conductive connection pillar 155 and the vertical connection conductor 230 are exposed to the outside. Another part of the preliminary sealing layer 251p remaining after the polishing process may form the sealing layer 251. Through the polishing process, a portion of the conductive connection pillar 155 and/or a portion of the vertical connection conductor 230 may be removed along with a portion of the preliminary sealing layer 251p. The polishing process may include a planarization process such as chemical mechanical polishing. The polished top surface 2519 of the sealing layer 251, the polished top surface of the conductive connection pillar 155, and the polished top surface of the vertical connection conductor 230 may be on the same plane.

Referring to FIG. 6G, a redistribution process is performed on the sealing layer 251 to form the redistribution structure 140. After forming the redistribution structure 140, the connection bump 190 may be formed on the redistribution structure 140. Afterwards, a sawing process is performed on the structure of Figure 6g. That is, the structure manufactured at the panel level can be cut along the scribe lane to separate the structure manufactured at the panel level into individual semiconductor packages 101 as shown in FIG. 5 .

7A to 7C are cross-sectional views showing a method of manufacturing a semiconductor package according to exemplary embodiments of the present invention. The semiconductor package described with reference to FIGS. 7A to 7C is similar to FIG. 5 except that it further includes a conductive adhesive layer 261 interposed between the vertical connection conductor 230 and the upper conductive layer 213. It may be substantially the same or similar to the semiconductor package 101 described above. Hereinafter, the description will focus on differences from the semiconductor package 101 and its manufacturing method described with reference to FIGS. 5 and 6A to 6G.

Referring to FIG. 7A, a conductive adhesive layer 261 is formed on the upper conductive layer 213 of the package substrate 210. The conductive adhesive layer 261 may include solder, for example.

Referring to FIG. 7B, a vertical connection conductor 230 is disposed on the conductive adhesive layer 261. For example, the vertical connection conductor 230 can be attached to the conductive adhesive layer 261 using a stencil mask 620 with alignment holes.

Referring to FIG. 7C, the vertical connection conductor 230 can be fixed on the upper conductive layer 213 by performing a curing process using the laser beam 630. As the conductive adhesive layer 261 is hardened through the curing process, the vertical connection conductor 230 can be more firmly fixed on the upper conductive layer 213.

Thereafter, similarly to those described with reference to FIGS. 6D to 6G, the steps of mounting the semiconductor chip 120, forming the sealing layer 251, forming the redistribution structure 140, attaching the connection bump 190, and sawing are sequentially performed. By performing this, a semiconductor package can be manufactured.

Figure 8 is a cross-sectional view showing a semiconductor package 102 according to exemplary embodiments of the present invention. FIG. 9 is an enlarged view showing the area indicated by “AA” in FIG. 8. Hereinafter, the semiconductor package 102 shown in FIGS. 8 and 9 will be described, focusing on differences from the semiconductor package 101 described with reference to FIG. 5 .

8 and 9, the semiconductor package 102 includes a package substrate 210, a semiconductor chip 120, a sealing layer 251, a conductive connection pattern 270, a vertical connection conductor 280, and a cover insulation. It may include a layer 290 and a redistribution structure 140 . The semiconductor package 102 may be, for example, a semiconductor package with a fan-out structure.

The sealing layer 251 may cover the semiconductor chip 120 disposed on the package substrate 210. The sealing layer 251 may cover the top surface of the package substrate 210 and the top surface and sidewalls of the semiconductor chip 120. The sealing layer 251 includes a first through hole 2511 positioned to overlap the upper conductive layer 213 of the package substrate 210 in a vertical direction (e.g., Z direction), and a chip of the semiconductor chip 120. It may include a second through hole 2512 positioned to overlap the pad 121 in a vertical direction (eg, Z direction).

The conductive connection pattern 270 extends conformally along the surface of the sealing layer 251 and can be connected to the upper conductive layer 213 of the package substrate 210 and the chip pad 121 of the semiconductor chip 120, respectively. there is. In exemplary embodiments, the conductive connection pattern 270 is provided in the first through hole 2511 of the sealing layer 251 to connect the first portion 271 to the upper conductive layer 213 and the sealing layer 251. A second part 273 provided in the first through hole 2511 and connected to the chip pad 121 of the semiconductor chip 120, and a first part (273) extending along the upper surface 2519 of the sealing layer 251 ( It may include a third part 275 that electrically connects 271) and the second part 273.

The first portion 271 of the conductive connection pattern 270 may extend conformally along the surface defining the first through hole 2511 of the sealing layer 251. The first portion 271 of the conductive connection pattern 270 extends from the top to the bottom of the side wall of the sealing layer 251 defining the first through hole 2511 of the sealing layer 251, and the upper conductive layer 213 ) can extend along the surface.

The second portion 273 of the conductive connection pattern 270 may extend conformally along the surface defining the second through hole 2512 of the sealing layer 251. The second portion 273 of the conductive connection pattern 270 extends from the top to the bottom of the sidewall of the sealing layer 251 defining the second through hole 2512 of the sealing layer 251, and is connected to the semiconductor chip 120. It may extend along the surface of the chip pad 121. In other example embodiments, the second portion 273 of the conductive connection pattern 270 may be replaced with the conductive connection pillar 155 of FIG. 5 .

The vertical connection conductor 280 is disposed on the conductive connection pattern 270 and is disposed in the first through hole 2511 of the sealing layer 251 to fill the first through hole 2511 of the sealing layer 251. You can. The sidewall of the vertical connection conductor 280 may be spaced apart from the sealing layer 251 with the conductive connection pattern 270 therebetween, and the lower surface of the vertical connection conductor 280 may have the conductive connection pattern 270 therebetween. It may be spaced apart from the upper conductive layer 213 of the package substrate 210. Within the first through hole 2511 of the sealing layer 251, the vertical connection conductor 280 may be surrounded by the first portion 271 of the conductive connection pattern 270. That is, the first portion 271 of the conductive connection pattern 270 may surround the vertical connection conductor 280 from a plan view. The vertical connection conductor 280 may be electrically connected to the upper conductive layer 213 of the package substrate 210 and the chip pad 121 of the semiconductor chip 120 through the conductive connection pattern 270.

The vertical connection conductor 280 may include a portion buried in the first through hole 2511 of the sealing layer 251 and a protrusion 281 that protrudes upward from the upper surface 2519 of the sealing layer 251. there is. For example, the height at which the vertical connection conductor 280 protrudes from the upper surface 2519 of the sealing layer 251 may be approximately 5 micrometers to 50 micrometers.

The cover insulating layer 290 may be disposed on the sealing layer 251 and cover the top surface 2519 of the sealing layer 251 and the conductive connection pattern 270. Additionally, the cover insulating layer 290 may cover the sidewall of the vertically connected conductor 280, but may not cover the top surface 283 of the vertically connected conductor 280. In example embodiments, the top surface 291 of the cover insulating layer 290 may be on the same plane as the top surface 283 of the vertical connection conductor 280. In example embodiments, the cover insulating layer 290 may be formed of EMC. In other exemplary embodiments, the cover insulating layer 290 may be formed of a photosensitive material such as polyimide (PI) or polybenzoxazole (PBO).

In exemplary embodiments, the vertical connection conductor 280 may include a recess 285 provided on its upper surface 283. The recess 285 of the vertical connection conductor 280 may be filled with a buried insulating layer 295. The buried insulating layer 295 may be spaced apart from the cover insulating layer 290 with the vertical connection conductor 280 interposed therebetween. In example embodiments, the upper surface of the buried insulating layer 295 is in contact with the lower surface of the redistribution structure 140, the surface of the vertical connection conductor 280 is in contact with the lower surface of the redistribution structure 140 (i.e. The upper surface 283 of the vertical connection conductor 280 (excluding the concave portion 295) and the upper surface 291 of the cover insulating layer 290 in contact with the lower surface of the redistribution structure 140 are the same plane. It may be on the table. In example embodiments, buried insulating layer 295 may have the same material and/or combination of materials as cover insulating layer 290 .

The redistribution structure 140 may be disposed on the cover insulating layer 290 . The redistribution structure 140 includes a plurality of second wiring insulating layers 141 stacked on the top surface 291 of the cover insulating layer 290 in a vertical direction (e.g., Z direction), and a second conductive layer. It may include a second conductive wiring structure 143 including 1431 and a second conductive via pattern 1433. The lower surface of the second conductive via pattern 1433 in the lowermost second wire insulating layer 141 may be in contact with the vertical connection conductor 280 and the buried insulating layer 295. The second conductive wiring structure 143 is connected to the chip pad 121 of the semiconductor chip 120 and the upper conductive layer 213 of the package substrate 210 through the vertical connection conductor 280 and the conductive connection pattern 270. ) can be electrically connected to.

FIGS. 10A to 10H are cross-sectional views showing a method of manufacturing the semiconductor package 102 of FIG. 8.

Referring to FIG. 10A, a package substrate 210 is prepared. The package substrate 210 may be a printed circuit board. After preparing the package substrate 210, the semiconductor chip 120 is mounted on the package substrate 210. The semiconductor chip 120 may be fixed on the package substrate 210 by an adhesive film 153 .

Referring to FIG. 10b, a sealing layer 251 covering the semiconductor chip 120 is formed on the package substrate 210. The sealing layer 251 at least partially exposes the first through hole 2511 configured to at least partially expose the upper conductive layer 213 of the package substrate 210 and the chip pad 121 of the semiconductor chip 120. It may include a second through hole 2512 configured to do so. For example, to form the sealing layer 251, forming a photosensitive material film of a photosensitive material such as polyimide on the package substrate 210, and performing a patterning process on the photosensitive material film to form the photosensitive material. The steps of forming the first through hole 2511 and the second through hole 2512 in the film may be performed sequentially.

Referring to FIG. 10C, a conductive connection pattern 270 is formed conformally extending along the surface of the sealing layer 251. The conductive connection pattern 270 may be formed through a rewiring process. For example, the conductive connection pattern 270 may include a seed metal layer and a core metal layer formed through a plating process using the seed metal layer as a seed and stacked on the seed metal layer. The seed metal layer may include titanium (Ti), copper (Cu), chromium (Cr), tungsten (W), nickel (Ni), aluminum (Al), palladium (Pd), gold (Au), or a combination thereof. You can. The core metal layer may include copper (Cu) or an alloy of copper (Cu).

Referring to FIG. 10D, a mask layer 640 is formed on the sealing layer 251. The mask layer 640 may include a mask opening 641 positioned to overlap the first through hole 2511. The mask opening 641 of the mask layer 640 may define an area in which the vertical connection conductor 280 to be formed in a subsequent step will be formed.

After forming the mask layer 640, the vertical connection conductor 280 is formed. The vertical connection conductor 280 may be formed to fill the first through hole 2511 exposed through the mask opening 641 of the mask layer 640 and partially fill the mask opening 641. The vertical connection conductor 280 may be formed through, for example, a plating process. For example, the vertical connection conductor 280 may include copper (Cu) or an alloy of copper (Cu).

In example embodiments, the horizontal width of the mask opening 641 of the mask layer 640 may determine the horizontal width of the protrusion (281 in FIG. 9) of the vertical connection conductor 280. In example embodiments, the horizontal width of the mask opening 641 of the mask layer 640 may be larger than the horizontal width of the first through hole 2511 of the sealing layer 251. In this case, the protrusion 281 of the vertical connection conductor 280 may be formed to have a horizontal width greater than the horizontal width of the first through hole 2511 of the sealing layer 251.

Referring to FIGS. 10D and 10E, after forming the vertical connection conductor 280, the mask layer 640 is removed. The mask layer 640 may be removed through, for example, a strip process.

Referring to FIG. 10F, a preliminary cover insulating layer 290p is formed on the sealing layer 251 to cover the conductive connection pattern 270 and the vertical connection conductor 280.

Referring to FIGS. 10F and 10G , a polishing process is performed to remove a portion of the preliminary cover insulating layer 290p so that the vertical connection conductor 280 is exposed to the outside. Another part of the preliminary cover insulating layer 290p remaining after the polishing process may form the cover insulating layer 290 and the buried insulating layer 295. Through the polishing process, a portion of the vertical connection conductor 280 may be removed along with a portion of the preliminary cover insulating layer 290p. The polishing process may include a planarization process such as chemical mechanical polishing. The polished top surface of the cover insulating layer 290, the polished surface of the vertical connection conductor 280, and the polished top surface of the buried insulating layer 295 may be on the same plane.

Referring to FIG. 10h, a redistribution process is performed on the cover insulating layer 290 to form the redistribution structure 140. After forming the redistribution structure 140, the connection bump 190 may be formed on the redistribution structure 140. Afterwards, a sawing process is performed on the structure of Figure 10h. That is, the structure manufactured at the panel level can be cut along the scribe lane to separate the structure manufactured at the panel level into individual semiconductor packages 102 as shown in FIG. 8 .

11A and 11B are cross-sectional views showing a method of manufacturing a semiconductor package according to exemplary embodiments of the present invention. The semiconductor package described with reference to FIGS. 11A and 11B is similar to that of FIG. 8 except that the buried insulating layer 295 filling the concave portion 285 of the vertical connection conductor 280 in FIG. 8 is omitted. It may be substantially the same or similar to the semiconductor package 102 described above. Hereinafter, the description will focus on differences from the semiconductor package 102 and its manufacturing method described with reference to FIGS. 8, 9, and 10A to 10H.

Referring to FIG. 11A, a structure corresponding to the structure of FIG. 10F is prepared, and a polishing process is performed to remove a portion of the preliminary cover insulating layer 290p. The polishing process may be performed so that the concave portion (285 in FIG. 9) of the vertical connection conductor 280 can be removed. Since the concave portion 285 of the vertically connected conductor 280 is removed, the upper surface 283 of the vertically connected conductor 280 may be an overall flat plane.

Referring to FIG. 11B, a redistribution process is performed on the cover insulating layer 290 to form the redistribution structure 140. The lower surface of the second conductive via pattern 1433 in the lowermost second wiring insulating layer 141 may be in continuous contact with the upper surface of the vertical connection conductor 280. After forming the redistribution structure 140, the connection bump 190 attaching and sawing steps are sequentially performed, so that a semiconductor package can be manufactured.

As above, exemplary embodiments have been disclosed in the drawings and specification. In this specification, embodiments have been described using specific terms, but this is only used for the purpose of explaining the technical idea of the present disclosure and is not used to limit the meaning or scope of the present disclosure described in the claims. Therefore, those skilled in the art will understand that various modifications and other equivalent embodiments are possible therefrom. Therefore, the true technical protection scope of the present disclosure should be determined by the technical spirit of the attached claims.

100: semiconductor package 110: package substrate
120: semiconductor chip 130: via frame
131: frame body 133: vertical connection conductor
140: Rewiring structure

Claims (9)

A package substrate including a conductive layer;
a semiconductor chip on the package substrate;
a sealing layer provided on the package substrate to cover the semiconductor chip and including a first through hole and a second through hole;
a vertically connected conductor including a portion buried in a first through hole of the sealing layer and a portion protruding from an upper surface of the sealing layer, and electrically connected to the conductive layer of the package substrate;
a first portion extending along a sidewall of the sealing layer defining the first through hole of the sealing layer, a second portion connected to a chip pad of the semiconductor chip through the second through hole of the sealing layer, and a third portion extending along the upper surface of the sealing layer, wherein the first portion is disposed between the vertical connecting conductor and the sealing layer and between the vertical connecting conductor and the conductive layer of the package substrate, conductive connection pattern;
a cover insulating layer provided on the sealing layer and in contact with the vertical connection conductor; and
a redistribution structure provided on the cover insulating layer and including a conductive wiring structure electrically connected to the vertical connection conductor;
A semiconductor package containing a. According to claim 1,
The vertical connection conductor includes a recess,
further comprising a buried insulating layer provided in the concave portion of the vertical connection conductor and in contact with the conductive wiring structure of the redistribution structure,
A semiconductor package, wherein the buried insulating layer and the cover insulating layer include the same material. According to claim 2,
The surface of the cover insulating layer in contact with the redistribution structure, the surface of the vertical connection conductor in contact with the redistribution structure, and the surface of the buried insulating layer in contact with the redistribution structure are on the same plane. A semiconductor package characterized in that. According to claim 1,
A semiconductor package, characterized in that the upper surface of the vertically connected conductor is an overall flat plane. delete delete Mounting a semiconductor chip on a package substrate including a conductive layer;
A sealing layer covering the semiconductor chip and the package substrate and including a first through hole exposing at least a portion of the conductive layer of the package substrate and a second through hole exposing at least a portion of a chip pad of the semiconductor chip. forming step;
a first portion extending along a sidewall of the sealing layer defining the first through hole of the sealing layer, a second portion connected to a chip pad of the semiconductor chip through the second through hole of the sealing layer, and forming a conductive connection pattern including a third portion extending along the upper surface of the sealing layer;
It includes a portion buried in a first through hole of the sealing layer and a portion protruding from an upper surface of the sealing layer, and is electrically connected to the conductive layer of the package substrate and the chip pad of the semiconductor chip through the conductive connection pattern. forming a vertically connected conductor;
forming a cover insulating layer on the sealing layer, covering the sealing layer and contacting the vertical connection conductor; and
forming a redistribution structure on the cover insulating layer, including a conductive wiring structure electrically connected to the vertical connection conductor;
A method of manufacturing a semiconductor package comprising. According to claim 7,
The step of forming the cover insulating layer is,
forming a preliminary insulating layer covering the sealing layer and the vertical connection conductor; and
a polishing step of removing a portion of the preliminary insulating layer to expose the vertical connection conductor;
Including,
The preliminary insulating layer remaining after the polishing step forms a buried insulating layer that fills the concave portion of the cover insulating layer and the vertical connection conductor. According to claim 8,
A method of manufacturing a semiconductor package, wherein the surface of the cover insulating layer, the surface of the vertical connection conductor, and the surface of the buried insulating layer are on the same plane.

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