KR101376265B1 - 배선 기판 및 그 제조 방법 - Google Patents
배선 기판 및 그 제조 방법 Download PDFInfo
- Publication number
- KR101376265B1 KR101376265B1 KR1020080047382A KR20080047382A KR101376265B1 KR 101376265 B1 KR101376265 B1 KR 101376265B1 KR 1020080047382 A KR1020080047382 A KR 1020080047382A KR 20080047382 A KR20080047382 A KR 20080047382A KR 101376265 B1 KR101376265 B1 KR 101376265B1
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- KR
- South Korea
- Prior art keywords
- external connection
- wiring board
- plating layer
- connection pad
- pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 238000000034 method Methods 0.000 title claims description 39
- 238000007747 plating Methods 0.000 claims abstract description 107
- 238000004519 manufacturing process Methods 0.000 claims description 24
- 239000010949 copper Substances 0.000 claims description 19
- 238000005530 etching Methods 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 8
- 229910052737 gold Inorganic materials 0.000 claims description 7
- 229910052759 nickel Inorganic materials 0.000 claims description 7
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 230000002093 peripheral effect Effects 0.000 claims description 6
- 229910052718 tin Inorganic materials 0.000 claims description 5
- 229910045601 alloy Inorganic materials 0.000 claims description 4
- 239000000956 alloy Substances 0.000 claims description 4
- 229910052763 palladium Inorganic materials 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 238000010030 laminating Methods 0.000 claims 2
- 238000009413 insulation Methods 0.000 abstract description 2
- 239000004065 semiconductor Substances 0.000 description 21
- 229910000679 solder Inorganic materials 0.000 description 13
- 239000011347 resin Substances 0.000 description 10
- 229920005989 resin Polymers 0.000 description 10
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 9
- 239000010931 gold Substances 0.000 description 9
- 239000000758 substrate Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 238000007772 electroless plating Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000006866 deterioration Effects 0.000 description 4
- 230000008901 benefit Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- KDLHZDBZIXYQEI-UHFFFAOYSA-N palladium Substances [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/007—Manufacture or processing of a substrate for a printed circuit board supported by a temporary or sacrificial carrier
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H05K1/113—Via provided in pad; Pad over filled via
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
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- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
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- H05K3/243—Reinforcing the conductive pattern characterised by selective plating, e.g. for finish plating of pads
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
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- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
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- H05K2201/09472—Recessed pad for surface mounting; Recessed electrode of component
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
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- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09845—Stepped hole, via, edge, bump or conductor
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- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/03—Metal processing
- H05K2203/0376—Etching temporary metallic carrier substrate
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
- H05K3/205—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using a pattern electroplated or electroformed on a metallic carrier
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Structure Of Printed Boards (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (18)
- 소정 수의 배선층과 각 배선층 사이의 절연층을 갖고, 또한, 외부 회로에 접속하기 위한, 표면 도금층을 구비한 외부 접속용 패드를 갖는 배선 기판으로서,상기 외부 접속용 패드의 면적이 그 표면 도금층의 면적보다 작고,상기 외부 접속용 패드가 상기 표면 도금층이 설치된 제 1 면과, 그 반대측의 제 2 면을 갖고,상기 외부 접속용 패드가 배선 기판 표면으로 되는 면과 그 반대측의 면을 갖는 가장 외층 절연층 중에 매설되어 있고,상기 외부 접속용 패드에 구비된 상기 표면 도금층의 상면이 상기 배선 기판 표면으로 되는 가장 외층 절연층의 면에 노출해 있고,상기 가장 외층 절연층의 반대측의 면으로부터 상기 외부 접속용 패드의 제 2 면에 도달하는 비아가 설치되어 있고,상기 가장 외층 절연층의 반대측의 면에 있어서의 상기 비아의 직경이 상기 외부 접속용 패드의 제 2 면측에 있어서의 상기 비아의 직경보다 크며, 상기 외부 접속용 패드의 제 2 면에 상기 비아가 접속되어 있는것을 특징으로 하는 배선 기판.
- 제 1 항에 있어서,상기 외부 접속용 패드의 외주부와 상기 표면 도금층의 외주부가 수평 방향의 간격을 갖는것을 특징으로 하는 배선 기판.
- 제 1 항 또는 제 2 항에 있어서,상기 외부 접속용 패드가, 상기 표면 도금층의 상면을 제외하고, 상기 가장 외층 절연층 중에 매설되어 있는것을 특징으로 하는 배선 기판.
- 제 1 항 또는 제 2 항에 있어서,상기 표면 도금층의 상면이 상기 가장 외층 절연층 표면으로부터 오목하게 위치하는것을 특징으로 하는 배선 기판.
- 제 1 항 또는 제 2 항에 있어서,상기 표면 도금층의 상면이 상기 가장 외층 절연층 표면으로부터 돌출해 있는것을 특징으로 하는 배선 기판.
- 제 1 항 또는 제 2 항에 있어서,당해 배선 기판의 상기 외부 접속용 패드가 설치된 면과는 반대측의 면에, 다른 외부 접속용 패드가 설치되어 있는것을 특징으로 하는 배선 기판.
- 제 1 항 또는 제 2 항에 있어서,상기 외부 접속용 패드의 재료가 구리 또는 그 합금인것을 특징으로 하는 배선 기판.
- 제 1 항 또는 제 2 항에 있어서,상기 표면 도금층이 Ni과 Au의 조합, Ni과 Pd과 Au의 조합, Sn, 또는 Sn과 Ag의 조합에 의해 형성되어 있는것을 특징으로 하는 배선 기판.
- 소정 수의 배선층과 각 배선층 사이의 절연층을 갖고, 또한, 외부 회로에 접속하기 위한, 표면 도금층을 구비한 외부 접속용 패드를 갖는 배선 기판이며,상기 외부 접속용 패드의 면적이 그 표면 도금층의 면적보다 작고,상기 외부 접속용 패드가 상기 표면 도금층이 설치된 제 1 면과, 그 반대측의 제 2 면을 갖고,상기 외부 접속용 패드가 배선 기판 표면으로 되는 면과 그 반대측의 면을 갖는 가장 외층 절연층 중에 매설되어 있고,상기 외부 접속용 패드에 구비된 상기 표면 도금층의 상면이 상기 배선 기판 표면으로 되는 가장 외층 절연층의 면에 노출해 있고,상기 가장 외층 절연층의 반대측의 면으로부터 상기 외부 접속용 패드의 제 2 면에 도달하는 비아가 설치되어 있고,상기 가장 외층 절연층의 반대측의 면에 있어서의 상기 비아의 직경이 상기 외부 접속용 패드의 제 2 면측에 있어서의 상기 비아의 직경보다 크며, 상기 외부 접속용 패드의 제 2 면에 상기 비아가 접속되는배선 기판을 제조하는 방법으로서,지지 부재 상에 표면 도금층과, 당해 표면 도금층보다 면적이 작은 외부 접속용 패드를 순차 형성하는 공정과,당해 외부 접속용 패드를 형성한 지지 부재 상에 소정 수의 절연층과 배선층을 형성하는 공정과,상기 지지 부재를 제거하는 공정을 포함하는 것을 특징으로 하는 배선 기판 제조 방법.
- 제 9 항에 있어서,상기 지지 부재 상에 표면 도금층과, 당해 표면 도금층보다 면적이 작은 외부 접속용 패드를 순차 형성하는 공정이, 상기 외부 접속용 패드의 면적을 표면 도금층의 면적보다 작게 하는 처리를 에칭에 의해 수행하는 공정을 갖는것을 특징으로 하는 배선 기판 제조 방법.
- 제 9 항 또는 제 10 항에 있어서,상기 외부 접속용 패드의 외주부와 상기 표면 도금층의 외주부에, 수평 방향의 간격을 갖게 하는것을 특징으로 하는 배선 기판 제조 방법.
- 제 9 항 또는 제 10 항에 있어서,상기 지지 부재 상에 소정 수의 절연층과 배선층을 형성하는 공정이, 상기 지지 부재 상에, 상기 외부 접속용 패드를 피복하도록 상기 가장 외층 절연층을 적층하는 공정을 갖고,상기 지지 부재를 제거하는 공정에서, 상기 가장 외층 절연층으로부터 상기 지지 부재를 제거하는 것에 의해, 상기 표면 도금층의 상면을 제외하고, 상기 가장 외층 절연층 중에 매설된 상기 외부 접속용 패드를 얻는것을 특징으로 하는 배선 기판 제조 방법.
- 제 9 항 또는 제 10 항에 있어서,상기 지지 부재 상에 표면 도금층과, 당해 표면 도금층보다 면적이 작은 외부 접속용 패드를 순차 형성하는 공정이, 상기 지지 부재 상에 도금층을 형성하고, 당해 도금층 상에 상기 표면 도금층, 외부 접속용 패드를 순차 형성하는 공정을 갖고,상기 지지 부재를 제거하는 공정에서, 상기 지지 부재를 제거함과 함께, 상기 도금층을 제거하고, 상기 표면 도금층의 상면이 상기 가장 외층 절연층 표면으로부터 오목하게 위치하는 외부 접속용 패드를 얻는것을 특징으로 하는 배선 기판 제조 방법.
- 제 9 항 또는 제 10 항에 있어서,상기 지지 부재 상에 표면 도금층과, 당해 표면 도금층보다 면적이 작은 외부 접속용 패드를 순차 형성하는 공정이, 상기 지지 부재 상에 오목부를 형성하고, 당해 오목부 내에 상기 표면 도금층, 외부 접속용 패드를 순차 형성하는 공정을 갖고,상기 지지 부재를 제거하는 공정에서, 상기 표면 도금층의 상면이 상기 가장 외층 절연층 표면으로부터 돌출한 외부 접속용 패드를 얻는것을 특징으로 하는 배선 기판 제조 방법.
- 제 9 항 또는 제 10 항에 있어서,상기 지지 부재 상에 소정 수의 절연층과 배선층을 형성하는 공정이, 가장 상층에 적층된 절연층 상에, 다른 외부 접속 패드를 형성하는 공정을 갖는것을 특징으로 하는 배선 기판 제조 방법.
- 제 9 항 또는 제 10 항에 있어서,상기 지지 부재 상에 소정 수의 절연층과 배선층을 형성하는 공정이,상기 지지 부재 상에 상기 외부 접속용 패드를 피복하도록 상기 가장 외층 절연층을 적층하는 공정과,상기 가장 외층 절연층에 상기 외부 접속용 패드의 제 2 면에 도달하는 비아를 형성함과 함께, 당해 가장 외층 절연층 상에, 상기 비아와 접속하는 배선층을 형성하는 공정을 갖는것을 특징으로 하는 배선 기판 제조 방법.
- 제 9 항 또는 제 10 항에 있어서,상기 외부 접속용 패드의 재료가 구리 또는 그 합금인것을 특징으로 하는 배선 기판 제조 방법.
- 제 9 항 또는 제 10 항에 있어서,상기 표면 도금층이 Ni과 Au의 조합, Ni과 Pd과 Au의 조합, Sn, 또는 Sn과 Ag의 조합에 의해 형성되어 있는것을 특징으로 하는 배선 기판 제조 방법.
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US20080298038A1 (en) | 2008-12-04 |
TW200847348A (en) | 2008-12-01 |
KR20080106013A (ko) | 2008-12-04 |
TWI458052B (zh) | 2014-10-21 |
JP5101169B2 (ja) | 2012-12-19 |
CN101315917A (zh) | 2008-12-03 |
US8357860B2 (en) | 2013-01-22 |
CN101315917B (zh) | 2012-01-04 |
US20130097856A1 (en) | 2013-04-25 |
US9258899B2 (en) | 2016-02-09 |
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