KR101103550B1 - A method for forming a metal line in semiconductor device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in a semiconductor device, and the present invention relates to dry etching of parasite spacers and micro trenches generated during a via and / or trench forming process for forming a metal wiring pattern. Removed by process. Therefore, in the present invention, it is possible to prevent the generation of EM (Electro Migration), SM (Stress Migration), voids, etc. due to the stress applied to the barrier film, thereby improving the reliability of the metal wiring. .

Semiconductor devices, metallization, metal plugs, copper metal layers, parasitic spacers, micro trenches

Description

A METHOD FOR FORMING A METAL LINE IN SEMICONDUCTOR DEVICE

1 to 8 are cross-sectional views illustrating a method of forming metal wirings of a semiconductor device in accordance with a preferred embodiment of the present invention.

9 and 10 are TEM photographs for explaining parasitic spacers and micro trenches generated in the prior art.

Description of the Related Art

10 semiconductor substrate 12 gate oxide film

14 polysilicon film 16 gate electrode

18 source / drain region 20 first interlayer insulating film

22, 34: photoresist pattern 26: metal plug

28 diffusion barrier film 30 second interlayer insulating film

32: antireflection film 36: metal wiring formation pattern

38: Parasitic Spacers and Micro Trench

42: metal wiring

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wiring in a semiconductor device, and more particularly, to a method for forming metal wiring in a semiconductor device which can improve the reliability of metal wiring by preventing the formation of micro trenches by parasitic spacers generated during the metal wiring forming process. It is about.

In a semiconductor device or an electronic device, a conductor film such as aluminum (Al) or tungsten (W) is deposited on an insulating film as a metal wiring forming technique, and then the conductor film is subjected to a conventional photolithography process and dry etching ( The technique of forming metal wiring by patterning through dry etching process has been established and widely used in this field. In particular, recently, a method of using a low-resistance metal such as copper (Cu) instead of aluminum or tungsten as wiring to reduce the RC delay centering on logic devices requiring high integration and high performance among semiconductor devices has recently been used. Is being studied. In RC, 'R' represents wiring resistance, and 'C' represents dielectric constant of the insulating film.

In the metallization process using copper, the patterning process is more difficult than aluminum or tungsten. Accordingly, a so-called 'damascene' process is used in which a trench is first formed and a metal wiring is formed to fill the trench. Currently commonly used processes include the single damascene process and the dual damascene process. The single damascene process is a method of forming a via hole and then filling the via hole with a conductive material, forming a wiring trench on the upper portion thereof, and then filling the trench with a wiring material to form a metal wiring. The dual damascene process is a method for forming metal vias by forming via holes and wiring trenches and then filling the wiring material with via holes and wiring trenches at the same time. In addition, various methods are suggested.

However, copper has a problem of degrading characteristics such as saturation current, threshold voltage and leakage current due to the rapid diffusion through the interstitial site in silicon. Is generated. As a result, the copper metal layer may not be used as a contact plug in a metal contact process for connecting the silicon substrate and the metal wiring.

For this reason, tungsten is used instead of copper for contact plugs. In general, a contact plug forming method includes a process of filling tungsten in a contact hole and then planarizing it by a chemical mechanical polishing (CMP) method. As described above, in the case of forming the contact plug using tungsten, micro trenches are generated by parasitic spacers between the tungsten and the copper metal wires as shown in the circles of FIGS. 9 and 10. As a result, even when the barrier films Ta, TaN, and the like are not stably deposited or stress is generated, stress (EM), stress migration (SM), stress induced voids (stress induced void), and the like are generated. Will be generated. Here, the stress-induced void refers to the generation of voids due to the movement of copper atoms in the practical application of semiconductor devices.

Accordingly, the present invention has been made to solve the above problems, and prevents the formation of micro trenches by parasitic spacers generated during the metal wiring formation process, thereby improving the reliability of metal wiring. The purpose is to provide.

According to an aspect of the present invention for achieving the above object, there is provided a semiconductor substrate having a metal plug formed in the first interlayer insulating film, depositing a second interlayer insulating film on the first interlayer insulating film, Performing an etching process to expose the upper portion of the metal plug to form a metal wiring pattern; and performing a second etching process to recess the exposed metal plug and at the same time to form the metal wiring pattern. Removing the micro trenches generated in the first interlayer insulating layers on both upper sidewalls of the metal plugs, and forming metal wirings to fill the metal wiring patterns. A method is provided.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.

1 to 5 are cross-sectional views illustrating a method of forming metal wirings of a semiconductor device in accordance with a preferred embodiment of the present invention. Here, the same reference numerals among the reference numerals shown in FIGS. 1 to 5 are the same components having the same function.

Referring to FIG. 1, a semiconductor substrate 10 cleaned by a pretreatment cleaning process is provided. The pretreatment cleaning process is performed with DHF (Diluted HF) followed by SC-1 (NH ₄ OH / H ₂ O ₂ / H ₂ O), or with BOE (Buffer Oxide Etchant) followed by SC-1 It can be carried out as.

Then, a well ion implantation process and a threshold voltage ion implantation process are performed to form a well region (not shown) and a threshold voltage ion implantation region (not shown) in the semiconductor substrate 10. In this case, a screen oxide may be formed on the semiconductor substrate 10 before the well ion implantation process and the threshold voltage ion implantation process to prevent damage to the semiconductor substrate 10.

Then, a gate oxide film 12 is formed on the semiconductor substrate 10. In this case, the gate oxide film 12 may be formed by a wet oxidation process and an annealing process. In this case, the wet oxidation process is carried out within a temperature range of 750 ° C to 800 ° C, and the annealing process is performed for 20 minutes to 30 minutes using N ₂ gas at a temperature range of 900 ° C to 910 ° C.

Then, a polysilicon film 14 is deposited on the gate oxide film 12. At this time, the polysilicon film 14 is low of 0.1torr to 0.3torr in the temperature range of 450 ° C to 600 ° C using SiH ₄ or Si ₂ H ₆ and PH ₃ gas by low pressure chemical vapor deposition (LPCVD). Can be deposited under pressure.

Then, a photolithography process is performed to sequentially pattern the polysilicon layer 14 and the gate oxide layer 12 to form the gate electrode 16.

Then, the source / drain ion implantation process is performed on the semiconductor substrate 10 exposed to both sides of the gate electrode 16 to form the source / drain regions 18. Here, the source / drain region 18 may be formed of a low concentration junction region and a high concentration junction region. In this case, the low concentration junction region is formed by defining the gate electrode 16 and then performing a low concentration ion implantation process. The high concentration junction region is formed by forming spacers (not shown) on both side walls of the gate electrode 16 after forming the low concentration junction region, and performing the high concentration ion implantation process using the spacer as an ion implantation mask. On the other hand, the high concentration junction region is formed deeper than the low concentration junction region.

Then, a metal layer (not shown) formed of cobalt (Co) or titanium (Ti) or nickel (Ni) or a stacked structure is deposited on the entire structure where the source / drain regions 18 are formed.

Then, a heat treatment process is performed on the metal layer to form a silicide layer (not shown) on the gate electrode 16 and the source / drain regions 18. In this case, when the metal layer is made of cobalt, the heat treatment process is divided into two times, and when it is made of titanium, it is preferable to carry out one time. This is because, in the case of cobalt, phase change is required through two heat treatment processes in order to form CoSi ₂ having a low specific resistance. Of course, between two heat treatment processes, a washing process for removing unreacted reactants is performed.

Referring to FIG. 2, an insulating film 20 (hereinafter referred to as a 'first interlayer insulating film') is deposited on the entire structure in which the silicide layer is formed. At this time, the first interlayer insulating film 20 is preferably formed of a low dielectric material having a dielectric constant of 1.8 to 5.0, the thickness of which is formed from a thickness of 5000 kPa to 15000 kPa from the semiconductor substrate 10. For example, the first interlayer insulating film 20 may be formed of boron phosphorus silicate glass (BPSG), phosphorus silicate glass (PSG), plasma enhanced tetra thyle ortho silicate (peteos), un-doped silicate glass (usg), and fluorinated silicate glass (FSG). Or CDO (Carbon Doped Oxide) or the like, i.e., a film in which fluorine, hydrogen, boron, carbon, methyl, silicon or phosphorus is locally bonded or interstitial to SiO or SiO ₂ . Can be formed.

Then, a chemical mechanical polishing (CMP) process is performed to planarize the first interlayer insulating film 20.

Referring to FIG. 3, after the photoresist is applied over the entire structure including the planarized first interlayer insulating layer 20, the photoresist pattern is sequentially performed by performing exposure and development processes using a photomask. (photoresist pattern; 22).

Then, an etching process using the photoresist pattern 22 as an etching mask is performed to pattern the first interlayer insulating layer 20 to expose the contact / hole regions 18 exposing the source / drain regions 18 between the gate electrodes 16. To form. Here, the etching process is carried out using CxHyFz (x, y, z is 0 or natural number) as the stock angle gas, and O ₂ , N ₂ , Ar, He or the like as the additive gas.

Then, a strip process is performed to remove the photoresist pattern 22.

Referring to FIG. 4, a barrier film (not shown) is deposited along a step of an upper surface of the entire structure including the contact hole 24. Here, the barrier film is formed of any one of Ta, TaN, TaC, TaAlN, TaSiN, TaSi ₂ , Ti, TiN, TiSiN, WN, WBN, WC, Co, and CoSi ₂ , or have a structure in which at least two or more of them are stacked. Can be. For example, when the barrier film is made of a Ti film / TiN film stacked structure, the Ti film functions as a glue layer. In addition, they may be deposited by PVD (Physical Vapor Chemical Vapor Deposition), CVD (Chemical Vapor Deposition) or ALD (Atomic Layer Depostion).

Then, a metal material is deposited on the entire structure so that the contact hole 24 is embedded. Here, the metal material may be formed of tungsten or aluminum. It is preferably formed of tungsten.

Then, the etching gas containing a halogen group element of the periodic table such as CMP process or SF ₆ / Cl ₂ / BCl ₃ as a stock angle gas, and the etch back using an additive gas such as O ₂ , N ₂ , Ar or He gas ( The metal plug 26 is formed by performing a planarization process by an etchback process.

Referring to FIG. 5, the diffusion barrier layer 28 may be deposited on the entire structure including the metal plug 26. Here, the diffusion barrier 28 may be formed of a material such as SiON, SiN or SiC. That is, the diffusion barrier 28 is formed of a material in which at least one of oxygen, nitrogen, carbon, and methyl is bonded to silicon. And, the thickness may be formed to a thickness of 100Å to 1000Å. On the other hand, the diffusion barrier 28 is formed to prevent the diffusion of copper atoms when the subsequent metal wiring (see '42' in FIG. 8) is formed of copper metal.

Then, an insulating film 30 (hereinafter referred to as a 'second interlayer insulating film') is deposited on the diffusion barrier film 28. Here, the second interlayer insulating film 30 may be deposited with the same material as the first interlayer insulating film 20 to a thickness of 1000 Å to 8000 Å.

Then, the anti-reflection film 32 may be deposited on the second interlayer insulating film 30. Here, the anti-reflection film 32 may be deposited with an organic material or an inorganic material such as SiON to a thickness of 200 kW to 1500 kW.                     

Referring to FIG. 6, after the photoresist is coated on the entire structure including the antireflection film 32, the photoresist pattern 34 is formed by performing exposure and development processes using a photo mask.

Next, an etching process using the photoresist pattern 34 is performed to pattern the antireflection film 32, the second interlayer insulating film 30, and the diffusion barrier film 28 to expose the upper portion of the metal plug 26. As a result, via holes and / or trenches 36 (hereinafter referred to as 'metal wiring formation patterns') are formed. In this case, the etching of the diffusion barrier 28 is to target an etching amount of 30% or more than the thickness. The etching process is performed by a dry etching method, and CxHyFz (x, y, z is 0 or natural water) is used as a stock angle gas, and O ₂ , N ₂ , Ar, He, etc. are added to the stock angle gas. do. In this case, when the ratio of x to y and z is increased, the C / F ratio is increased to increase the etching selectivity of the diffusion barrier 28. In addition, by reducing the addition ratio of O ₂ , N ₂ , Ar, He gas, etc., the etching selectivity may be increased. On the other hand, decreasing the ratio of x to y and z, or increasing the addition ratio of O ₂ , N ₂ , Ar, He gas, etc., decreases the C / F ratio, thereby reducing the etching selectivity to the diffusion barrier 28. Can be reduced. By this process, parasitic spacers and micro trenches 38 are formed in the upper sidewall portions of the metal plug 26.

Referring to FIG. 7, an etching process using a photoresist pattern 34 is performed to recess the metal plug 26, and the first interlayer insulating layer 20 disposed on both sidewalls of the metal plug 26. A portion of the top of the etch is etched to remove the micro trench 38 formed in FIG. There is no micro trench (see '38' in FIG. 6) by parasitic spacers as shown '40'. In this case, the etching process may dry etching the metal plug 26 (eg, SF ₆ , Cl ₂ , BCl _3, etc.), and the etching gas capable of removing the micro trench 38 by parasitic spacers. (Eg, SF ₆ , CxHyFz (x, y, z is 0 or natural number)).

Referring to FIG. 8, a strip process is performed to remove the photoresist pattern 34, and then the anti-reflection film 32 is removed.

Then, a barrier film (not shown) is deposited along the step of the upper surface of the entire structure including the metallization pattern 36. Here, the barrier film is formed of any one of Ta, TaN, TaC, TaAlN, TaSiN, TaSi ₂ , Ti, TiN, TiSiN, WN, WBN, WC, Co, and CoSi ₂ , or have a structure in which at least two or more of them are stacked. Can be. For example, when the barrier film has a Ti film / TiN film laminated structure, the Ti film functions as an adhesive layer. And they can be deposited by PVD, CVD or ALD method.

Then, a metal material is deposited on the entire structure so that the metallization pattern 36 is buried. Here, the metal material may be formed of a metal layer made of any one of Al, Pt (Platinum), Pd (Palladium), Ru (Rubidium), St (Strontium), Rh (Rhadium), Co, and copper. It is preferably formed of copper.

Then, the etching gas containing the halogen group element of the periodic table such as CMP process or SF ₆ / Cl ₂ / BCl _{3 is used} as the stock angle gas for the upper part of the entire structure on which the metal material is deposited, and O ₂ , N ₂ , Ar or The metallization 42 is formed by performing a planarization process by an etch back process using an additive gas such as He gas.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, according to the present invention, the barrier is formed by removing the micro trenches by parasitic spacers generated during the via and / or trench forming process for forming the metallization pattern by a dry etching process. It is possible to prevent the generation of EM (Electro Migration), SM (Stress Migration), voids, etc. due to the stress applied to the film, thereby improving the reliability of the metal wiring.

Claims (11)

(a) providing a semiconductor substrate having a metal plug formed in the first interlayer insulating film; (b) depositing a second interlayer insulating film on the first interlayer insulating film including the metal plug; (c) selectively etching the second interlayer insulating layer in a first etching process to form a trench to expose an upper portion of the metal plug; (d) etching the upper portion of the metal plug by a second etching process to recess the metal plug; And (e) filling the inside of the trench to form a metal wiring connected to the metal plug. The method of claim 1, The first etching process is performed using CxHyFz (x, y, z is 0 or natural water) gas, or by adding at least any one of O ₂ , N ₂ , Ar and He to the CxHyFz stock corner gas A metal wiring forming method for a semiconductor device, characterized in that carried out. The method of claim 1, Wherein the second etching process is performed using SF ₆ , Cl ₂ , BCl ₃ or CxHyFz (x, y, z is 0 or natural water) etching gas. The method of claim 1, And the first and second interlayer insulating films are formed of a material having a dielectric constant of 1.8 to 5.0. The method of claim 1, And the first and second interlayer insulating films are formed of BPSG, PSG, PETEOS, USG, FSG, or CDO. The method of claim 1, And the first and second interlayer insulating films are formed of a film in which fluorine, hydrogen, boron, carbon, methyl, silicon, or phosphorus is bonded or inserted locally to SiO or SiO ₂ . The method of claim 1, In the case of forming the metal interconnection with a copper metal material, in the step (b), before the deposition of the second interlayer insulating film on the first interlayer insulating film, further comprising the step of depositing a diffusion barrier film on the first interlayer insulating film Metal wiring forming method of a semiconductor device comprising a. The method of claim 1, And removing parasitic spacers and micro trenches generated by the first etching process during the second etching process. The method of claim 1, further comprising depositing a diffusion barrier between the first interlayer insulating film and the second interlayer insulating film. 2. The method of claim 1, further comprising forming an antireflection film on the second interlayer insulating film. The method of claim 1, wherein the metal wiring is formed of a metal layer made of any one of Al, Pt, Pd, Ru, St, Rb, Co, and Cu.

Images