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KR100578230B1 - Bit line formation method using dual damascene process - Google Patents

Bit line formation method using dual damascene process Download PDF

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KR100578230B1
KR100578230B1 KR1020000036730A KR20000036730A KR100578230B1 KR 100578230 B1 KR100578230 B1 KR 100578230B1 KR 1020000036730 A KR1020000036730 A KR 1020000036730A KR 20000036730 A KR20000036730 A KR 20000036730A KR 100578230 B1 KR100578230 B1 KR 100578230B1
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film
bit line
forming
nitride film
insulating film
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KR20020002528A (en
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오찬권
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주식회사 하이닉스반도체
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/30DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48Data lines or contacts therefor
    • H10B12/482Bit lines
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/31051Planarisation of the insulating layers
    • H01L21/31053Planarisation of the insulating layers involving a dielectric removal step
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819Smoothing of the dielectric
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 비트라인배선의 리프팅을 방지하는데 적합한 비트라인의 형성 방법에 관한 것으로, 불순물접합층과 워드라인이 형성된 반도체소자의 제조 방법에 있어서, 상기 워드라인상에 제 1 절연막을 형성한후, 후속 듀얼다마신 식각시 상기 제 1 절연막의 손실을 방지하기 위한 질화막과 비트라인용 제 2 절연막을 순차적으로 형성하는 제 1 단계; 듀얼 다마신 마스크를 이용하여 상기 제 2 절연막, 절연막손실방지용 질화막 및 제 1 절연막을 식각하여 상기 불순물접합층이 노출되는 비트라인용 콘택홀을 형성하는 제 2 단계; 상기 제 2 단계의 결과물 전면에 측벽용 질화막을 형성한후, 전면식각하여 상기 제 2 절연막의 내벽에 접하는 스페이서를 형성하는 제 3 단계; 상기 제 3 단계의 결과물상에 확산방지막, 비트라인용 배선막을 순차적으로 형성한후, 상기 비트라인용 배선막을 전면식각하여 상기 콘택홀 내부로 소정깊이만큼 리세스시키는 제 4 단계; 및 상기 리세스된 배선막상에 상기 배선막 보호용 질화막을 형성한후, 상기 제 2 절연막이 드러날때까지 상기 배선막 보호용 질화막을 화학적기계적연마하여 비트라인을 형성하는 제 5 단계를 포함하여 이루어짐을 특징으로 한다
The present invention relates to a method for forming a bit line suitable for preventing the lifting of a bit line wiring. In the method for manufacturing a semiconductor device in which an impurity junction layer and a word line are formed, after forming a first insulating film on the word line, A first step of sequentially forming a nitride film and a second insulating film for bit lines to prevent loss of the first insulating film during subsequent dual damascene etching; Etching a second insulating film, an insulating film loss preventing nitride film, and a first insulating film by using a dual damascene mask to form a bit line contact hole through which the impurity bonding layer is exposed; A third step of forming a spacer in contact with an inner wall of the second insulating layer after forming a nitride film for the sidewall on the entire surface of the resultant of the second step; A fourth step of sequentially forming a diffusion barrier film and a bit line wiring film on the resultant of the third step, and then etching the bit line wiring film over the entire surface to recess the predetermined depth into the contact hole; And a fifth step of forming a bit line by chemically mechanically polishing the wiring film protection nitride film until the second insulating film is formed after forming the wiring film protection nitride film on the recessed wiring film. Should be

비트라인, 화학적기계적연마, 리프팅, 텅스텐, 구리, 마스크질화막, 듀얼다마신공정Bit line, chemical mechanical polishing, lifting, tungsten, copper, mask nitride film, dual damascene process

Description

듀얼다마신공정을 이용한 비트라인 형성 방법{METHOD FOR FORMING BITLINE USING DUAL DAMASCENE PROCESS} Bit line forming method using dual damascene process {METHOD FOR FORMING BITLINE USING DUAL DAMASCENE PROCESS}             

도 1a 내지 도 1d는 종래기술에 따른 비트라인의 형성 방법을 도시한 도면,1A to 1D illustrate a method of forming a bit line according to the prior art;

도 2a 내지 도 2d는 본 발명의 실시예에 따른 비트라인의 형성 방법을 도시한 도면.
2A to 2D illustrate a method of forming a bit line according to an exemplary embodiment of the present invention.

*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

31 : 반도체기판 32 : 불순물접합층31 semiconductor substrate 32 impurity bonding layer

33 : 워드라인절연막 34 : 식각방지용 질화막33: word line insulating film 34: etching prevention nitride film

35 : 비트라인절연막 36 : 듀얼 다마신 마스크35: bit line insulating film 36: dual damascene mask

38 : 질화막스페이서 39 : 금속확산방지막38 nitride film spacer 39 metal diffusion prevention film

40 : 비트라인배선막 41 : 비트라인보호용 질화막
40: bit line wiring film 41: bit line protection nitride film

본 발명은 반도체소자의 제조 방법에 관한 것으로, 특히 듀얼 다마신 공정을 이용한 비트라인의 형성 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a bit line using a dual damascene process.

일반적으로, 비트라인 형성 방법은 폴리실리콘(Polysilicon), 텅스텐실리사이드(W-Silicide), 캡핑물질(Capping material)로 디자인룰(Design rule)에 따라 마스크산화막(Mask oxide) 또는 마스크질화막(Mask nitride)을 증착하고 이를 패터닝하므로써 형성하는데, 폴리실리콘과 텅스텐실리사이드의 비저항이 소자 집적도 가 증가함에 따른 요구를 충족시키지 못하는 문제점이 발생하여 이를 해결하기 위해 금속배선막을 도입하였다.In general, the bit line forming method is made of polysilicon, tungsten silicide, and capping material, according to a design rule of mask oxide or mask nitride. It is formed by depositing and patterning it, and the metal resistive film is introduced to solve the problem that the specific resistance of polysilicon and tungsten silicide does not meet the requirements of increased device integration.

도 1a 내지 도 1d는 종래기술에 따른 비트라인 형성 방법을 도시한 도면이다.1A to 1D are diagrams illustrating a bit line forming method according to the prior art.

먼저 워드라인(도시 생략), 불순물접합층(12) 등 소정공정이 완료된 반도체기판(11)상에 워드라인절연막(13)을 증착한후, 상기 워드라인절연막(13)을 선택적으로 패터닝하여 상기 불순물접합층(12)이 노출되는 플러그용 콘택홀을 형성하고, 상기 콘택홀을 매립하는 비트라인 플러그(14)를 형성한다.First, a word line insulating layer 13 is deposited on a semiconductor substrate 11 on which a predetermined process such as a word line (not shown) and an impurity bonding layer 12 is completed, and then the word line insulating layer 13 is selectively patterned to form the word line insulating layer 13. A plug contact hole for exposing the impurity bonding layer 12 is formed, and a bit line plug 14 for filling the contact hole is formed.

이어 후속 텅스텐막 증착시 WF6의 반도체기판(11)과의 반응을 억제하기 위한 확산방지금속막(15)으로서 Ti/TiN을 증착하고, 상기 확산방지금속막(15)상에 금속배선막(16)으로 텅스텐을 증착한다.Subsequently, Ti / TiN is deposited as a diffusion barrier metal layer 15 for suppressing the reaction of the WF 6 with the semiconductor substrate 11 during deposition of a tungsten layer, and a metal interconnection layer on the diffusion barrier metal layer 15 is formed. 16) deposit tungsten.

이어 상기 금속배선막(16)과 후속 마스크질화막의 응력감소를 위해 버퍼층 (17)으로서 USG(Undoped Silicon Glass)막을 증착하고, 상기 버퍼층(17)상에 플라즈마증착법(Plasma Enhanced deposition) 또는 저압증착법(Low Pressure deposition)을 이용하여 마스크질화막(18)을 증착한다.Subsequently, an undoped silicon glass (USG) film is deposited as the buffer layer 17 to reduce the stress of the metallization layer 16 and the subsequent mask nitride layer, and a plasma enhanced deposition method or a low pressure deposition method is performed on the buffer layer 17. The mask nitride film 18 is deposited using low pressure deposition.

도 1b에 도시된 바와 같이, 비트라인 마스크를 이용하여 상기 마스크질화막 (18), 버퍼층(17), 금속배선막(16) 및 확산방지금속막(15)을 식각하여 비트라인을 형성하는데, 이 때, 웨이퍼모서리지역에 잔류할 수 있는 금속배선막으로 인한 결함 발생을 억제하기 위해 먼저 WEE(Wafer Edge Exposure)마스크(19)를 이용하여 웨이퍼모서리지역의 비트라인 형성을 위한 상기 마스크질화막(18), 버퍼층(17), 금속배선막 (15) 및 확산방지금속막(15)을 제거한다.As shown in FIG. 1B, the mask nitride layer 18, the buffer layer 17, the metallization layer 16, and the diffusion barrier metal layer 15 are etched using a bit line mask to form a bit line. At this time, the mask nitride film 18 for forming bit lines in the wafer edge region by using a wafer edge exposure (WEE) mask 19 in order to suppress the occurrence of defects due to the metal wiring film that may remain in the wafer edge region. The buffer layer 17, the metallization film 15 and the diffusion barrier metal film 15 are removed.

도 1c에 도시된 바와 같이, 상기 웨이퍼모서리지역의 비트라인 형성막들을 제거한 다음, 비트라인 마스크를 이용하여 비트라인(19)을 패터닝한 후, 상기 비트라인의 측벽에 접하는 비트라인 측벽스페이서(20)를 형성한다. 이어 상기 구조 전면에 비트라인절연막(21)으로 저온 USG막을 증착하면, WEE마스크와 비트라인 마스크 공정에서 중복되어 오픈되었던 지역(22)에서 비트라인절연막(21)이 얇게 증착된다. 즉, 비트라인절연막(21)으로 저온 USG막중에서 상대적으로 갭필(Gapfill)특성이 우수한 고밀도플라즈마산화막(High Density Plasma oxide)을 증착하면, 증착 및 식각하는 증착메카니즘상 웨이퍼모서리에 인접한 비트라인 모서리 부분의 증착두께가 얇게 된다.As shown in FIG. 1C, after removing the bit line forming films of the wafer edge region, patterning the bit line 19 using a bit line mask, the bit line sidewall spacer 20 in contact with the sidewall of the bit line. ). Subsequently, when the low-temperature USG film is deposited on the entire surface of the structure using the bit line insulating film 21, the bit line insulating film 21 is thinly deposited in the region 22 that is overlapped and opened in the WEE mask and the bit line mask process. That is, when the high density plasma oxide film having excellent gapfill characteristics is deposited in the low temperature USG film with the bit line insulating film 21, the bit line edge portion adjacent to the wafer edge is deposited and etched. The deposition thickness of the film becomes thin.

도 1d에 도시된 바와 같이, 상기 비트라인절연막(21)을 비트라인 마스크질화막(18) 상부에 2000Å만큼 잔류시키는 타겟으로 화학적기계적연마할 경우, 즉 비트라인 절연막(21)의 화학적기계적연마(Chemical Mechanical Polishing; CMP)공정에서 메인셀(Main cell)지역의 마스크질화막(18) 상부의 절연막 두께를 2000Å으로 조절하면 모서리 지역의 마스크질화막(18)까지 손실되게 되며(23), 이로 인해 후속 캐패시터 공정에서 열응집(Thermal budget)으로 인해 비트라인배선금속막인 텅스텐이 리프팅 (Lifting)되는 문제점이 있다.
As shown in FIG. 1D, when the bit line insulating layer 21 is chemically mechanically polished to a target for remaining 2000 μs on the bit line mask nitride layer 18, that is, the chemical mechanical polishing of the bit line insulating layer 21 is performed. In the mechanical polishing (CMP) process, if the thickness of the insulating film on the mask nitride film 18 in the main cell region is adjusted to 2000Å, the mask nitride film 18 in the corner region is lost (23). Due to the thermal budget, there is a problem in that tungsten, a bit line wiring metal film, is lifted.

본 발명은 상기 종래기술의 문제점을 해결하기 위해 안출한 것으로서, 듀얼 마다신공정을 이용하여 비트라인콘택 및 배선을 형성하므로써 비트라인용 마스크질화막의 손실 및 비트라인배선의 리프팅현상을 방지하는데 적합한 비트라인의 형성 방법을 제공함에 그 목적이 있다.
The present invention has been made to solve the problems of the prior art, a bit line suitable for preventing the loss of the bit line mask and the lifting phenomenon of the bit line wiring by forming a bit line contact and wiring using a dual mad process Its purpose is to provide a method of forming a.

상기의 목적을 달성하기 위한 본 발명의 비트라인의 형성 방법은 불순물접합층과 워드라인이 형성된 반도체소자의 제조 방법에 있어서, 상기 워드라인상에 제 1 절연막을 형성한후, 후속 듀얼다마신 식각시 상기 제 1 절연막의 손실을 방지하기 위한 질화막과 비트라인용 제 2 절연막을 순차적으로 형성하는 제 1 단계; 듀얼 다마신 마스크를 이용하여 상기 제 2 절연막, 절연막손실방지용 질화막 및 제 1 절연막을 식각하여 상기 불순물접합층이 노출되는 비트라인용 콘택홀을 형성하는 제 2 단계; 상기 제 2 단계의 결과물 전면에 측벽용 질화막을 형성한후, 전면식각하여 상기 제 2 절연막의 내벽에 접하는 스페이서를 형성하는 제 3 단계; 상기 제 3 단계의 결과물상에 확산방지막, 비트라인용 배선막을 순차적으로 형성한후, 상기 비 트라인용 배선막을 전면식각하여 상기 콘택홀 내부로 소정깊이만큼 리세스시키는 제 4 단계; 및 상기 리세스된 배선막상에 상기 배선막 보호용 질화막을 형성한후, 상기 제 2 절연막이 드러날때까지 상기 배선막 보호용 질화막을 화학적기계적연마하여 비트라인을 형성하는 제 5 단계를 포함하여 이루어짐을 특징으로 한다.The method of forming a bit line of the present invention for achieving the above object is a method of manufacturing a semiconductor device in which an impurity junction layer and a word line are formed, and after the first insulating film is formed on the word line, subsequent dual damascene etching A first step of sequentially forming a nitride film and a second insulating film for bit lines to prevent loss of the first insulating film during the process; Etching a second insulating film, an insulating film loss preventing nitride film, and a first insulating film by using a dual damascene mask to form a bit line contact hole through which the impurity bonding layer is exposed; A third step of forming a spacer in contact with an inner wall of the second insulating layer after forming a nitride film for the sidewall on the entire surface of the resultant of the second step; A fourth step of sequentially forming a diffusion barrier film and a bit line wiring film on the resultant of the third step, and then etching the bit line wiring film by etching the entire surface of the bit line to recess a predetermined depth into the contact hole; And a fifth step of forming a bit line by chemically mechanically polishing the wiring film protection nitride film until the second insulating film is formed after forming the wiring film protection nitride film on the recessed wiring film. It is done.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

도 2a 내지 도 2d는 본 발명의 실시예에 따른 듀얼 다마신 공정을 이용한 비트라인 형성 방법을 도시한 도면이다.2A to 2D illustrate a method of forming a bit line using a dual damascene process according to an exemplary embodiment of the present invention.

도 2a에 도시된 바와 같이, 워드라인(도시 생략), 불순물접합층(32)을 포함한 소정공정이 완료된 반도체기판(31)상에 워드라인절연막(33)을 형성한후, 후속 듀얼다마신(Dual damascene) 식각시 워드라인절연막(33)의 손실을 방지하기 위한 질화막(34)으로 SixNy,(x:y=1:1∼5:1), SiON 또는 Si-rich 질화막을 저압(LP) 또는 플라즈마(PE) 방법으로 400∼800℃에서 100Å∼500Å두께로 증착한다.As shown in FIG. 2A, a word line insulating film 33 is formed on a semiconductor substrate 31 on which a predetermined process including a word line (not shown) and an impurity bonding layer 32 is completed, followed by subsequent dual damascene ( Dual damascene) is a nitride film 34 for preventing the loss of the word line insulating film 33 during etching, and low pressure (Si x N y , (x: y = 1: 1-5: 1), SiON or Si-rich nitride film LP) or plasma (PE) method to deposit a thickness of 100 Pa to 500 Pa at 400 to 800 ° C.

이어 상기 질화막(34)상에 비트라인절연막(35)으로 BPSG(Boro Phospho Silicate Glass), PSG(Phosphorous Silicate Glass), FSG(Fluorine Silicate Glass), PETEOS(Plasma Enhanced Tetra Etyl Ortho Silicate), PE-SiH4, HDP USG(High Density Plasma Undoped Silicon Glass), HDP PSG 또는 APL(Advanced Planarization Layer) 산화막 중 어느 하나의 절연막을 3000Å∼10000Å두께로 증 착한다.Subsequently, BPSG (Boro Phospho Silicate Glass), PSG (Phosphorous Silicate Glass), FSG (Fluorine Silicate Glass), PETEOS (Plasma Enhanced Tetra Etyl Ortho Silicate), and PE-SiH on the nitride film 34. 4 , an insulating film of any one of HDP USG (High Density Plasma Undoped Silicon Glass), HDP PSG, or APL (Advanced Planarization Layer) oxide film is deposited to a thickness of 3000 kV to 10,000 kPa.

이어 상기 비트라인절연막(35)을 300℃∼1000℃에서 열처리한 다음, 상기 비트라인절연막(35)상에 감광막을 도포하고 노광 및 현상으로 패터닝한후, 상기 패터닝된 감광막(36)을 마스크로 하여 상기 비트라인절연막(35)을 식각한다. 이어 듀얼다마신마스크(Dual damascene mask)를 이용하여 상기 비트라인절연막(35) 하부의 질화막(34) 및 워드라인절연막(33)을 식각하여 비트라인콘택 및 비트라인배선을 위한 콘택홀(37)을 형성한다.Subsequently, the bit line insulating layer 35 is heat-treated at 300 ° C. to 1000 ° C., and then a photosensitive layer is coated on the bit line insulating layer 35, and patterned by exposure and development. The bit line insulating layer 35 is etched. Subsequently, the nitride layer 34 and the word line insulating layer 33 under the bit line insulating layer 35 are etched using a dual damascene mask to form a contact hole 37 for bit line contact and bit line wiring. To form.

도 2b에 도시된 바와 같이, 상기 패터닝된 감광막(36)을 제거한 다음, 상기 노출된 비트라인절연막(35)을 포함한 전면에 측벽용 질화막으로서 SixNy(x:y=1:1∼5:1), Si-rich 질화막 중 어느 하나를 저압(LP)법으로 400℃∼1000℃에서 300Å∼600Å두께로 증착한 다음, 전면식각하여 상기 비트라인절연막(35)의 측벽에 접하는 질화막스페이서(38)를 형성한다.As shown in FIG. 2B, the patterned photoresist layer 36 is removed, and then Si x N y (x: y = 1: 1 to 5 is formed on the entire surface including the exposed bit line insulating layer 35 as a nitride film for sidewalls. (1) A nitride film spacer is deposited on any one of the Si-rich nitride films at a low pressure (LP) method at 400 ° C. to 1000 ° C. at a temperature of 400 ° C. to 1000 ° C., and is then etched to be in contact with the sidewall of the bit line insulating film 35. 38).

이어 상기 질화막스페이서(38)를 포함한 전면에 금속확산방지막(39)으로서 Ti, TiN, TiSi, WN, TaN, TiSiN 또는 TiAlN 중 어느 하나의 도전층을 화학적기상증착법(Chemical Vapor Deposition; CVD) 또는 스퍼터링(Sputtering)법을 이용하여 300℃∼600℃에서 100Å∼1000Å두께로 증착하거나, 또는 상기 도전층들을 조합하여 증착한다.Subsequently, any one of the conductive layers of Ti, TiN, TiSi, WN, TaN, TiSiN or TiAlN as the metal diffusion barrier 39 on the entire surface including the nitride film spacer 38 is deposited or deposited by chemical vapor deposition (CVD) or sputtering. It is deposited at a thickness of 100 kV to 1000 kV at 300 ° C to 600 ° C by using the Sputtering method, or a combination of the above conductive layers is deposited.

이어 상기 금속확산방지막(39)상에 비트라인배선막(40)으로서 텅스텐(W) 또는 구리(Cu) 중 어느 하나의 금속을 화학적기상증착법(CVD) 또는 스퍼터링 (Sputtering)을 이용하여 300℃∼600℃에서 500Å∼2000Å두께로 증착한다. Subsequently, a metal of any one of tungsten (W) or copper (Cu) is used as a bit line wiring film 40 on the metal diffusion barrier film 39 by chemical vapor deposition (CVD) or sputtering. It deposits at 500 degreeC-2000 mm thickness at 600 degreeC.                     

도 2c에 도시된 바와 같이, Cl2, BCl3, CCl4 등의 클로린(Chlorine)계 식각제를 이용하여 상기 비트라인배선막(40)을 전면식각하여 상기 비트라인배선 내부로 500Å∼2000Å깊이로 리세스한다. 이후, 선택적으로 비트라인배선막(40)의 부식을 억제하기 위해 식각후 챔버에서 플루오린(Fluorine)으로 클로린(Chlorine)을 대치하는 보호막공정을 진행할 수 있다. 또한, 소자에 따라 선택적으로 비트라인배선막 (40)과 후속 마스크질화막간 응력 발생을 억제하기 위한 버퍼층으로서 PETEOS, PESiH4와 같은 USG막을 300℃∼800℃에서 300Å∼1000Å두께로 증착할 수 있다.As shown in FIG. 2C, the bit line interconnection film 40 is etched entirely using a chlorine-based etching agent such as Cl 2 , BCl 3 , CCl 4, etc., and is 500 Å to 2000 Å deep into the bit line wiring. Recess to Thereafter, in order to suppress corrosion of the bit line interconnection film 40, a protective film process may be performed to replace chlorine with fluorine in the chamber after etching. Further, depending on the device, USG films such as PETEOS and PESiH 4 can be deposited at 300 占 Å to 1000 占 Å at 300 占 폚 to 800 占 폚 as a buffer layer for suppressing the stress generation between the bit line interconnect film 40 and the subsequent mask nitride film. .

이어 상기 리세스된 비트라인배선막(40)을 포함한 전면에 비트라인배선막 보호용 마스크질화막(41)으로서 SixNy(x:y=1:1∼5:1), SiON, Si-rich 질화막 중 어느 하나의 절연막을 저압(PE) 또는 플라즈마(PE) 방법으로 400℃∼800℃에서 500Å∼2000Å두께로 증착한다.Subsequently, as the mask nitride film 41 for protecting the bit line wiring film on the entire surface including the recessed bit line wiring film 40, Si x N y (x: y = 1: 1 to 5: 1), SiON, and Si-rich. An insulating film of any one of the nitride films is deposited at a low pressure (PE) or plasma (PE) method at a thickness of 500 Pa to 2000 Pa at 400 ° C to 800 ° C.

도 2d에 도시된 바와 같이, 비트라인절연막(35)이 드러날때까지 상기 비트라인배선막 보호용 마스크질화막(41)을 화학적기계적연마(CMP)하거나 또는 연마특성을 향상시키기 위해 부분적으로 에치백(Etchback)한 후 화학적기계적연마하여 비트라인배선을 형성한다. 이 때, 상기 화학적기계적연마시 50nm∼300nm크기의 실리카, 알루미나, 세리아와 같은 연마제가 첨가된 pH 8∼11로 유지되는 슬러리 (Slurry)를 이용하거나, 또는 균일도 특성을 향상시키기 위해 마스크질화막(41)을 증착두께의 50%∼80% 타겟으로 부분식각한 다음, 화학적기계적연마한다.As shown in FIG. 2D, the bit-line wiring layer protective mask nitride layer 41 is chemically mechanically polished (CMP) or partially etched back until the bit line insulating layer 35 is exposed. After chemical mechanical polishing, bit line wiring is formed. At this time, the mask nitride film 41 to maintain a uniformity characteristics, or to use a slurry maintained at a pH of 8 to 11 to which abrasives such as silica, alumina, and ceria of 50 nm to 300 nm size are added during chemical mechanical polishing ) Is partially etched into a 50% to 80% target of the deposition thickness, followed by chemical mechanical polishing.

상기한 바와 같이, 마스크질화막(41)을 화학적기계적연마하여 비트라인콘택 및 비트라인배선을 형성하므로써 안정된 두께의 마스크질화막을 확보할 수 있고, 이에 따라 비트라인 배선의 리프팅을 방지한다.As described above, the mask nitride film 41 is chemically mechanically polished to form bit line contacts and bit line wirings, thereby ensuring a stable mask nitride film, thereby preventing lifting of the bit line wirings.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.
Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

상술한 바와 같이, 본 발명의 비트라인 형성 방법은 듀얼다마신공정을 이용하여 비트라인콘택 및 배선을 형성하므로써, 비트라인절연막을 평탄화함에 따른 비트라인배선의 리프팅을 근본적으로 방지할 수 있고, 비트라인배선의 리프팅을 방지하기 위한 별도의 질화막을 증착할 필요가 없으므로 공정을 단순화시킬 수 있는 효과가 있다.As described above, the bit line forming method of the present invention can prevent the lifting of the bit line wiring by planarizing the bit line insulating film by forming the bit line contact and wiring by using the dual damascene process, Since there is no need to deposit a separate nitride film to prevent the lifting of the wiring, there is an effect that can simplify the process.

Claims (14)

불순물접합층과 워드라인이 형성된 반도체소자의 제조 방법에 있어서,In the method of manufacturing a semiconductor device having an impurity junction layer and a word line, 상기 워드라인상에 제 1 절연막을 형성한후, 후속 듀얼다마신 식각시 상기 제 1 절연막의 손실을 방지하기 위한 질화막과 비트라인용 제 2 절연막을 순차적으로 형성하는 제 1 단계;Forming a first insulating film on the word line, and subsequently forming a nitride film and a second insulating film for bit lines to prevent loss of the first insulating film during subsequent dual damascene etching; 듀얼 다마신 마스크를 이용하여 상기 제 2 절연막, 절연막손실방지용 질화막 및 제 1 절연막을 식각하여 상기 불순물접합층이 노출되는 비트라인용 콘택홀을 형성하는 제 2 단계;Etching a second insulating film, an insulating film loss preventing nitride film, and a first insulating film by using a dual damascene mask to form a bit line contact hole through which the impurity bonding layer is exposed; 상기 제 2 단계의 결과물 전면에 측벽용 질화막을 형성한후, 전면식각하여 상기 제 2 절연막의 내벽에 접하는 스페이서를 형성하는 제 3 단계;A third step of forming a spacer in contact with an inner wall of the second insulating layer after forming a nitride film for the sidewall on the entire surface of the resultant of the second step; 상기 제 3 단계의 결과물상에 확산방지막, 비트라인용 배선막을 순차적으로 형성한후, 상기 비트라인용 배선막을 전면식각하여 상기 콘택홀 내부로 소정깊이만큼 리세스시키는 제 4 단계; 및A fourth step of sequentially forming a diffusion barrier film and a bit line wiring film on the resultant of the third step, and then etching the bit line wiring film over the entire surface to recess the predetermined depth into the contact hole; And 상기 리세스된 배선막상에 상기 배선막 보호용 질화막을 형성한후, 상기 제 2 절연막이 드러날때까지 상기 배선막 보호용 질화막을 화학적기계적연마하여 비트라인을 형성하는 제 5 단계A fifth step of forming a bit line by chemically mechanically polishing the wiring film protection nitride film until the second insulating film is exposed after forming the wiring film protection nitride film on the recessed wiring film 를 포함하여 이루어짐을 특징으로 하는 비트라인의 형성 방법.Bit line forming method characterized in that it comprises a. 제 1 항에 있어서,The method of claim 1, 상기 제 1 절연막의 손실을 방지하기 위한 질화막은 SixNy(x:y=1:1∼5:1), SiON 또는 Si-rich 질화막 중 어느 하나를 저압 또는 플라즈마 증착법 중 어느 하나의 증착법을 이용하여 400∼800℃에서 100Å∼500Å 두께로 증착하는 것을 특징으로 하는 비트라인의 형성 방법.The nitride film for preventing the loss of the first insulating film is any one of Si x N y (x: y = 1: 1 to 5: 1), SiON or Si-rich nitride film by low pressure or plasma deposition. A method of forming a bit line, which is deposited at 400 to 800 占 Å at a thickness of 100 to 500 Å. 제 1 항에 있어서,The method of claim 1, 상기 비트라인용 제 2 절연막은 BPSG, PSG, FSG, PETEOS, PE-SiH4, HDP USG, HDP PSG 또는 APL 산화막 중 어느 하나의 절연막을 이용하며, 3000Å∼10000Å두께로 증착되는 것을 특징으로 하는 비트라인의 형성 방법.The second insulating film for the bit line is any one of an insulating film of BPSG, PSG, FSG, PETEOS, PE-SiH 4 , HDP USG, HDP PSG or APL oxide film, characterized in that the bit is deposited to 3000 ~ 10000Å thickness How to form a line. 제 1 항에 있어서,The method of claim 1, 상기 제 1 단계에서,In the first step, 상기 제 2 절연막 형성후, 300℃∼1000℃에서 열처리하는 것을 특징으로 하는 비트라인의 형성 방법.And forming the second insulating film, followed by heat treatment at 300 ° C to 1000 ° C. 제 1 항에 있어서,The method of claim 1, 상기 측벽용 질화막은 SixNy(x:y=1:1∼5:1), Si-rich 질화막 중 어느 하나를 저압증착법을 이용하여 400℃∼1000℃에서 300Å∼600Å두께로 증착하는 것을 특징으로 하는 비트라인의 형성 방법.The nitride film for the side wall may be formed by depositing any one of Si x N y (x: y = 1: 1 to 5: 1) and a Si-rich nitride film at a temperature of 300 Pa to 600 Pa using a low pressure deposition method at 400 to 1000 ° C. Characterized in that the formation of the bit line. 제 1 항에 있어서,The method of claim 1, 상기 확산방지막은 Ti, TiN, TiSi, WN, TaN, TiSiN 또는 TiAlN 중 어느 하나의 도전층을 이용하며, 화학적기상증착법 또는 스퍼터링을 이용하여 300℃∼600℃에서 100Å∼1000Å두께로 증착하거나, 또는 상기 도전층들을 조합하여 증착하는 것을 특징으로 하는 비트라인의 형성 방법.The diffusion barrier layer is any one of a conductive layer of Ti, TiN, TiSi, WN, TaN, TiSiN or TiAlN, and is deposited to a thickness of 100Å to 1000Å at 300 ° C to 600 ° C by chemical vapor deposition or sputtering, or And depositing a combination of the conductive layers. 제 1 항에 있어서,The method of claim 1, 상기 비트라인배선막은 텅스텐 또는 구리 중 어느 하나의 금속을 이용하되, 화학적기상증착법 또는 스퍼터링을 이용하여 300℃∼600℃에서 500Å∼2000Å두께로 증착하는 것을 특징으로 하는 비트라인의 형성 방법.The bit line wiring film may be formed of any one of tungsten or copper, and is deposited using a chemical vapor deposition method or sputtering at 300 ° C. to 600 ° C. at a thickness of 500 kPa to 2000 kPa. 제 1 항에 있어서,The method of claim 1, 상기 제 4 단계는, The fourth step, Cl2, BCl3 또는 CCl4 중 어느 하나의 식각제를 이용하여 상기 비트라인배선막을 전면식각하여 상기 콘택홀 내부로 500Å∼2000Å깊이만큼 리세스시키는 것을 특징으로 하는 비트라인의 형성 방법.A method of forming a bit line, the entire etching of the bit line wiring layer using an etchant of Cl 2 , BCl 3 or CCl 4 to recess 500 Å to 2000 Å deep into the contact hole. 제 1 항 또는 제 8 항에 있어서,The method according to claim 1 or 8, 상기 제 4 단계후, 선택적으로 상기 비트라인배선막의 부식을 억제하기 위해 전면식각후 챔버에서 플루오린계 가스를 이용한 보호막 공정을 실시하는 단계를 포함하여 이루어짐을 특징으로 하는 비트라인의 형성 방법.And after the fourth step, selectively performing a protective film process using a fluorine-based gas in the chamber after the front surface etching to inhibit corrosion of the bit line interconnection film. 제 1 항 또는 제 8 항에 있어서,The method according to claim 1 or 8, 상기 제 4 단계후, 선택적으로 상기 비트라인배선막과 후속 배선막 보호용 질화막간 응력 발생을 억제하기 위한 버퍼층으로서 PETEOS, PESiH4와 같은 USG막을 300℃∼800℃에서 300Å∼1000Å두께로 증착하는 단계를 포함하여 이루어짐을 특징으로 하는 비트라인의 형성 방법.After the fourth step, selectively depositing a USG film such as PETEOS and PESiH 4 at 300 DEG C to 800 DEG C at 300 DEG C to 800 DEG C as a buffer layer for suppressing stress generation between the bit line wiring film and the subsequent nitride film for protecting the wiring film. Bit line forming method characterized in that it comprises a. 제 1 항에 있어서,The method of claim 1, 상기 비트라인배선막 보호용 질화막은 SixNy(x:y=1:1∼5:1), SiON, Si-rich 질화막 중 어느 하나의 절연막을 이용하되, 저압 또는 플라즈마증착법 중 어느 하나의 증착법을 이용하여 400℃∼800℃에서 500Å∼2000Å두께로 증착하는 것을 특징으로 하는 비트라인의 형성 방법.The bit line wiring layer protective nitride film may be formed using any one of Si x N y (x: y = 1: 1 to 5: 1), SiON, and Si-rich nitride films, and any one of low pressure and plasma deposition methods. A method for forming a bit line, which is deposited at a thickness of 500 Pa to 2000 Pa at 400 ° C to 800 ° C. 제 1 항에 있어서,The method of claim 1, 상기 제 5 단계는,The fifth step, 상기 배선막보호용 질화막을 화학적기계적연마하기 전에,Before chemical mechanical polishing of the wiring film protective nitride film, 상기 배선막보호용 질화막의 연마특성을 향상시키기 위해 부분적으로 에치백하는 단계를 포함하여 이루어짐을 특징으로 하는 비트라인의 형성 방법.And partially etching back to improve polishing characteristics of the nitride film for protecting the wiring film. 제 1 항에 있어서,The method of claim 1, 상기 제 5 단계에서,In the fifth step, 상기 화학적기계적연마시 50nm∼300nm크기의 실리카, 알루미나 또는 세리아가 첨가된 pH 8∼11로 유지되는 슬러리를 이용하는 것을 특징으로 하는 비트라인의 형성 방법.And a slurry maintained at a pH of 8 to 11 to which silica, alumina or ceria having a size of 50 nm to 300 nm is added during chemical mechanical polishing. 제 1 항 또는 제 12 항에 있어서,The method of claim 1 or 12, 상기 화학적기계적연마전에 상기 배선막보호용 질화막을 그 증착두께의 50%∼80% 타겟으로 부분식각하는 것을 특징으로 하는 비트라인의 형성 방법.And etching the wiring film protective nitride film to a 50% to 80% target of the deposition thickness before the chemical mechanical polishing.
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KR19990048154A (en) * 1997-12-08 1999-07-05 윤종용 Semiconductor device having damascene bit line and manufacturing method thereof
KR19990053190A (en) * 1997-12-23 1999-07-15 윤종용 Manufacturing Method of Semiconductor Device for Bit Line Capping of Ultra Fine Line Width
KR20000027544A (en) * 1998-10-28 2000-05-15 김영환 Method for manufacturing semiconductor element
US6071804A (en) * 1998-09-19 2000-06-06 United Semiconductor Corp. Method of fabricating bit lines by damascene

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19990048154A (en) * 1997-12-08 1999-07-05 윤종용 Semiconductor device having damascene bit line and manufacturing method thereof
KR19990053190A (en) * 1997-12-23 1999-07-15 윤종용 Manufacturing Method of Semiconductor Device for Bit Line Capping of Ultra Fine Line Width
US6071804A (en) * 1998-09-19 2000-06-06 United Semiconductor Corp. Method of fabricating bit lines by damascene
KR20000027544A (en) * 1998-10-28 2000-05-15 김영환 Method for manufacturing semiconductor element

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