JP3677755B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a wiring technique in a semiconductor device, and more particularly to a semiconductor device having a wiring structure suitable for high integration and a method for manufacturing the same.
[0002]
[Prior art]
As LSIs become larger, device miniaturization is being pursued.
In order to realize a semiconductor integrated circuit having gates, wirings, and contact holes with finer dimensions, conventionally, the exposure wavelength in photolithography has been shortened to improve the resolution.
[0003]
Various device structures that reduce the alignment margin between lithography processes while reducing the minimum resolution size in this way have been studied, and the device size can be reduced without reducing the size of the pattern to be formed. Has been tried.
Examples of such a device structure include a self-aligned contact (hereinafter referred to as SAC) or a borderless contact (hereinafter referred to as BLC).
[0004]
A conventional SAC structure will be described in comparison with a case where no SAC structure is used.
As shown in FIG. 30A, in the case where two gate electrodes 40 are formed on the semiconductor substrate 10 and the interlayer insulating film 20 is formed thereon, the two gate electrodes 40 are connected to each other. When the contact hole 22 is opened to the semiconductor substrate 10 through the gap, it is necessary to previously arrange the gate electrode 40 in consideration of the alignment accuracy when the contact hole 22 is opened.
[0005]
That is, the gap a between the contact hole 22 and the gate electrode 40 must be at least more than the alignment accuracy so that the conductive film and the gate electrode 40 are not short-circuited when the conductive film is embedded in the contact hole 22 ( FIG. 30 (b)). Therefore, the distance between the gate electrodes 40 is affected by the contact hole 22, and further miniaturization becomes difficult.
[0006]
On the other hand, in the case of the SAC structure, as shown in FIG. 30C, the gate electrode 40 is covered with an interlayer insulating film 20 and an insulating film 38 having etching selectivity. Therefore, when the interlayer insulating film 20 is etched, the insulating film 38 is not etched, and the conductive film and the gate electrode 40 are not short-circuited even when the conductive film is buried in the contact hole 22.
[0007]
Therefore, even when a positional shift occurs in the lithography process for forming the contact hole 22, the opening of the semiconductor substrate 10 is determined only by the gate electrode 40 and the insulating film 38, so that as shown in FIG. The gate electrode 40 and the contact hole 22 can be arranged without considering the alignment. Thereby, the element can be miniaturized.
[0008]
The SAC structure is disclosed in, for example, Japanese Patent Laid-Open Nos. 61-292323, 4-106929, '94 Symp. VLSI Tech., Tech. Dig., Pp. 99-100.
Next, a conventional BLC structure will be described in comparison with a case where no BLC structure is used.
[0009]
As shown in FIG. 31A, when the element isolation film 12 is formed on the semiconductor substrate 10 and the interlayer insulating film 20 is formed thereon, a contact hole 22 is formed in the vicinity of the element isolation film 12. In the case of opening, the contact hole 22 and the element isolation film 12 must be separated so that the contact hole 22 is not positioned on the element isolation film 12 even when a positional shift occurs.
[0010]
That is, when the contact hole 22 is located on the element isolation film, the element isolation film 12 is etched in the etching when the contact hole 22 is opened, and the conductive film 24 is embedded when the conductive film is embedded in the contact hole 22. This is because a short-circuit occurs between the semiconductor substrate 10 and the semiconductor substrate 10 (FIG. 31B).
On the other hand, in the case of the BLC structure, as shown in FIG. 31C, the interlayer insulating film 20 is formed by the insulating films 16 and 18 having different etching selectivity. At this time, if a material with sufficient etching selectivity for the insulating film 16 in contact with the element isolation film 12 is selected for the element isolation film 12, the element isolation is performed even when the contact hole 22 is opened to the surface of the semiconductor substrate 10. Since the film 12 is not etched, a junction short circuit between the conductive film embedded in the contact hole 22 and the semiconductor substrate 10 can be prevented.
[0011]
Therefore, if the BLC structure is used, a junction short circuit can be prevented even when the element isolation film 12 and the contact hole 22 overlap with each other. Therefore, there is no need to consider the alignment margin between the element isolation film 12 and the contact hole 22. The contact hole 22 can be disposed as shown in FIG. Thereby, the element can be miniaturized.
[0012]
[Problems to be solved by the invention]
However, the conventional semiconductor device using the BLC structure has the following problems.
That is, when etching the insulating film 16, it is desirable to use wet etching in order to obtain a selection ratio with the element isolation film 12, but wet etching for removing the insulating film 16 is isotropic etching. Etching is performed up to the insulating film 16 below the insulating film 18 to form holes 30 (FIG. 32A). Since the holes 30 thus formed cannot be covered by the conventional sputtering method, they remain even after the conductive film 24 is deposited (FIG. 32B). For this reason, when the plug 26 is formed by using the W filling method in the subsequent contact formation process, the source gas WF is used. ₆ Intruded from the hole portion, substrate erosion called wormhole occurred, and junction breakdown occurred in the source / drain diffusion layer 14 (FIG. 32 (c)).
[0013]
In addition, when Al (aluminum) deposited by CVD instead of the W plug is used as a wiring material, Al and the semiconductor substrate are in direct contact within the holes 30, so that heat treatment in a later process is performed. As a result, the Al and the semiconductor substrate may react to cause a junction breakdown in the source / drain diffusion layer 14 (FIG. 33A).
[0014]
The same was true when Cu was used as the wiring material. In particular, in the case of Cu, when it diffuses into a semiconductor substrate, a deep level is formed, so that the transistor characteristics may be significantly deteriorated. Further, since Cu easily diffuses in the silicon oxide film, when Cu reaches the gate oxide film 34, the leakage current between the gate electrode 40 and the semiconductor substrate 10 may increase (FIG. 33B).
[0015]
Also, as shown in FIG. 34, in a semiconductor device having a wiring 210 connected to a contact plug 208 embedded in an interlayer insulating film 202 on a semiconductor substrate 200, a BLC structure is formed when a via hole connected to the wiring 210 is opened. When the insulating film 220 is etched up to the top of the etching stopper film 216 immediately above the interlayer insulating film 208 due to misalignment or the like at the time of opening the via hole, voids formed when the etching stopper film 216 is etched. The contact plug 208 is exposed in the 224, and the contact plug 230 and the contact plug 208 may be short-circuited.
[0016]
Further, when the etching stopper film 112 is removed without forming the holes 124 by using anisotropic reactive ion etching, it is difficult to ensure selectivity with respect to the base film.
That is, in the structure shown in FIG. 35A, if the etching stopper film 112 in the wiring trench 118 is etched under a condition that can ensure a sufficient selection ratio with respect to the interlayer insulating film 104, the contact plug 110 is sufficient. As a result, the contact plug 110 may be etched (FIG. 35B).
[0017]
On the contrary, if the etching stopper film 112 is etched under a condition that can secure a sufficient selection ratio with respect to the contact plug 110, a sufficient selection ratio with respect to the interlayer insulating film 104 cannot be ensured. The insulating film 104 may be etched (FIG. 35C).
As described above, in the etching of the etching stopper film 112, it is difficult to ensure the etching selectivity for the contact plug 110 and the interlayer insulating film 104 at the same time, which affects the reliability of the semiconductor device such as deterioration of contact characteristics. There was a thing.
[0018]
Further, when the BLC structure is applied when forming the contact plug 144 on the wiring 122 formed by being embedded in the interlayer insulating film 114, the conductive film is formed in the hole 138 formed by the recession of the etching stopper film 130. Since the wiring 122 is exposed even after the 140 is formed, the material gas of the plug 142 reacts with the wiring 122 when the plug 142 is embedded, and a high resistance reactant 146 may be formed. For this reason, the contact characteristics between the contact plug 144 and the wiring 122 may be deteriorated (FIG. 36).
[0019]
Further, in the process of detailed examination by the inventors of the present application, a new problem that has not been known has been found.
That is, for example, as shown in FIG. 37A, in the case of the SAC structure in which the position of the gate electrode 40 and the contact hole 22 overlaps and there is a step in the contact hole 22, the insulating film 16 made of SiN film and It has been found that when the contact hole 22 is opened in the interlayer insulating film 20 made of the insulating film 18, the SiN film is easily worn out at the shoulder portion of the step when the insulating film 18 is etched. As a result, when the SiN film depleted by the conventional method is removed, as shown by the dotted line in FIG. 37 (a), the insulating film 38 directly under the SiN film is etched, and the gate electrode 40 may be exposed. .
[0020]
Further, in order to suppress the above-described depletion of the SiN film, when the selection ratio between the SiN film and the oxide film is increased by etching using phosphoric acid or fluorine radicals, the insulating film 16 is formed as shown in FIG. Etching in the lateral direction proceeds and holes 30 are formed. Thereafter, when the conductive film 24 is deposited, the conductive film 24 is not deposited in the pores 30. Therefore, when the W filling method is used in the subsequent contact formation process, WF which is a source gas is used. ₆ May intrude through the hole 30 and a wormhole may occur, causing a breakdown of the junction at the source / drain diffusion layer 14.
[0021]
Even when salicide is formed on the source / drain diffusion layer 14, since the semiconductor substrate 10 is not sufficiently covered by the silicide layer 44 at the edge portion of the element isolation film 12, worm holes are generated from the edge portion. It sometimes occurred and the joint was broken (FIG. 38).
An object of the present invention is to provide a semiconductor device having a SAC structure or a BLC structure that can reduce phenomena affecting the reliability of the semiconductor device, such as junction leakage and short-circuit between wires, and a method for manufacturing the same.
[0022]
[Means for Solving the Problems]
The object is to comprise an underlying substrate, a first insulating film formed on the underlying substrate, and a second insulating film formed on the first insulating film, and an opening reaching the underlying substrate. An interlayer insulating film formed; a conductive film formed on an inner wall and a bottom of the opening; and a buried conductor formed in the opening where the conductive film is formed. The opening width of the opening formed in the insulating film is wider than the opening width of the opening formed in the second insulating film, and the conductive film formed on the inner wall of the opening; The conductive film formed at the bottom of the opening is continuous, and the conductive film forms a region below the second insulating film in the opening formed in the first insulating film. Fill It is achieved by a semiconductor device characterized by being formed as described above. Since the base substrate is not exposed in the opening by configuring the semiconductor device in this manner, when the conductive material is embedded in the opening, the base substrate is eroded by the source gas of the conductive material, or the conductive material and the base are exposed. Reaction with the substrate can be prevented. Thereby, the reliability of the semiconductor device can be improved.
Also, the object is to form an opening reaching the base substrate, comprising a base substrate, a first insulating film formed on the base substrate, and a second insulating film formed on the first insulating film. An interlayer insulating film having a portion formed thereon, a conductive film formed on an inner wall and a bottom portion of the opening, and a buried conductor formed in the opening in which the conductive film is formed, The opening width of the opening formed in the first insulating film is wider than the opening width of the opening formed in the second insulating film, The conductive film is formed so as to completely surround the inside of the opening, This can also be achieved by a semiconductor device in which a hole is formed under the second insulating film in the opening. Since the base substrate is not exposed in the opening by configuring the semiconductor device in this manner, when the conductive material is embedded in the opening, the base substrate is eroded by the source gas of the conductive material, or the conductive material and the base are exposed. Reaction with the substrate can be prevented. Thereby, the reliability of the semiconductor device can be improved.
[0023]
Further, the object is formed on the base substrate that reacts with the source gas of the conductive material, the first insulating film formed on the base substrate, and the first insulating film. The etching characteristics are different from those of the first insulating film. Formed on the second insulating film and the second insulating film; Etching characteristics are the same as the first insulating film An interlayer insulating film having an opening reaching the base substrate, and an opening of the opening. Whole bottom as well as inner wall And an embedded conductor formed using the source gas in the opening where the conductive film is formed, and The first insulating film is thinner than the second insulating film, An opening width of the opening formed in the second insulating film is wider than an opening width of the opening formed in the third insulating film, and the opening formed in the first insulating film. The opening width of the portion is also achieved by a semiconductor device characterized in that it is substantially equal to the opening width of the opening formed in the third insulating film. By configuring the semiconductor device in this manner, the base substrate can be completely isolated from the opening by conductive film formation.
[0025]
In the semiconductor device, it is preferable that the base substrate further includes at least one wiring layer. The semiconductor device according to the present invention can be applied to any wiring layer in a multilayer wiring structure having a plurality of wiring layers.
Further, the above object is to provide a first insulating film deposition step for depositing a first insulating film on a base substrate, and a second insulating film having a different etching characteristic from the first insulating film on the first insulating film. A second insulating film deposition step for depositing the film and anisotropic etching of the second insulating film reach the first insulating film. First A first opening forming step for forming an opening; First By removing the first insulating film in the opening by a method in which etching proceeds also in the lateral direction, First Opening the opening to the base substrate and simultaneously etching the first insulating film under the second insulating film to form a gap To form a second opening A second opening forming step, and Second In order not to expose the base substrate in the opening, Formed on the inner wall and bottom of the second opening, At least of the void The second Aperture Side edge Conductive film Compost A conductive film deposition step to be stacked, and at least the conductive film is formed Second It is also achieved by a method of manufacturing a semiconductor device, characterized by having a buried conductor forming step of forming a buried conductor in the opening. By manufacturing the semiconductor device in this manner, the inside of the opening and the base substrate can be completely isolated by conductive film formation. Thus, when the conductive material is embedded in the opening in a later step, the base substrate is not eroded by the source gas of the conductive material, and the base substrate and the conductive material do not react. Thereby, the reliability of the semiconductor device can be improved.
Further, in the above semiconductor device manufacturing method, in the conductive film deposition step, the gap is removed. Fill As described above, the conductive film may be formed.
In the method for manufacturing a semiconductor device, in the conductive film deposition step, the conductive film may be formed so that holes remain in the gap.
[0026]
In the method for manufacturing a semiconductor device, it is preferable that the conductive film is deposited by a collimated sputtering method in the conductive film deposition step. By depositing a conductive film by a collimated sputtering method, the opening of the gap can be easily closed.
In the method of manufacturing a semiconductor device, in the conductive film deposition step, Second It is desirable that the conductive film is deposited so that the film thickness of the conductive film at the bottom of the opening is thicker than that of the first insulating film. By doing so, the opening of the gap can be easily closed.
[0027]
In the method for manufacturing a semiconductor device, it is preferable that the conductive film is deposited by a CVD method in the conductive film deposition step. By depositing the conductive film by the CVD method, the conductive film can be easily embedded in the gap.
In the method of manufacturing a semiconductor device, in the conductive film deposition step, Second It is desirable to deposit the conductive film so that the film thickness of the conductive film at the bottom of the opening is ½ or more of the film thickness of the first insulating film. By doing so, the opening of the gap can be easily embedded.
[0028]
Further, the object is to deposit a first insulating film on a base substrate that reacts with a source gas of a conductive material, and to form the first insulating film on the first insulating film. Film and etching characteristics But Different Thicker than the first insulating film. A second insulating film deposition step of depositing a second insulating film, and the second insulating film on the second insulating film; 1 Insulation film and etching characteristics Are equal A third insulating film deposition step for depositing a third insulating film; and a first opening for forming an opening reaching the second insulating film by anisotropically etching the third insulating film Forming step and the second insulating film in the opening Isotropically Etchan To A second opening forming step for opening the opening to the top of the first insulating film, and anisotropically etching the first insulating film in the opening to form the opening. A third opening forming step for opening up to the base substrate; ,Previous To cover the base substrate exposed in the opening , On the inner wall and bottom of the opening A semiconductor device comprising: a conductive film deposition step of depositing a conductive film; and a step of forming a buried conductor using the source gas in the opening in which the conductive film is formed. This is also achieved by the manufacturing method. By manufacturing the semiconductor device in this manner, the inside of the opening and the base substrate can be completely isolated by conductive film formation. Accordingly, even when the second insulating film needs to be isotropically etched in order to use the SAC structure, substrate erosion due to the source gas when the conductive material is embedded can be prevented. In addition, the reaction between the conductive material and the base substrate can be prevented.
[0029]
In the method for manufacturing a semiconductor device, it is preferable that in the third opening forming step, an over-etching amount when etching the first insulating film is set to about 50% or less. By manufacturing the semiconductor device in this manner, the opening can be formed while suppressing damage to the base substrate.
In the method for manufacturing a semiconductor device, the base substrate preferably further includes at least one wiring layer. The method for manufacturing a semiconductor device according to the present invention can be applied to any wiring layer in a multilayer wiring structure having a plurality of wiring layers.
[0031]
DETAILED DESCRIPTION OF THE INVENTION
[First Embodiment]
The semiconductor device and the manufacturing method thereof according to the first embodiment of the present invention will be described with reference to FIGS.
FIG. 1 is a schematic cross-sectional view showing the structure of the semiconductor device according to the present embodiment, FIGS. 2 and 3 are process cross-sectional views showing the method for manufacturing the semiconductor device according to the present embodiment, and FIG. FIG. 5 is a view for explaining the effect of the semiconductor device manufacturing method according to the present embodiment.
[0032]
The structure of the semiconductor device according to the present embodiment will be explained with reference to FIG.
An element isolation film 12 that defines an element region is formed on the semiconductor substrate 10, and a diffusion layer 14 is formed in the element region. An interlayer insulating film 20 composed of an etching stopper film 16 and an insulating film 18 is formed on the semiconductor substrate 10, and a contact hole 22 reaching the semiconductor substrate is opened in the interlayer insulating film 20. A conductive film 24 that functions as a barrier metal is formed on the inner wall of the contact hole 22 and the interlayer insulating film 20, and a plug 26 is embedded in the contact hole 22 in which the conductive film 24 is formed. A wiring layer 28 connected to the plug 26 is formed on the interlayer insulating film 20.
[0033]
Here, the semiconductor device according to the present embodiment is characterized in that although the etching stopper film 16 in the vicinity of the contact hole 22 is etched in the lateral direction to form the void 30, the conductive film formed in the contact hole 22. Reference numeral 24 denotes that the hole 30 is not interrupted and is formed so as to completely surround the inside of the contact hole.
[0034]
Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS.
First, an insulating film to be an etching stopper film 16 is deposited on the semiconductor substrate 10 in which the diffusion layer 14 is formed in the element region defined by the element isolation film 12 (FIG. 2A). For example, a SiN film can be used as the etching stopper film. For example, by plasma CVD, the substrate temperature is 400 ° C., the power is 300 W, SiH _Four Flow rate is 100cc, NH _Three Deposited at a flow rate of 50 cc.
[0035]
Next, an insulating film 18 is deposited on the etching stopper film 16 to form an interlayer insulating film 20 (FIG. 2B). As the insulating film 18, for example, SiO ₂ A membrane can be used. For example, by plasma CVD, the substrate temperature is 400 ° C., the power is 300 W, SiH _Four Flow rate 50cc, N ₂ Deposition is performed with an O flow rate of 500 cc.
Subsequently, a contact hole 22 that penetrates the insulating film 18 and reaches the etching stopper film 16 is opened by normal lithography and anisotropic etching (FIG. 2C). At this time, the etching condition is SiO 2 ₂ The etching of the contact hole 22 does not reach the semiconductor substrate 10 by setting the etching rate of the etching stopper film 16 made of the SiN film to be sufficiently small with respect to the insulating film 18 made of the film.
[0036]
Thereafter, the etching stopper film 16 in the contact hole 22 is removed by isotropic etching (FIG. 2D). As a result, the bottom of the contact hole 22 reaches the semiconductor substrate 10 and at the same time, the etching stopper film 16 under the insulating film 18 in the vicinity of the contact hole 22 is etched to form a hole 30. Here, the isotropic etching is performed by, for example, wet etching using a phosphoric acid aqueous solution having a temperature of 100 ° C. and a concentration of 90%. This isotropic etching removes only the etching stopper film 16 and does not affect the semiconductor substrate 10, the insulating film 18, and the element isolation film 12.
[0037]
Next, the conductive film 24 is formed so as to cover the opening of the hole 30 (FIG. 3A). When depositing the conductive film 24, it is desirable to use a collimated sputtering method that allows the conductive film 24 to be deposited thickly on the bottom of the contact hole 22, rather than a normal sputtering method. For example, the conductive film 24 is formed by depositing a TiN film with a power of 10 kW, a collimator aspect ratio of 2 and a pressure of 2 mTorr.
[0038]
In the collimated sputtering method, as shown in FIG. 4A, by providing a collimator 54 between the target 50 and the substrate 52, only sputtered particles having a component perpendicular to the substrate 52 are deposited on the substrate 52. It is what is deposited.
In a normal sputtering method, since sputtered particles include particles having various directional components, when a film is formed in the contact hole 22 having a large aspect ratio, as shown in FIG. The nearer the opening, the faster the deposition rate, making it difficult to deposit at the bottom of the contact hole.
[0039]
However, since the collimator 54 is provided, most of the sputtered particles have a vertical component, so that the film can be easily formed on the bottom of the contact hole (FIG. 4C).
Note that the conductive film 24 is formed by WF at the time of embedding in a later process. ₆ It serves as a barrier layer against the gas, and has the effect of spatially separating the semiconductor substrate 10 and the contact hole 22 and electrically conducting.
[0040]
Since the conductive film 24 needs to be formed to cover at least the opening of the hole 30, the film thickness of the conductive film 24 to be formed needs to be at least as high as the opening of the hole 30. It is. That is, when the height of the opening is 100 nm, the thickness of the conductive film 24 to be formed needs to be 100 nm or more.
Subsequently, using the blanket W-CVD and etch back techniques, the plugs 26 are formed by burying W in the contact holes 22 (FIG. 3B). For example, the substrate temperature is 400 ° C., the pressure is 80 Torr, and WF ₆ Flow rate 20cc, H ₂ A W film is formed at a flow rate of 2000 cc, and Cl ₂ Etch back is performed at a flow rate of 100 cc, a power of 200 W, and a pressure of 6 mTorr.
[0041]
Here, in forming the W film, WF reacts very well with Si constituting the semiconductor substrate 10. ₆ Although gas is used, the semiconductor substrate 10 is isolated from the contact hole 22 by the conductive film 24. The conductive film 24 made of a TiN film is made of WF. ₆ As it has excellent barrier properties against erosion, WF ₆ The molecules 36 do not reach the semiconductor substrate 10 in the holes 30 and can prevent the junction breakdown of the source / drain regions due to erosion (FIG. 5).
[0042]
Thereafter, by forming the wiring layer 28 and performing patterning, a semiconductor device can be formed without causing junction breakdown (FIG. 3C).
As described above, according to the present embodiment, vacancies generated by isotropic etching of the etching stopper film are spatially isolated by the deposition of the conductive film. ₆ WF even when forming W film using gas ₆ There is no direct contact between the gas and the semiconductor substrate, and WF ₆ It is possible to prevent the junction breakdown due to gas erosion. Thereby, the reliability of the semiconductor device can be improved.
[0043]
The present invention is not limited to the above embodiment, and various modifications can be made.
For example, in the above embodiment, WF ₆ Although the case where the W plug is formed by the CVD method using a gas has been shown, the present invention can also be applied to the case where the plug 26 is formed of another metal material such as Al or Cu.
That is, in the semiconductor device according to the above-described embodiment, the holes 30 generated for isotropically etching the etching stopper film 16 are spatially separated from the inside of the contact hole 22 by the conductive film 24. Therefore, when Al or Cu is used as the material of the plug 26, the conductive film 24 functions as a barrier film that prevents the silicon substrate in the hole 30 and the plug material from coming into direct contact with each other. Bonding breakage due to the reaction between the substrate and the plug material can be prevented.
[0044]
When Al is used for the plug material, a blanket Al-CVD technique or a selective aluminum CVD technique can be applied. When Cu is used for the plug material, Cu is deposited by CVD or Cu is deposited by sputtering and then reflowed to fill the contact hole 22 and then polished back using CMP. Thus, the plug 26 can be formed.
[0045]
In the above embodiment, the SiN film is used as the etching stopper film 16, and the SiON film is used as the insulating film 18. ₂ Although the films are used, any combination of these films may be used as long as these films can be etched independently by setting the etching conditions.
Further, although the TiN film formed by the collimated sputtering method is used as the conductive film 24, a laminated film made of TiN film / Ti film may be used. If such a laminated film is used, the contact resistance between the semiconductor substrate 10 and the conductive film 24 can be reduced.
[0046]
The Ti film can be deposited by CVD or sputtering. When the Ti film is deposited by sputtering, it is not always necessary to use collimated sputtering. As long as the air holes 30 can be completely blocked by the TiN film deposited on the upper layer of the Ti film, the Ti film may be deposited by a normal sputtering method.
Also, instead of using a TiN film, WF ₆ Other conductive films that are resistant to gas erosion can also be applied. For example, a W film deposited by a collimated sputtering method can be used.
[0047]
Further, as the conductive film 24, a material having an effect as a diffusion barrier with respect to Cu or Al, for example, a WN film, a Ta film, a TaN film, a TiSiN film, a WSiN film, or the like can be used.
Further, although the phosphoric acid aqueous solution is used for etching the SiN film, other etching methods may be used.
[0048]
In addition, although blanket W-CVD and an etch back technique are used when filling W used for the plug 26, W may be buried in the contact hole 22 by selective tungsten CVD.
Further, the above-described process conditions are just an example, and even if these numerical values are changed to appropriate values, the effects of the present invention are not affected at all.
[Second Embodiment]
A semiconductor device and a manufacturing method thereof according to the second embodiment of the present invention will be described with reference to FIGS. The same components as those of the semiconductor device and the manufacturing method thereof according to the first embodiment are denoted by the same reference numerals, and description thereof is omitted or simplified.
[0049]
FIG. 6 is a process sectional view showing the structure of the semiconductor device according to the present embodiment. FIG. 7 is a process sectional view showing the method for manufacturing the semiconductor device according to the present embodiment.
The structure of the semiconductor device according to the present embodiment will be explained with reference to FIG.
The semiconductor device according to the present embodiment is characterized in that the holes 30 are filled with the conductive film 24. That is, in the semiconductor device according to the first embodiment shown in FIG. 1, the inside of the contact hole 22 and the hole 30 are spatially separated by depositing the conductive film 24 using the collimated sputtering method. In the semiconductor device according to, the inside of the hole 30 is filled with the conductive film 24, and the inside of the contact hole 22 and the semiconductor substrate 10 are isolated.
[0050]
In this way, erosion during plug formation is prevented.
Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS.
First, a contact hole 22 is opened in the interlayer insulating film 20 in the same manner as in the semiconductor device manufacturing method according to the first embodiment shown in FIGS.
[0051]
Next, the conductive film 24 is deposited by the CVD method. For example, a TiN film can be used as the conductive film. For example, by CVD, the substrate temperature is 500 ° C., TiCl _Four Flow rate 10cc, NH _Three Deposition is performed at a flow rate of 500 cc and a pressure of 100 mTorr.
Ti source gases include TDMAT (tetrakis dimethylamino titanium), TDEAT (tetrakis diethylamino titanium), and TiI. _Four Etc. may be used. When TDMAT is used, for example, the substrate temperature is 400 ° C., the TDMAT flow rate is 2 cc, NH _Three The deposition can be performed at a flow rate of 10 cc and a pressure of 100 mTorr. When TDEAT is used, for example, the substrate temperature is 400 ° C., the TDEAT flow rate is 30 cc, NH _Three The gas can be deposited at a flow rate of 10 slm and a pressure of 10 Torr.
[0052]
Since the CVD method has better coverage than the sputtering method, the inside of the holes 30 can be easily embedded by optimizing the film forming conditions. Therefore, WF ₆ The barrier effect against gas is high, the semiconductor substrate 10 and the contact hole 22 are spatially separated, and the effect of electrical conduction can be made higher than in the sputtering method.
[0053]
In the case where the conductive film 24 is formed using a TiN film formed by the CVD method, it is necessary to deposit a film thickness that at least closes the opening of the hole 30 in order to fully exhibit the effects of the present invention. is there. Since this film thickness depends on the coverage capability of the CVD film, it cannot be uniquely determined. For example, when the height of the opening is 100 nm and the TiN film is formed under the above conditions, A film thickness of about 100 nm or more is necessary.
[0054]
When depositing the conductive film 24 having excellent step coverage, the holes 30 are completely filled by depositing the conductive film 24 having a thickness of about ½ or more of the thickness of the etching stopper film 16. Can do.
Thereafter, the plug 26 is formed in the same manner as in the semiconductor device manufacturing method according to the first embodiment (FIG. 7B), and further the wiring layer 28 is formed (FIG. 7C).
[0055]
As described above, according to the present embodiment, the holes generated by the isotropic etching of the etching stopper film are filled with the conductive film. ₆ WF even when forming W film using gas ₆ There is no direct contact between the gas and the semiconductor substrate, and WF ₆ It is possible to prevent the junction breakdown due to gas erosion. Thereby, the reliability of the semiconductor device can be improved.
[0056]
The present invention is not limited to the above embodiment, and various modifications can be made.
For example, a TiN film formed by CVD is used as the conductive film 24, but WF ₆ Any conductive film having erosion resistance against gas can be used. For example, even if it is a polycrystalline silicon film or an amorphous silicon film doped with impurities, WF ₆ It is sufficient that the erosion does not reach the semiconductor substrate 10.
[0057]
As in the first embodiment, the structure of the semiconductor device according to the present embodiment can also be applied to a method for manufacturing a semiconductor device in which an Al plug or a Cu plug is formed.
Further, the above-described process conditions are just an example, and even if these numerical values are changed to appropriate values, the effects of the present invention are not affected at all.
[Third Embodiment]
A semiconductor device and a manufacturing method thereof according to the third embodiment of the present invention will be described with reference to FIGS.
[0058]
8 is a diagram for explaining a buried wiring using a BLC structure, FIG. 9 is a diagram for explaining a problem in a buried wiring using Cu, and FIG. 10 is a plan view and a cross-sectional view showing the structure of the semiconductor device according to the present embodiment. 11 and 12 are process cross-sectional views illustrating the method for fabricating the semiconductor device according to the present embodiment.
In the first and second embodiments, the present invention is applied when a contact hole is opened on a semiconductor substrate. However, the BLC structure according to the present invention can be applied to various underlayer structures.
[0059]
That is, the present invention solves a common problem in the process of embedding a conductive material in an opening, and not only when a plug is formed in a contact hole opened on a semiconductor substrate, but also other contact holes such as The effect is also exhibited in a process of filling a via hole with a plug or a process of forming a buried wiring.
[0060]
In this embodiment, the case where the BLC structure is applied to the embedded wiring will be described with reference to FIGS.
First, the embedded wiring and the embedded wiring using the BLC structure will be described.
With the demand for higher speed LSI, lowering of resistance of wiring material is required. In order to realize this, a novel low-resistance material such as Cu (copper) has been studied as a wiring material.
[0061]
However, since Cu does not generate a reactant having a high vapor pressure, it is difficult to use a patterning method using a reaction such as RIE (Reactive Ion Etching), and it is difficult to form fine wiring.
For this reason, when forming a wiring using Cu, a wiring groove is formed in the insulating film in advance, Cu is embedded in the groove by sputtering or the like, and Cu on the insulating film is etched back by CMP or the like. It is useful to form a wiring embedded in an insulating film by (polishing back).
[0062]
The BLC structure can also be applied when forming such a buried wiring. A case where the BLC structure is applied to the embedded wiring will be described with reference to FIG.
As shown in FIGS. 8A and 8B, when the contact plug 110 is embedded in the interlayer insulating film 104 formed on the semiconductor substrate 100, the wiring 122 embedded in the interlayer insulating film 116 in the upper layer. When the etching is performed to form the wiring trench 118 for embedding the wiring 122 in the interlayer insulating film 116, the interlayer insulating film 104 must be prevented from being etched. This is because if the etching reaches the interlayer insulating film 104, the shape of the wiring 122 embedded in the wiring trench 118 is greatly affected (FIG. 8C). When the shape of the wiring 122 changes in this way, the variation in wiring resistance increases, and the withstand voltage between the wiring 122 and a lower wiring (not shown) decreases, which affects the reliability of the semiconductor device. It will be.
[0063]
Therefore, if the BLC structure is applied in such a case, the interlayer insulating film 104 can be prevented from being excessively etched.
That is, by forming an etching stopper film 112 having different etching selectivity from these insulating films between the interlayer insulating film 104 and the interlayer insulating film 116, the etching of the interlayer insulating film 116 is controlled by the etching stopper film 112. It can be stopped (FIG. 8 (d)).
[0064]
By doing so, when etching the wiring trench 118 for embedding the wiring 122, the influence of the etching does not reach the interlayer insulating film 104, and the shape of the wiring 122 is determined only by the thickness of the interlayer insulating film 116. Wiring can be formed stably.
However, when Cu is used as the material for the embedded wiring, it is not preferable to apply the BLC structure as it is. The reason will be described below.
[0065]
Even in the case of forming an embedded wiring using Cu, when etching the etching stopper film 112, as in the case of a normal BLC structure, wet etching is performed to ensure etching selectivity with the interlayer insulating film 104 and the insulating film 114. It is preferable to use etching. However, since wet etching is isotropic etching, etching is performed up to the etching stopper film 112 under the insulating film 114, and a hole 124 is formed under the insulating film 114 (FIG. 9A). . Since the holes 124 formed in this way cannot be covered by the conventional sputtering method, they remain even after the conductive film 120 is deposited (FIG. 9B).
[0066]
For this reason, when Cu is embedded in the wiring formation process of the next step, Cu is embedded in the holes 124, and Cu diffuses from this portion into the insulating film 114, causing inter-wire leakage and dielectric constant of the insulating film. May rise (FIG. 9C).
As described above, it is not preferable to apply the conventional BLC structure as it is to the embedded wiring using Cu.
[0067]
Next, the structure of the semiconductor device according to the present embodiment will be explained with reference to FIG. FIG. 10A is a plan view showing the structure of the semiconductor device according to the present embodiment, and FIG. 10B is a cross-sectional view showing the structure of the semiconductor device according to the present embodiment.
On the semiconductor substrate 100, an interlayer insulating film 104 having a contact hole 102 opened in a predetermined region is formed. A contact plug 110 made of a conductive film 106 and a plug 108 is formed in the contact hole 102.
[0068]
An interlayer insulating film 116 including an etching stopper film 112 and an insulating film 114 is formed on the base substrate where the contact plug 110 is exposed on the surface of the interlayer insulating film 104. In the interlayer insulating film 116, a wiring groove 118 for embedding wiring is formed, and the contact plug 110 is exposed at the bottom of the groove.
A conductive film 120 serving as a barrier metal is formed on the inner wall of the wiring groove 118 and the interlayer insulating film 104, and a wiring 122 is embedded in the wiring groove 118 in which the conductive film 120 is formed.
[0069]
Here, in the semiconductor device according to the present embodiment, the etching stopper film 112 in the vicinity of the wiring trench 118 is etched in the lateral direction to form the void 124, but the conductive film 120 formed in the wiring trench 118 is The hole 124 is not interrupted, and is characterized in that it is formed so as to completely surround the inside of the wiring groove 118.
Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS.
[0070]
First, an interlayer insulating film 104 in which contact plugs 110 are embedded is formed on the semiconductor substrate 100. The contact plug 110 is connected to a transistor electrode (not shown) formed on the semiconductor substrate 100. The interlayer insulating film 104 is formed of, for example, a silicon oxide film.
Here, the contact plug 110 may have any structure.
[0071]
One or more wiring layers may be formed between the semiconductor substrate 100 and the interlayer insulating film 104. That is, the wiring 122 may be a second-layer metal wiring, or may be an upper-layer metal wiring.
In this specification, such a base structure is collectively referred to as a base substrate. That is, the base substrate referred to in this specification includes not only the semiconductor substrate itself but also a semiconductor substrate on which elements such as transistors are formed, and a structure in which one or more wiring layers are formed on the upper layer. Shall also be included.
[0072]
Next, an insulating film to be the etching stopper film 112 is deposited on such a base substrate. As the etching stopper film 112, for example, a SiN film can be used. For example, by plasma CVD, the substrate temperature is 400 ° C., the power is 300 W, SiH _Four Flow rate is 100cc, NH _Three Deposited at a flow rate of 50 cc.
Subsequently, an insulating film 114 is deposited on the etching stopper film 112, and an interlayer insulating film 116 composed of the etching stopper film 112 and the insulating film 114 is formed (FIG. 11A). As the insulating film 114, for example, SiO ₂ A membrane can be used. For example, by plasma CVD, the substrate temperature is 400 ° C., the power is 300 W, SiH _Four Flow rate 50cc, N ₂ Deposition is performed with an O flow rate of 500 cc.
[0073]
Thereafter, a wiring groove 118 that reaches the etching stopper film 112 through the insulating film 114 is opened by using a normal lithography technique and anisotropic etching technique (FIG. 11B). At this time, the etching condition is SiO 2 ₂ By setting the etching rate of the etching stopper film 112 made of the SiN film to be sufficiently small with respect to the insulating film 114 made of, the etching of the wiring groove 118 does not reach the interlayer insulating film 104 or the contact plug 110. .
[0074]
Next, the etching stopper film 112 in the wiring trench 118 is removed by isotropic etching (FIG. 11C). As a result, the bottom of the wiring trench 118 reaches the interlayer insulating film 104 or the contact plug 110, and at the same time, the etching stopper film 112 under the insulating film 114 near the wiring trench 118 is etched to form a hole 124. Here, the isotropic etching is performed by, for example, wet etching using a phosphoric acid aqueous solution having a temperature of 100 ° C. and a concentration of 90%.
[0075]
Subsequently, the conductive film 120 is formed so as to cover the opening of the hole 124 (FIG. 12A). Here, the conductive film 118 serves as a barrier layer that prevents the wiring material from entering the cavities 124 when the wiring material is embedded in a later step. The conductive film 118 includes the interlayer insulating films 104 and 116 and the wiring groove 118. It has the effect of spatial isolation. Since the conductive film 120 needs to be formed to cover at least the opening of the hole 124, the film thickness of the conductive film 120 to be formed needs to be at least as high as the opening of the hole 124. It is. Therefore, it is desirable to use a collimated sputtering method for depositing the conductive film 120 (see the first embodiment).
[0076]
Thereafter, a Cu film is deposited by sputtering and reflow is performed, and Cu is embedded in the wiring trench 118. For example, Cu is sputtered at a pressure of 1.5 mTorr, power of 5 kW, and an Ar flow rate of 25 sccm, and Cu is reflowed at a temperature of 350 ° C., an Ar flow rate of 1000 sccm, and a pressure of 80 Torr.
Next, Cu and the conductive film 120 on the interlayer insulating film 116 are removed by the CMP method, and the Cu and the conductive film 120 are left only in the wiring trench 118. For example, CMP is performed using an alumina-based abrasive at a rotation speed of 100 rpm and a polishing pressure of 6 psi. Thus, the wiring 122 embedded in the wiring groove 118 is formed (FIG. 12B).
[0077]
In addition, you may use CVD method for embedding Cu. For example, Cu (PMPS) (HFAC) at a flow rate of 0.08 g / min and H ₂ Is introduced as a carrier gas at a flow rate of 300 cc, and the temperature is 200 ° C. and the pressure is 200 mTorr.
Here, Cu that easily diffuses in the silicon oxide film is used for the wiring 122, but the interlayer insulating film 104 and the insulating film 114 made of the silicon oxide film are isolated from the wiring 122 by the conductive film 120. The conductive film 120 made of a TiN film has an excellent effect as a diffusion barrier for Cu, so that Cu does not diffuse into the interlayer insulating films 104 and 116, and leakage between wirings or dielectric of the interlayer insulating film is caused. An increase in rate can be prevented.
[0078]
As described above, according to the present embodiment, since the voids 124 generated by isotropic etching of the etching stopper film 112 are spatially isolated by the deposition of the conductive film 120, Cu is embedded in the wiring trench 118. At this time, Cu and the interlayer insulating films 104 and 116 are not in direct contact with each other, and leakage between wirings due to Cu diffusion, an increase in the dielectric constant of the interlayer insulating film, and the like can be prevented.
[0079]
The present invention is not limited to the above embodiment, and various modifications can be made.
For example, although the case where the embedded wiring is formed has been described in the above embodiment, the present invention may be applied to filling of via holes used for interlayer connection of multilayer wiring. In this case, this can be easily achieved by replacing the wiring trench 118 with a via hole.
Moreover, although the example which forms the electroconductive film 120 by the collimated sputtering method was shown in the said embodiment, you may deposit the electroconductive film 120 using CVD method like 2nd Embodiment. In this case, the holes 124 can be completely filled with the conductive film 120.
[0080]
Further, if a material having an effect as a diffusion barrier with respect to Cu, for example, a WN film, a Ta film, a TaN film, a TiSiN film, a WSiN film, or the like is used as the conductive film 120, Cu or Al is contained in the conductive film 120. Can be effectively prevented from diffusing and reaching the holes 124.
In addition, as an example of isotropic etching of the etching stopper film 112, an example in which wet etching using a phosphoric acid aqueous solution is used has been shown. If isotropic etching is used, the etching stopper film 112 can be etched without affecting the plug 110 in any way. Here, isotropic dry etching is performed by, for example, SF. ₆ Flow rate is 120cc, O ₂ The flow rate is 30 cc, the power is 200 W, the pressure is 200 mTorr, and the temperature is 20 ° C.
[0081]
Further, the above-described process conditions are just an example, and even if these numerical values are changed to appropriate values, the effects of the present invention are not affected at all.
[Fourth Embodiment]
A semiconductor device and a manufacturing method thereof according to the fourth embodiment of the present invention will be described with reference to FIGS. The same components as those of the semiconductor device and the manufacturing method thereof according to the first embodiment are denoted by the same reference numerals, and description thereof is omitted or simplified.
[0082]
FIG. 13 is a schematic cross-sectional view showing the structure of the semiconductor device according to the present embodiment, and FIGS. 14 to 17 are process cross-sectional views showing the method for manufacturing the semiconductor device according to the present embodiment.
The semiconductor device according to the present embodiment is characterized in that an insulating film 32 is further formed under the etching stopper film 16 and the inner diameter of the contact hole 22 formed in the interlayer insulating film 20 changes in the depth direction. There is.
[0083]
That is, the etching stopper film 16 in the vicinity of the contact hole 22 is etched in the lateral direction to increase the inner diameter, but the inner diameter of the insulating film 32 is substantially equal to the inner diameter of the insulating film 18 and is smaller than the inner diameter of the etching stopper film 16. ing.
The conductive film 24 formed in the contact hole 22 is interrupted at the etching stopper film 16, but the opening formed in the insulating film 32 is completely formed by the conductive film 24 formed at the bottom of the contact hole 22. The semiconductor substrate 10 is not exposed in the contact hole 22.
[0084]
By configuring the semiconductor device in this manner, it is possible to prevent the semiconductor substrate 10 from being eroded by the source gas when the plug 26 is formed.
Next, the method for fabricating the semiconductor device according to the present embodiment will be explained.
An element isolation film 12 having a thickness of about 250 nm is formed on the main surface of the semiconductor substrate 10. Next, a well, a channel stop layer, and a threshold control impurity layer (not shown) are formed in a desired region.
[0085]
Subsequently, a gate oxide film 34 having a thickness of about 6 nm is formed by thermal oxidation, and an amorphous silicon film having a thickness of about 200 nm is deposited thereon by a CVD method.
Thereafter, P (phosphorus) ions are applied to the amorphous silicon film in the region for forming the N-channel transistor, and BF is applied to the amorphous silicon film in the region for forming the P-channel transistor. ₂ (Boron fluoride) ions are implanted respectively.
[0086]
Next, a silicon oxide film having a thickness of about 80 nm is deposited on the amorphous silicon film by a CVD method.
Subsequently, the gate electrode 40 is formed by patterning the laminated film composed of the amorphous silicon film and the silicon oxide film 38 by photolithography and RIE (Reactive Ion Etching) method (FIG. 14A). .
[0087]
Thereafter, impurities are implanted into the semiconductor substrate 10 using the gate electrode as a mask to form an LDD (Lightly Doped Drain).
A silicon oxide film having a thickness of about 100 nm is deposited by CVD, and then etched back to form sidewalls 42 on the side walls of the gate electrode.
Next, impurities are implanted into the semiconductor substrate 10 using the gate electrode and the side wall 42 as a mask to form the source / drain diffusion layer 14.
[0088]
Thereafter, a heat treatment at 800 ° C. is performed to activate the implanted impurities (FIG. 14B).
Next, a Co (cobalt) film having a thickness of about 8 nm and a TiN film having a thickness of about 15 nm are successively deposited by sputtering, and then RTA (Rapid Thermal Annealing) is performed at 550 ° C. / CoSi selectively on the drain diffusion layer ₂ A film 44 is formed.
[0089]
Subsequently, the TiN film is removed with ammonia-hydrogen peroxide, and the unreacted Co film is removed with sulfuric acid-hydrogen peroxide (FIG. 14C).
In this way, CoSi is formed on the source / drain diffusion layer 14. ₂ After the MOS transistor having the film 44 selectively formed is formed on the semiconductor substrate 10, the insulating film 32 made of a silicon oxide film having a thickness of about 10 nm and the etching stopper film 16 made of a SiN film having a thickness of about 50 nm are formed. Then, an insulating film 18 made of a silicon oxide film having a thickness of about 250 nm is deposited by PE-CVD. Next, the SOG film 46 is spin-coated on the insulating film 18 to form the interlayer insulating film 20 whose surface is flattened.
[0090]
Subsequently, a resist film 48 having a contact hole pattern to be formed is formed on the SOG film 46 by lithography (FIG. 15A).
Next, using the resist film as a mask, C _Four F ₈ Etching is performed using a mixed gas plasma of Ar and Ar to process the SOG film 46 and the insulating film 18. At this time, a SiN film is used as the etching stopper film 16, but the SiN film on the shoulder of the gate electrode is worn out by about half of the total film thickness (FIG. 15B).
[0091]
After removing the resist film 48, it is immersed in a phosphoric acid aqueous solution at 150 ° C., and the etching stopper film 16 made of an SiN film is removed. In the etching using phosphoric acid, since the selective ratio between the SiN film and the silicon oxide film can be secured to about 50, the underlying insulating film 32 is hardly worn. Further, since etching with phosphoric acid is isotropic, the SiN film is also etched in the lateral direction. As a result, the insulating film 18 has an overhang shape, and a hole 30 is formed (FIG. 16A).
[0092]
Next, CF _Four , CHF _Three The insulating film 32 made of a silicon oxide film is anisotropically etched by a mixed gas plasma of Ar. At the time of etching, since the upper insulating film 18 serves as a mask, only the insulating film 32 directly under the opening of the overhanging insulating film 18 is removed (FIG. 16B).
At this time, by setting the over-etching to about 50% or less, the wear of the side wall 42 surrounding the gate electrode can be suppressed to be sufficiently small, so that a short circuit with the plug 26 to be formed later can be prevented. In addition, even when a boundary between the element isolation film 12 and the element region exists in the contact hole 22, wear of the element isolation film 12 can be suppressed, so that a junction short-circuit can be prevented.
[0093]
Thereafter, a conductive film 24 made of a TiN film having a thickness of about 70 nm is deposited by sputtering. At this time, a TiN film is deposited on the bottom of the contact hole 22, but not in the hole 30. However, since the insulating film 32 remains in the hole 30, the semiconductor substrate 10 is not exposed in the contact hole 22 after the conductive film 24 is deposited. Therefore, the conductive film 24 can be deposited so as to cover the semiconductor substrate 10 even if a slight overhang occurs when depositing the conductive film 24, so that a normal sputtering method can be used (FIG. 17A). ).
[0094]
Next, a W film having a thickness of about 600 nm is deposited by CVD. As described above, since the semiconductor substrate 10 is not exposed in the contact hole, the WF is deposited when the W film is deposited. ₆ Gas does not come into contact with the semiconductor substrate 10, and erosion of the semiconductor substrate 10 can be prevented. Thereby, junction destruction can also be prevented.
Subsequently, the plug 26 is formed by etching back the W film and leaving it only in the contact hole.
[0095]
Thereafter, a wiring layer 28 is formed on the upper layer, and a wiring layer (not shown) is further formed on the upper layer as necessary (FIG. 17B).
As described above, according to the present embodiment, by providing the insulating film 32 under the etching stopper film 16, the semiconductor substrate 10 at the bottom of the contact hole 22 is electrically conductive even when the insulating film 18 has an overhang shape. Since the conductive film 24 can completely cover, the erosion of the semiconductor substrate during the formation of the plug 26 can be prevented.
[0096]
Thereby, when removing the etching stopper film 16, an etching method with a high selection ratio can be used. Therefore, even if the SAC structure has a shoulder of the gate electrode 40 inside the contact hole 22, the gate electrode 40 It is possible to prevent the gate electrode 40 from being exposed by etching the upper side wall 42 and the insulating film 38.
[0097]
The present invention is not limited to the above embodiment, and various modifications can be made.
For example, in the above embodiment, the insulating film 32 directly below the etching stopper film 16 is SiO. ₂ Although a film is used, a SiON film may be used.
In addition, the SiN film was removed by wet etching using a phosphoric acid aqueous solution. _Four And O ₂ It is also possible to use fluorine radicals by using a down flow of mixed gas plasma. In this case, since a selection ratio of about 10 can be obtained, it can be used in the above manufacturing method. If chlorine is further added, the selectivity between the silicon oxide film and the SiN film can be improved to almost infinite.
[0098]
For removing the SiN film, SF is used. ₆ Gas plasma may be used. In this case, the selection ratio is slightly low, about 5, but the above manufacturing method can be applied by setting the thickness of the insulating film 32 to about 20 nm. SF ₆ In etching using gas plasma, the etching rate in the vertical direction is faster than in the horizontal direction.
[0099]
The film thickness of the insulating film 32 is desirably set as appropriate depending on the etching conditions of the SiN film.
In the above embodiment, the CoSi is formed on the source / drain diffusion layer 14. ₂ The film 44 was formed in a self-aligned manner, but CoSi ₂ The same applies to a semiconductor device in which the film 44 is not formed.
[0100]
Further, the above-described process conditions are just an example, and even if these numerical values are changed to appropriate values, the effects of the present invention are not affected at all.
[Fifth Embodiment]
A semiconductor device and a manufacturing method thereof according to the fifth embodiment of the present invention will be described with reference to FIGS.
[0101]
FIG. 18 is a schematic cross-sectional view showing the structure of the semiconductor device according to the present embodiment. FIGS. 19 and 20 are process cross-sectional views showing the method for manufacturing the semiconductor device according to the present embodiment.
In the present embodiment, the case where the semiconductor device according to the fourth embodiment and the manufacturing method thereof are applied to a semiconductor device having embedded wiring will be described.
First, the structure of the semiconductor device according to the present embodiment will be explained with reference to FIG. FIG. 18A is a plan view showing the structure of the semiconductor device according to the present embodiment, and FIG. 18B is a schematic sectional view showing the structure of the semiconductor device according to the present embodiment.
[0102]
In addition to the wiring structure shown in the third embodiment, the embedded wiring may be used for local wiring that directly contacts the semiconductor substrate. For example, as shown in FIG. 18A, in the structure in which the gate electrodes 62 and 64 are arranged in parallel on the element region 60, a buried wiring is used for the wiring 66 that connects the element region 60 and the gate electrode 62. Can do.
[0103]
When the BLC structure is applied when forming the wiring groove 68 for embedding the wiring in such a semiconductor device, junction breakage occurs in the hole 30 portion as in the conventional semiconductor device shown in FIG. (FIG. 39).
Therefore, in the semiconductor device according to the present embodiment, the insulating film 32 is further formed under the etching stopper film 16, and the opening width of the wiring groove 68 formed in the interlayer insulating film 20 is changed in the depth direction (FIG. 18 (b)).
[0104]
That is, the etching stopper film 16 in the vicinity of the wiring trench 68 is etched in the lateral direction to increase the opening width, but the inner diameter of the insulating film 32 is substantially equal to the inner diameter of the insulating film 18 and is narrower than the inner diameter of the etching stopper film 16. It has become.
The conductive film 24 formed in the wiring groove 68 is interrupted at the portion of the etching stopper film 16, but the opening formed in the insulating film 32 is completely formed by the conductive film 24 formed at the bottom of the wiring groove 68. The semiconductor substrate 10 is not exposed in the wiring trench 68.
[0105]
By configuring the semiconductor device in this manner, it is possible to prevent the erosion of the semiconductor substrate 10 by the source gas when forming the plug 26 and the junction breakdown due to the reaction between the wiring material and the semiconductor substrate 10.
Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS. These process drawings show a cross section taken along line AA ′ in FIG.
[0106]
First, a MOS transistor is formed on the main surface of the semiconductor substrate 10 in the same manner as in the semiconductor device manufacturing method according to the fourth embodiment, for example. At this time, the silicon oxide film 38 in a predetermined region on the gate electrode 62 connected to the wiring 66 is removed in advance (FIG. 19A).
After the MOS transistor is formed on the semiconductor substrate 10 in this manner, the insulating film 32 made of a silicon oxide film having a thickness of about 10 nm, the etching stopper film 16 made of a SiN film having a thickness of about 50 nm, and the thickness of about 250 nm. An insulating film 18 made of a silicon oxide film is deposited by PE-CVD. Next, the surface of the insulating film 18 is polished by CMP to form an interlayer insulating film 20 having a flattened surface (FIG. 19B).
[0107]
Next, the insulating film 18 is processed into a pattern of a buried wiring to be formed by ordinary lithography and etching techniques. Etching of the insulating film 18 is performed by, for example, C _Four F ₈ And a mixed gas plasma of Ar and Ar.
Subsequently, the etching stopper film 16 made of a SiN film is etched. For example, wet etching using a phosphoric acid aqueous solution at 150 ° C. is used. In the etching using phosphoric acid, since the selective ratio between the SiN film and the silicon oxide film can be secured to about 50, the underlying insulating film 32 is hardly depleted. Further, since etching with phosphoric acid is isotropic, the SiN film is also etched in the lateral direction. As a result, the insulating film 18 has an overhang shape, and a hole 30 is formed.
[0108]
Next, CF _Four , CHF _Three The insulating film 32 made of a silicon oxide film is anisotropically etched by a mixed gas plasma of Ar. At the time of etching, since the upper insulating film 18 serves as a mask, only the insulating film 32 directly under the opening of the overhanging insulating film 18 is removed.
Thus, a wiring trench 68 is formed in which the source / drain diffusion layer 14 and the gate electrode 62 are exposed (FIG. 19C).
[0109]
Thereafter, a conductive film 24 made of a TiN film having a thickness of about 70 nm is deposited by sputtering. At this time, a TiN film is deposited on the bottom of the wiring trench 68 but not in the hole 30. However, since the insulating film 32 remains in the hole 30, the semiconductor substrate 10 is not exposed in the wiring groove 68 after the conductive film 24 is deposited. Therefore, since the conductive film 24 can be deposited so as to cover the semiconductor substrate 10 even if a slight overhang occurs when depositing the conductive film 24, a normal sputtering method can be used (FIG. 20A). ).
[0110]
Next, a W film is deposited by the CVD method, and W is embedded in the wiring trench 68. For example, the substrate temperature is 400 ° C., the pressure is 80 Torr, and WF ₆ Flow rate 20cc, H ₂ A W film is formed at a flow rate of 2000 cc.
Here, in forming the W film, WF reacts very well with Si constituting the semiconductor substrate 10. ₆ Although gas is used, since the semiconductor substrate 10 is isolated from the wiring trench 68 by the conductive film 24, WF ₆ Molecules do not come into contact with the semiconductor substrate 10, and erosion of the semiconductor substrate 10 can be prevented.
[0111]
Subsequently, the W film and the conductive film 24 on the interlayer insulating film 20 are removed by CMP to leave W only in the wiring trench 68. For example, CMP is performed using an alumina-based abrasive at a rotation speed of 50 rpm and a polishing pressure of 6 psi. Thus, a wiring 66 is formed which is buried in the wiring trench 68 and connects the source / drain diffusion layer 14 and the gate electrode 62 (FIG. 20B).
[0112]
Thus, according to the present embodiment, by providing the insulating film 32 under the etching stopper film 16, the semiconductor substrate 10 at the bottom of the wiring trench 68 is conductive even when the insulating film 18 has an overhang shape. Since the film 24 is completely covered, it is possible to prevent the wiring material and the semiconductor substrate 10 from reacting when the wiring 66 is formed.
The present invention is not limited to the above embodiment, and various modifications can be made.
[0113]
For example, although W is embedded as the embedded wiring in the above embodiment, the wiring 66 may be formed by embedding Cu. However, in this case, the formation of the conductive film 24 using the collimated sputtering method as shown in the first embodiment or the CVD method as shown in the second embodiment is more effective in suppressing Cu diffusion. It is effective.
Further, Al may be used as the embedded wiring. Also in this case, the reaction between Al and the semiconductor substrate 10 can be prevented.
[0114]
Further, the above-described process conditions are just an example, and even if these numerical values are changed to appropriate values, the effects of the present invention are not affected at all.
[Sixth Embodiment]
A semiconductor device and a manufacturing method thereof according to the sixth embodiment of the present invention will be described with reference to FIGS.
[0115]
FIG. 21 is a schematic cross-sectional view showing the structure of the semiconductor device according to the present embodiment, and FIGS. 22 and 23 are process cross-sectional views showing the method for manufacturing the semiconductor device according to the present embodiment.
As shown in FIG. 36, when a via hole is formed below the interlayer insulating film 134 when a via hole is formed on the buried wiring 122, the source gas of the plug 142 and the buried wiring 122 are filled when the via hole is filled with the plug. Reacts in the holes 138 to produce a high-resistance reactant 146, which may degrade the contact characteristics.
[0116]
In the present embodiment, a semiconductor device that solves the above-described problems and a method for manufacturing the same are provided.
The semiconductor device according to the present embodiment is characterized in that the same structure as the interlayer insulating film in the fourth embodiment is adopted as the interlayer insulating film 134 formed on the buried wiring 122. That is, in the semiconductor device according to the present embodiment, in the via hole having the BLC structure, the insulating film 128 is further provided under the etching stopper film 130, and the wiring 122 embedded in the via hole is an insulating film in the hole 138. 128 is isolated from the contact plug 144.
[0117]
Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS.
First, for example, in the same way as in the semiconductor device manufacturing method according to the third or fifth embodiment, the wiring 122 embedded in the interlayer insulating film 114 is formed on the semiconductor substrate 100 (FIG. 22A).
[0118]
Next, an insulating film 128 made of a silicon oxide film having a film thickness of about 10 nm, an etching stopper film 130 made of a SiN film having a film thickness of about 50 nm, and a film thickness of about 700 nm are formed on the base substrate in which the wiring 122 is thus buried. An insulating film 132 made of a silicon oxide film is deposited by a PE-CVD method, and an insulating film 128, an etching stopper film 130, and an interlayer insulating film 134 made of the insulating film 132 are formed.
[0119]
Subsequently, the surface of the interlayer insulating film 134 is polished by a CMP method to flatten the surface (FIG. 22B).
Thereafter, a via hole 136 formed on the wiring 122 is opened by normal lithography and etching. First, C _Four F ₈ Etching with a mixed gas plasma of Ar and Ar is performed to process the insulating film 132.
[0120]
Next, it is immersed in a phosphoric acid aqueous solution at 150 ° C., and the etching stopper film 130 in the via hole 136 is removed. In the etching using phosphoric acid, since the selective ratio between the SiN film and the silicon oxide film can be secured to about 50, the underlying insulating film 128 is hardly worn. Further, since etching with phosphoric acid is isotropic, the SiN film is also etched in the lateral direction. As a result, the insulating film 132 has an overhang shape, and a hole 138 is formed.
[0121]
Next, CF _Four , CHF _Three The insulating film 128 made of a silicon oxide film is anisotropically etched by a mixed gas plasma of Ar. At the time of etching, since the upper insulating film 128 serves as a mask, only the insulating film 128 directly under the opening of the overhanging insulating film 132 is removed (FIG. 22C).
Thereafter, a conductive film 140 made of a TiN film having a thickness of about 70 nm is deposited by sputtering. At this time, although the conductive film 140 is deposited at the bottom of the via hole, it is not deposited in the hole 138. However, since the insulating film 128 remains in the hole 138, the wiring 122 is not exposed in the via hole 136 after the conductive film 140 is deposited. Therefore, the conductive film 140 can be deposited so as to cover the wiring 122 even if a slight overhang occurs when depositing the conductive film 140, so that a normal sputtering method can be used (FIG. 23A). .
[0122]
Next, a W film having a thickness of about 600 nm is deposited by CVD. As described above, since the wiring 122 is not exposed in the via hole 136, the WF is deposited when the W film is deposited. ₆ Gas does not come into contact with the wiring 122. Therefore, wiring made of Cu and WF ₆ Since the gas does not react to form a high resistance reactant, the contact characteristics between the wiring 122 and the W film can be kept good.
[0123]
Subsequently, the W film is etched back to remain only in the via hole 136, thereby forming a contact plug 144 (FIG. 23B).
As described above, according to the present embodiment, the insulating film 128 is provided under the etching stopper film 130, so that the wiring 122 in the via hole 136 is electrically conductive even when the insulating film 132 has an overhang shape. Since the plug is completely covered with 140, the plug material gas and the wiring 122 do not react when the plug 142 is formed. Thereby, the contact reliability between the contact plug 144 and the wiring 122 can be improved.
[0124]
The present invention is not limited to the above embodiment, and various modifications can be made.
For example, although the case where the contact plug 144 is formed on the embedded wiring 122 has been described in the above embodiment, the present invention can also be applied to the case where the embedded wiring is formed on the contact plug.
In the present invention, since the conductive material exposed in the holes 138 reacts with the CVD source gas and the upper wiring material, the contact characteristics are adversely affected. It can be applied to a wiring structure.
[0125]
In the above embodiment, the problem is solved by providing the insulating film 128 under the etching stopper film 130. However, the structure of the semiconductor device according to the first or second embodiment is applied, and the via hole 136 is vacated by the conductive film 140. The hole 138 may be spatially blocked, or the conductive film 140 may be completely embedded in the hole 138.
Further, the above-described process conditions are just an example, and even if these numerical values are changed to appropriate values, the effects of the present invention are not affected at all.
[Seventh Embodiment]
A semiconductor device and a manufacturing method thereof according to the seventh embodiment of the present invention will be described with reference to FIGS.
[0126]
FIG. 24 is a schematic cross-sectional view showing the structure of the semiconductor device according to the present embodiment. FIGS. 25 and 26 are process cross-sectional views showing the method for manufacturing the semiconductor device according to the present embodiment.
As shown in FIG. 34, in a semiconductor device having a wiring 210 connected to a contact plug 208 embedded in an interlayer insulating film 202 on a semiconductor substrate 200, a BLC structure is applied when a via hole connected to the wiring 210 is opened. Then, the contact plug 230 and the contact plug 208 may be short-circuited in the hole 224 formed when the etching stopper film 216 is etched.
[0127]
In the present embodiment, a semiconductor device that reduces the short between plugs as described above and a manufacturing method thereof are provided.
The semiconductor device according to the present embodiment is characterized in that an insulating film 214 is further provided under the etching stopper film 216. That is, the upper interlayer insulating film 220 for embedding the contact plug 230 is constituted by the insulating film 214, the etching stopper film 216, and the insulating film 218, and the contact plug 230 filled in the via hole is in the hole 224. It is insulated from the contact plug 208 by the insulating film 214.
[0128]
Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS.
First, for example, in the same manner as the semiconductor device manufacturing method according to the third embodiment, an interlayer insulating film 202 in which contact plugs 208 are embedded is formed on a semiconductor substrate 200.
[0129]
Next, on the interlayer insulating film 202 in which the contact plug 208 is embedded, a wiring layer composed of a wiring 210 made of, for example, Al and a conductive film 212 made of, for example, TiN is formed (FIG. 25A). The conductive film 212 functions as an antihalation film when patterning the wiring 210 and / or as an electromigration prevention film.
[0130]
Subsequently, an insulating film 214 made of a silicon oxide film with a thickness of about 10 nm, an etching stopper film 216 made of a SiN film with a thickness of about 50 nm, and a film thickness of about An insulating film 218 made of a 700 nm silicon oxide film is deposited by PE-CVD to form an interlayer insulating film 220 made of an insulating film 214, an etching stopper film 216, and an insulating film 218.
[0131]
Thereafter, the surface of the interlayer insulating film 220 is polished by a CMP method to flatten the surface (FIG. 25B).
Next, a via hole 222 formed on the wiring 210 is opened by normal lithography and etching. First, C _Four F ₈ Etching with a mixed gas plasma of Ar and Ar is performed to process the insulating film 218.
Subsequently, it is immersed in a phosphoric acid aqueous solution at 150 ° C., and the etching stopper film 216 in the via hole 222 is removed. In the etching using phosphoric acid, since the selective ratio between the SiN film and the silicon oxide film can be secured about 50, the underlying insulating film 214 is hardly worn. Further, since etching with phosphoric acid is isotropic, the SiN film is also etched in the lateral direction. As a result, the insulating film 218 has an overhang shape, and a hole 224 is formed.
[0132]
After this, CF _Four , CHF _Three The insulating film 214 made of a silicon oxide film is anisotropically etched by a mixed gas plasma of Ar. At the time of etching, since the upper insulating film 218 serves as a mask, only the insulating film 214 immediately under the opening of the overhanging insulating film 218 is removed (FIG. 25C).
At this time, even if the hole 224 extends on the contact plug 208, the contact plug 208 is not exposed in the via hole 222 because the insulating film 214 is formed in the hole 224.
[0133]
Next, a conductive film 226 made of a TiN film having a thickness of about 70 nm is deposited by sputtering (FIG. 26A).
Subsequently, a W film having a thickness of about 600 nm is deposited by CVD. As described above, since the contact plug 208 is not exposed in the via hole 222, the W film and the contact plug 208 are not short-circuited.
[0134]
Thereafter, the W film is etched back to remain only in the via hole 222, thereby forming the contact plug 230 (FIG. 26B).
As described above, according to the present embodiment, by providing the insulating film 214 under the etching stopper film 216, the contact plug 208 is exposed under the hole 224 even when the insulating film 218 has an overhang shape. Therefore, a short circuit between the contact plug 230 and the contact plug 208 can be reduced as compared with the conventional semiconductor device.
[0135]
The present invention is not limited to the above embodiment, and various modifications can be made.
For example, in the above embodiment, the problem is solved by providing the insulating film 214 under the etching stopper film 216, but the structure of the semiconductor device according to the first embodiment is applied, and the via hole 222 and the hole 224 are formed by the conductive film 226. May be completely blocked spatially.
[0136]
Further, the above-described process conditions are just an example, and even if these numerical values are changed to appropriate values, the effects of the present invention are not affected at all.
[Eighth Embodiment]
A semiconductor device and a manufacturing method thereof according to the eighth embodiment of the present invention will be described with reference to FIGS.
[0137]
FIG. 27 is a schematic cross-sectional view showing the structure of the semiconductor device according to the present embodiment, and FIGS. 28 and 29 are process cross-sectional views showing the method for manufacturing the semiconductor device according to the present embodiment.
In the fourth to seventh embodiments, the structure in which the insulating film is further provided under the etching stopper film is applied to the interlayer insulating film. However, if this structure is applied to the case where a buried wiring is formed on the interlayer insulating film, the wiring groove It is also possible to facilitate the etching for forming.
[0138]
In the present embodiment, the case where the structure of the interlayer insulating film according to the fourth embodiment is applied to the structure of the semiconductor device according to the third embodiment will be described.
The semiconductor device according to the present embodiment is characterized in that an insulating film 126 made of a silicon oxide film is further formed under the etching stopper film 112 in the semiconductor device according to the third embodiment shown in FIG.
[0139]
By providing the insulating film 126 in this manner, an etching process for forming the wiring trench 118 for embedding the wiring 122 can be facilitated.
Next, the method for fabricating the semiconductor device according to the present embodiment will be explained.
First, for example, in the same manner as in the semiconductor device manufacturing method according to the third embodiment, an interlayer insulating film 104 in which contact plugs 110 are embedded is formed on a semiconductor substrate 100 (FIG. 28A).
[0140]
Next, a SiO film having a thickness of about 10 nm is formed on such a base substrate. ₂ An insulating film 126 made of a film and an etching stopper film 112 made of a SiN film having a thickness of about 50 nm are sequentially deposited.
Subsequently, a SiO film having a thickness of about 250 nm is formed on the etching stopper film 112. ₂ An insulating film 114 made of a film is deposited, and an insulating film 126, an etching stopper film 112, and an interlayer insulating film 116 made of the insulating film 114 are formed (FIG. 28B).
[0141]
Thereafter, a wiring groove 118 that reaches the etching stopper film 112 through the insulating film 114 is opened by using a normal lithography technique and anisotropic etching technique. At this time, the etching condition is SiO 2 ₂ By setting the etching rate of the etching stopper film 112 made of the SiN film to be sufficiently smaller than the insulating film 114 made of the insulating film 114, the wiring groove 118 is formed in the etching stopper film 112 with the etching stopper film 112 being hardly etched. Open up to the top. The insulating film 114 is etched by, for example, C _Four F ₈ It is desirable to use reactive ion etching with a mixed gas plasma of Ar and Ar under conditions that can ensure a selectivity of 20 or more with respect to the etching stopper film 112.
[0142]
Following the etching of the insulating film 114, the etching stopper film 112 is etched to the top of the insulating film 126. At this time, the etching conditions are set such that the etching stopper film 112 made of SiN film is SiO 2. ₂ By setting the etching rate of the formed film insulating film 126 to be sufficiently low, the wiring groove 118 can be opened to the insulating film 126 with almost no etching of the insulating film 126 (FIG. 28C). )). Etching of the etching stopper film 112 is performed by, for example, SF. ₆ And O ₂ It is desirable that the reactive ion etching using the above is performed under conditions that can ensure a selectivity of 3 or more with respect to the insulating film 126.
[0143]
In the conventional structure shown in FIG. 35, since the underlying interlayer insulating film 104 and the contact plug 110 are exposed by this etching, the etching conditions are set by the trade-off of the etching selectivity of both to the etching stopper film 112. In the structure of the semiconductor device according to the embodiment, only the selection ratio of the insulating film 126 to the etching stopper film 112 needs to be considered, and the wiring trench 118 can be easily opened.
[0144]
Next, the insulating film 126 in the wiring groove 118 is etched, and the contact plug 110 is exposed in the wiring groove 116. At this time, since the interlayer insulating film 104 is exposed in the wiring trench 118, the interlayer insulating film 104 is also etched simultaneously with the etching of the insulating film 126. However, since the film thickness of the insulating film 126 is as thin as about 10 nm, Even when the amount of etching is taken into account, the film loss of the interlayer insulating film 104 due to the etching of the insulating film 126 is sufficiently small. Accordingly, there is no step in the wiring trench 118 that affects the contact characteristics (FIG. 29A).
[0145]
Note that the etching of the insulating film 126 can obtain a sufficient selection ratio with respect to the contact plug 110, so that the contact plug 110 is not etched.
Subsequently, a conductive film 120 connected to the contact plug 110 is formed on the inner wall and the bottom surface of the wiring groove 118.
[0146]
Thereafter, a Cu film is deposited by sputtering and reflow is performed, and Cu is embedded in the wiring trench 118. For example, Cu is sputtered at a pressure of 1.5 mTorr, power of 5 kW, and an Ar flow rate of 25 sccm, and Cu is reflowed at a temperature of 350 ° C., an Ar flow rate of 1000 sccm, and a pressure of 80 Torr.
Next, Cu on the interlayer insulating film 116 is removed by CMP to leave Cu only in the wiring trench 118. For example, CMP is performed using an alumina-based abrasive at a rotation speed of 100 rpm and a polishing pressure of 6 psi. Thus, the wiring 120 embedded in the wiring groove 116 is formed (FIG. 29B).
[0147]
As described above, according to the present embodiment, when forming the wiring 120 embedded in the interlayer insulating film 116 on the interlayer insulating film 104 in which the contact plug 110 is embedded, the etching stopper film 11 is formed. 2 Further below the insulating film 12 6 The etching stopper film 11 is used because the BLC structure having 2 Contact plug when etching 110 In addition, the interlayer insulating film 104 is not etched. This allows contact plugs 110 And wiring 12 2 Can be improved, and at the same time, the reliability of the semiconductor device can be improved.
[0148]
Note that the above-described process conditions are just examples, and even if these numerical values are changed to appropriate values, the effects of the present invention are not affected at all.
[0149]
【The invention's effect】
As described above, according to the present invention, the base substrate, the first insulating film formed on the base substrate, and the second insulating film formed on the first insulating film reach the base substrate. An interlayer insulating film in which the opening is formed, a conductive film formed on the inner wall and bottom of the opening, and a buried conductor formed in the opening in which the conductive film is formed. The opening width of the opening formed in the insulating film is wider than the opening width of the opening formed in the second insulating film, and is formed on the conductive film formed on the inner wall of the opening and the bottom of the opening. The conductive film is continuous with the conductive film, and the conductive film forms a region under the second insulating film in the opening formed in the first insulating film. Fill Therefore, when the conductive material is embedded in the opening, it is possible to prevent erosion of the base substrate due to the source gas of the conductive material and reaction between the conductive material and the base substrate. Can do. Thereby, the reliability of the semiconductor device can be improved.
Further, an interlayer insulating film comprising an underlying substrate, a first insulating film formed on the underlying substrate, and a second insulating film formed on the first insulating film and having an opening reaching the underlying substrate. An opening formed in the first insulating film, having a film, a conductive film formed on the inner wall and bottom of the opening, and a buried conductor formed in the opening in which the conductive film is formed Is wider than the opening width of the opening formed in the second insulating film, The conductive film is formed so as to completely surround the inside of the opening, A hole is formed under the second insulating film in the opening. Half Since the conductor device is configured, when the conductive material is embedded in the opening, it is possible to prevent erosion of the base substrate due to the source gas of the conductive material and reaction between the conductive material and the base substrate. Thereby, the reliability of the semiconductor device can be improved.
[0150]
Further, a base substrate that reacts with a source gas of a conductive material, a first insulating film formed on the base substrate, and a first insulating film are formed. Etching characteristics are different from the first insulating film Formed on the second insulating film and the second insulating film; Etching characteristics are the same as the first insulating film An interlayer insulating film having an opening reaching the base substrate, and an opening Whole bottom as well as inner wall And an embedded conductor formed using a source gas in the opening where the conductive film is formed, The first insulating film is thinner than the second insulating film, The opening width of the opening formed in the second insulating film is wider than the opening width of the opening formed in the third insulating film, and the opening width of the opening formed in the first insulating film is Since a semiconductor device that is substantially equal to the opening width of the opening formed in the third insulating film is configured, the base substrate can be completely isolated from the opening by conductive film formation. Accordingly, when the conductive material is embedded in the opening, it is possible to prevent erosion of the base substrate by the source gas of the conductive material and reaction between the conductive material and the base substrate.
[0152]
Further, the structure of the semiconductor device described above can be applied to any wiring layer in a multilayer wiring structure having a plurality of wiring layers.
In addition, a first insulating film deposition step of depositing a first insulating film on the base substrate, and a second insulating film having a different etching characteristic from the first insulating film are deposited on the first insulating film. The first insulating film is reached by anisotropically etching the second insulating film and the second insulating film deposition step. First By removing the first opening forming step for forming the opening and the first insulating film in the opening by a method in which etching proceeds in the lateral direction, First At the same time as opening the opening to the base substrate, the first insulating film under the second insulating film is etched to form a gap. To form a second opening A second opening forming step, Second To prevent the base substrate from being exposed in the opening, Formed on the inner wall and bottom of the second opening, At least void Second Aperture Side edge Conductive film Compost Conductive film deposition process to be stacked, and at least a conductive film is formed Second By manufacturing the semiconductor device by the embedded conductor forming step of forming the embedded conductor in the opening, the inside of the opening and the base substrate can be completely isolated by conductive film formation. Thus, when the conductive material is embedded in the opening in a later step, the base substrate is not eroded by the source gas of the conductive material, and the base substrate and the conductive material do not react. Thereby, the reliability of the semiconductor device can be improved.
Further, in the above method for manufacturing a semiconductor device, in the conductive film deposition step, the gap is removed. Fill Thus, a conductive film can be formed.
Further, in the above semiconductor device manufacturing method, in the conductive film deposition step, the conductive film can be formed such that holes remain in the gap.
[0153]
Further, in the above semiconductor device manufacturing method, if the conductive film is deposited by the collimated sputtering method, the opening of the gap can be easily closed.
Further, in the above method for manufacturing a semiconductor device, Second If the conductive film is deposited so that the film thickness of the conductive film at the bottom of the opening is larger than that of the first insulating film, the opening of the gap can be easily blocked.
[0154]
Further, in the above semiconductor device manufacturing method, if the conductive film is deposited by the CVD method, the conductive film can be embedded in the gap.
Further, in the above method for manufacturing a semiconductor device, Second If the conductive film is deposited so that the film thickness of the conductive film at the bottom of the opening is ½ or more of the film thickness of the first insulating film, the opening of the gap can be easily filled.
[0155]
In addition, a first insulating film deposition step of depositing a first insulating film on a base substrate that reacts with a source gas of a conductive material, and a first insulating film and etching characteristics on the first insulating film But Different Thicker than the first insulating film A second insulating film deposition step for depositing a second insulating film, and a second insulating film on the second insulating film; 1 Insulation film and etching characteristics Are equal A third insulating film deposition step for depositing a third insulating film, and a first opening forming step for forming an opening reaching the second insulating film by anisotropically etching the third insulating film And a second insulating film in the opening Isotropically Etchan To Thus, the second opening forming step for opening the opening to the first insulating film and the first insulating film in the opening are anisotropically etched to open the opening to the base substrate. And a third opening forming step Open Cover the base substrate exposed in the mouth On the inner wall and bottom of the opening By manufacturing a semiconductor device by a conductive film deposition step of depositing a conductive film and a step of forming a buried conductor using a source gas in the opening where the conductive film is formed, The inside of the opening and the base substrate can be completely isolated. Accordingly, even when the second insulating film needs to be isotropically etched in order to use the SAC structure, substrate erosion due to the source gas when the conductive material is embedded can be prevented. In addition, the reaction between the conductive material and the base substrate can be prevented.
[0156]
Further, in the above method for manufacturing a semiconductor device, if the overetching amount when etching the first insulating film is set to about 50% or less, the opening can be formed while suppressing damage to the base substrate. .
Further, the method for manufacturing a semiconductor device according to the present invention can be applied to any wiring layer formed in a multilayer wiring structure having a plurality of wiring layers.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view showing a structure of a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a process cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the invention;
FIG. 3 is a process cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the invention;
FIG. 4 is a diagram illustrating the principle of a collimated sputtering method.
FIG. 5 is a diagram for explaining an effect in the semiconductor device manufacturing method according to the first embodiment of the present invention;
FIG. 6 is a schematic cross-sectional view showing a structure of a semiconductor device according to a second embodiment of the present invention.
FIG. 7 is a process sectional view showing a method for producing a semiconductor device according to a second embodiment of the invention.
FIG. 8 is a diagram illustrating a buried wiring to which a BLC structure is applied.
FIG. 9 is a diagram illustrating a problem in a buried wiring using Cu.
10A and 10B are a plan view and a cross-sectional view showing the structure of a semiconductor device according to a third embodiment of the invention.
FIG. 11 is a process cross-sectional view (No. 1) illustrating the method for manufacturing the semiconductor device according to the third embodiment of the invention;
FIG. 12 is a process cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the third embodiment of the present invention;
FIG. 13 is a schematic cross-sectional view showing the structure of a semiconductor device according to a fourth embodiment of the present invention.
FIG. 14 is a process cross-sectional view (No. 1) illustrating the method for manufacturing the semiconductor device according to the fourth embodiment of the invention;
FIG. 15 is a process cross-sectional view (No. 2) illustrating the method for manufacturing the semiconductor device according to the fourth embodiment of the invention;
FIG. 16 is a process cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the fourth embodiment of the present invention;
FIG. 17 is a process cross-sectional view (No. 4) illustrating the method for manufacturing the semiconductor device according to the fourth embodiment of the invention;
18A and 18B are a plan view and a cross-sectional view showing the structure of a semiconductor device according to a fifth embodiment of the invention.
FIG. 19 is a process cross-sectional view (No. 1) illustrating the method for manufacturing the semiconductor device according to the fifth embodiment of the invention;
FIG. 20 is a process cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the fifth embodiment of the present invention;
FIG. 21 is a schematic sectional view showing the structure of a semiconductor device according to a sixth embodiment of the present invention.
FIG. 22 is a process cross-sectional view (No. 1) illustrating the method for manufacturing the semiconductor device according to the sixth embodiment of the invention;
FIG. 23 is a process cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the sixth embodiment of the present invention;
FIG. 24 is a schematic sectional view showing the structure of a semiconductor device according to a seventh embodiment of the present invention.
FIG. 25 is a process cross-sectional view (No. 1) illustrating the method for manufacturing the semiconductor device according to the seventh embodiment of the invention;
FIG. 26 is a process cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the seventh embodiment of the present invention;
FIG. 27 is a schematic sectional view showing the structure of a semiconductor device according to an eighth embodiment of the present invention.
FIG. 28 is a process cross-sectional view (No. 1) illustrating the method for manufacturing the semiconductor device according to the eighth embodiment of the invention;
FIG. 29 is a process cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the eighth embodiment of the present invention;
FIG. 30 is a diagram illustrating the structure of a conventional semiconductor device having a SAC structure.
FIG. 31 is a diagram illustrating a structure of a conventional semiconductor device having a BLC structure.
FIG. 32 is a diagram (part 1) for explaining problems of a conventional semiconductor device;
FIG. 33 is a (second) diagram for explaining a problem of the conventional semiconductor device;
FIG. 34 is a diagram (No. 3) for explaining a problem of the conventional semiconductor device.
FIG. 35 is a diagram (No. 4) for explaining a problem of the conventional semiconductor device.
FIG. 36 is a diagram (No. 5) for explaining a problem of the conventional semiconductor device.
FIG. 37 is a diagram (No. 6) for explaining a problem of the conventional semiconductor device.
FIG. 38 is a diagram (No. 7) for explaining a problem of the conventional semiconductor device.
FIG. 39 is a diagram (No. 8) for explaining a problem of the conventional semiconductor device.
[Explanation of symbols]
10 ... Semiconductor substrate
12 ... element isolation film
14 ... diffusion layer
16 ... Etching stopper film
18 ... Insulating film
20 ... Interlayer insulating film
22 ... Contact hole
24. Conductive film
26 ... Plug
28: Wiring layer
30 ... Hole
32. Insulating film
34 ... Gate oxide film
36 ... WF ₆ molecule
38. Insulating film
40 ... Gate electrode
42 ... sidewall
44 ... CoSi ₂ film
46 ... SOG film
48 ... Resist film
50 ... Target
52 ... Board
54 ... Collimator
60: Element region
62 ... Gate electrode
64 ... Gate electrode
66 ... wiring
68 ... Wiring groove
100: Semiconductor substrate
102 ... Contact hole
104 ... Interlayer insulating film
106 ... conductive film
108 ... Plug
110 ... Contact plug
112 ... Etching stopper film
114: Insulating film
116 ... Interlayer insulating film
118: Wiring groove
120 ... conductive film
122 ... Wiring
124 ... Hole
126 ... Insulating film
128: Insulating film
130 ... Etching stopper film
132. Insulating film
134 ... interlayer insulating film
136 ... via hole
138 ... Hole
140 ... conductive film
142 ... plug
144: Contact plug
146 ... high resistance reactant
200: Semiconductor substrate
202 ... Interlayer insulating film
204 ... Conductive film
206 ... Plug
208 ... Contact plug
210 ... Wiring
212 ... conductive film
214 ... Insulating film
216 ... Etching stopper film
218 ... Insulating film
220 ... interlayer insulating film
222 ... via hole
224 ... Hole
226 ... conductive film
228 ... Plug
230 ... Contact plug

Claims (14)

A base substrate;
An interlayer insulating film formed of a first insulating film formed on the base substrate and a second insulating film formed on the first insulating film, wherein an opening reaching the base substrate is formed;
A conductive film formed on the inner wall and bottom of the opening;
An embedded conductor formed in the opening in which the conductive film is formed,
The opening width of the opening formed in the first insulating film is wider than the opening width of the opening formed in the second insulating film,
The conductive film formed on the inner wall of the opening and the conductive film formed on the bottom of the opening are continuous,
The conductive film is formed so as to fill a region under the second insulating film in the opening formed in the first insulating film. A base substrate;
An interlayer insulating film formed of a first insulating film formed on the base substrate and a second insulating film formed on the first insulating film, wherein an opening reaching the base substrate is formed;
A conductive film formed on the inner wall and bottom of the opening;
An embedded conductor formed in the opening in which the conductive film is formed,
The opening width of the opening formed in the first insulating film is wider than the opening width of the opening formed in the second insulating film,
The conductive film is formed so as to completely surround the inside of the opening,
A void is formed under the second insulating film in the opening. A semiconductor device, wherein: A base substrate that reacts with a source gas of a conductive material;
A first insulating film formed on the base substrate; a second insulating film formed on the first insulating film and having different etching characteristics from the first insulating film; and the second insulating film An interlayer insulating film formed on the first insulating film and having a third insulating film having an etching characteristic equal to that of the first insulating film and having an opening reaching the base substrate;
A conductive film formed on the entire bottom and inner walls of the opening;
An embedded conductor formed by using the source gas in the opening in which the conductive film is formed;
The first insulating film is thinner than the second insulating film,
The opening width of the opening formed in the second insulating film is wider than the opening width of the opening formed in the third insulating film,
An opening width of the opening formed in the first insulating film is approximately equal to an opening width of the opening formed in the third insulating film. The semiconductor device according to any one of claims 1 to 3,
The base substrate further includes at least one wiring layer. A semiconductor device, wherein: A first insulating film deposition step of depositing a first insulating film on the base substrate;
A second insulating film deposition step of depositing a second insulating film having etching characteristics different from those of the first insulating film on the first insulating film;
A first opening forming step of forming a first opening reaching the first insulating film by anisotropically etching the second insulating film;
The first insulating film in the first opening is removed by a method in which etching proceeds in the lateral direction, so that the first opening is opened up to the base substrate and at the same time the second A second opening forming step of forming a second opening formed by etching the first insulating film under the insulating film to form a void;
As the underlying substrate within said second opening is not exposed, it is formed on the inner wall and bottom of the second opening, a conductive film which closes the end portion of the second opening side of at least the voids a conductive film depositing step of sedimentary,
And a buried conductor forming step of forming a buried conductor in at least the second opening in which the conductive film is formed. In the manufacturing method of the semiconductor device according to claim 5,
In the conductive film deposition step, the conductive film is formed so as to fill the gap. A method of manufacturing a semiconductor device, wherein: In the manufacturing method of the semiconductor device according to claim 5,
In the conductive film deposition step, the conductive film is formed so that holes remain in the gap. A method of manufacturing a semiconductor device, wherein: In the manufacturing method of the semiconductor device according to claim 5 or 7,
In the conductive film deposition step, the conductive film is deposited by a collimated sputtering method. The method of manufacturing a semiconductor device according to claim 8.
In the conductive film deposition step, the conductive film is deposited so that the film thickness of the conductive film at the bottom of the second opening is thicker than that of the first insulating film. A method for manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to claim 5 or 6,
In the conductive film deposition step, the conductive film is deposited by a CVD method. The method of manufacturing a semiconductor device according to claim 10.
In the conductive film deposition step, the conductive film is deposited so that the film thickness of the conductive film at the bottom of the second opening is ½ or more of the film thickness of the first insulating film. A method of manufacturing a semiconductor device. A first insulating film deposition step of depositing a first insulating film on a base substrate that reacts with a source gas of a conductive material;
On the first insulating film, a second insulating film depositing step of depositing said first insulating film and etching characteristics varies, the thicker than the first insulating film a second insulating film,
A third insulating film deposition step of depositing a third insulating film having etching characteristics equal to those of the first insulating film on the second insulating film;
A first opening forming step of forming an opening reaching the second insulating film by anisotropically etching the third insulating film;
By isotropically etching Holdings Rukoto the second insulating film in the opening, a second opening forming step of opening the opening to on the first insulating film,
A third opening forming step of opening the opening to the base substrate by anisotropically etching the first insulating film in the opening;
A conductive film deposition step of depositing a conductive film on the inner wall and bottom of the opening so as to cover the base substrate exposed in the opening ;
Forming a buried conductor using the source gas in the opening in which the conductive film is formed. A method for manufacturing a semiconductor device, comprising: In the manufacturing method of the semiconductor device according to claim 12,
In the third opening forming step, the amount of overetching when the first insulating film is etched is set to about 50% or less. In the manufacturing method of the semiconductor device according to claim 5,
The base substrate further includes at least one wiring layer. A method of manufacturing a semiconductor device, wherein:

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