KR101026476B1 - Phase-change random access memory device and method for manufacturing the same - Google Patents

Abstract

The present invention discloses a phase change memory device capable of reducing the amount of current required for phase change of a phase change film by reducing the contact area between a bottom electrode contact and a phase change film, and a method of manufacturing the same. The disclosed phase change memory device includes a first insulating film having a first contact hole formed on a semiconductor substrate having a predetermined substructure and exposing a portion of the substrate, and a lower electrode contact filling the first contact hole. And a second insulating film formed on the first insulating film including the lower electrode contact and exposing at least a portion of the lower electrode contact, and an upper electrode formed on the second insulating film and arranged on both sides corresponding to the lower electrode contact, respectively. And a first spacer covering both sidewalls of the upper electrode, and a phase change layer pattern formed on the resultant to fill the exposed portions of the second insulating layer and contact the lower electrode contact.

As described above, the present invention uses a spacer structure to reduce the contact area between the lower electrode contacts to 100 nm or less, so that the amount of current required for the phase change of the phase change film pattern, that is, the program of the phase change memory device is reduced. The amount of current required for operation can be reduced.

Description

Phase change memory device and its manufacturing method {PHASE-CHANGE RANDOM ACCESS MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME}

1 is a graph for explaining a method of programming and erasing a phase change memory device.

2 is a cross-sectional view for explaining a conventional phase change memory element.

3 is a cross-sectional view illustrating a phase change memory device according to an embodiment of the present invention.

4A to 4F are cross-sectional views illustrating processes of manufacturing a phase change memory device according to an embodiment of the present invention.

5 is a cross-sectional view illustrating a phase change memory device according to another embodiment of the present invention.

6A to 6G are cross-sectional views illustrating processes for manufacturing a phase change memory device according to another exemplary embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same. More particularly, the amount of current required for phase change of a phase change film is reduced by reducing the contact area between the bottom electrode contact and the phase change film. A phase change memory device for reducing and a method of manufacturing the same.

Semiconductor memory devices, such as DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory (SRAM)), are volatile and fast data input / output (RAM) products that lose data over time. If you input data once, you can maintain the status, but it can be classified into ROM products that have slow input / output data. Such typical memory elements represent logic '0' or logic '1' depending on the stored charge.

Here, the DRAM, which is a volatile memory device, requires high charge storage capability because periodic refresh operation is required, and thus many efforts have been made to increase the surface area of a capacitor electrode. However, increasing the surface area of the capacitor electrode makes it difficult to increase the integration of the DRAM device.

On the other hand, nonvolatile memory devices have almost indefinite storage capacities, and there is an increasing demand for flash memory devices that are electrically input and output such as EEPROM (Elecrtically Erasable and Programmable ROM).

Such flash memory cells generally have a vertically stacked gate structure having a floating gate formed on a silicon substrate. The multilayer gate structure typically includes one or more tunnel oxide or dielectric layers and a control gate formed on or around the floating gate, wherein the principle of writing or erasing data in the flash memory cell is based on the tunnel oxide layer. A method of tunneling charges is used. At this time, a higher operating voltage than the power supply voltage is required. As a result, the flash memory elements require a boosting circuit to form a voltage necessary for writing and erasing operations.

Therefore, many efforts have been made to develop a new memory device having a non-volatile characteristic and random access, and having a simple structure while increasing the integration of devices. A representative example is a phase-change random access memory (PRAM). )to be.

The phase change memory device widely uses a chalcogenide film as a phase change film. In this case, the chalcogenide film is a compound film containing germanium (Ge), stevidium (Sb), and tellurium (Te) (hereinafter referred to as a 'GST film'), wherein the GST film is provided with a current, that is, Joule According to Joule Heat, a reversible phase change occurs between the amorphous state and the crystalline state.

1 is a graph for explaining a method of programming and erasing a phase change memory device, in which the horizontal axis represents time and the vertical axis represents temperature applied to the phase change film.

As shown in FIG. 1, when the phase change film is heated at a temperature higher than the melting temperature (Tm) for a short time (first operating period; t ₁ ), the phase change film is cooled at a high speed. Change to Amorphous State (see curve 'A'). On the contrary, the phase change film is heated at a temperature lower than the melting temperature Tm and higher than the crystallization temperature Tc for a longer time than the first operating period t ₁ (second operating period t ₂ ). Upon cooling, the phase change film changes to Crystalline State (see curve 'B').

Here, the resistivity of the phase change film having an amorphous state is higher than that of the phase change film having a crystalline state. Accordingly, by detecting the current flowing through the phase change layer in the read mode, it is possible to determine whether the information stored in the phase change memory cell is logic '1' or logic '0'.

As described above, Joule heat is required for the phase change of the phase change film. In a conventional phase change memory device, when a high density current flows through an area in contact with a phase change film, the crystal state of the phase change film contact surface changes, and the smaller the contact surface, the smaller the state of phase change material changes. The current density required to make it smaller.

2 is a process cross-sectional view for explaining a phase change memory device according to the prior art.

As shown in FIG. 2, a phase change memory device according to the related art includes a bottom electrode 3 formed on a semiconductor substrate 1 having a predetermined substructure and the bottom electrode 3. A first insulating layer having a first contact hole formed on a substrate including the first contact hole to expose a portion of the lower electrode 3, a bottom electrode contact buried in the first contact hole and connected to the lower electrode; A second insulating layer formed on the lower electrode contact and the first insulating layer and having a second contact hole exposing the lower electrode contact, a phase change layer pattern filling the second contact hole, and a second insulating layer formed on the second insulating layer It is configured to include a top electrode (Top Electrode) connected to the phase change film pattern.

In the phase change memory device according to the related art having the above-described configuration, when a current flows between the lower electrode 3 and the upper electrode 17, the lower electrode contact 9 and the phase change layer pattern 15 The crystal state of the phase change film pattern of the contact surface 19 changes according to the current intensity (ie, heat) passing through the contact surface 19. At this time, the heat necessary to change the state of the phase change film pattern is directly affected by the contact surface 19 of the phase change film pattern 15 and the lower electrode contact 9. Therefore, the contact area between the phase change film pattern 15 and the lower electrode contact 9 should be as small as possible.

However, in such a conventional phase change memory device, since the lower electrode and the phase change film pattern are connected through the lower electrode contact, the contact area between the phase change film pattern and the lower electrode contact is entirely limited to the photo process for the contact hole. There is a difficulty in reducing the contact area due to limitations in the area. Thus, a problem arises in that the amount of current required for phase change is increased.

Accordingly, the present invention has been made to solve the above problems, by using a spacer structure to reduce the contact area between the lower electrode contact and the phase change film pattern to less than 100nm phase change of the phase change film pattern (Phase Change) It is an object of the present invention to provide a phase change memory device capable of reducing the amount of current required in the present invention and a method of manufacturing the same.

A phase change memory device of the present invention for achieving the above object is formed on a semiconductor substrate having a predetermined substructure and having a first insulating film having a first contact hole for exposing a portion of the substrate, the first contact A lower electrode contact filling the hole, a second insulating film formed on the first insulating film including the lower electrode contact and exposing at least a portion of the lower electrode contact, and both sides formed on the second insulating film and corresponding to the lower electrode contact. An upper electrode arranged at each of the portions, a first spacer covering both side walls of the upper electrode, and a phase change layer pattern formed on the resultant and filling the exposed portions of the second insulating layer to be in contact with the lower electrode contact; It is characterized in that the configuration.

And a third insulating layer formed on the second insulating layer to surround an upper surface of the upper electrode and enclosing a side surface of the upper electrode including the first spacer and exposing the lower electrode contact.

A second spacer is further included on side surfaces of the first spacer and the exposed second insulating layer.

The first spacer is made of a nitride film material, and the second spacer is made of an oxide film material.

A lower electrode connected to the lower electrode contact is interposed between the first insulating layer and the second insulating layer including the lower electrode contact.

The phase change layer pattern is in contact with the lower electrode contact by 0.1 m or less by the first spacer.

The phase change film pattern is made of a GST film, and any one of a GeSb2Te4 film and a Ge2Sb2Te5 film is used.

Meanwhile, the method of manufacturing a phase change memory device of the present invention includes forming a first insulating film on a semiconductor substrate having a predetermined substructure, and then etching a first insulating film to expose a first contact hole exposing a portion of the substrate. Forming a lower electrode contact to fill the first contact hole, forming a second insulating layer on the substrate including the lower electrode, and forming a second insulating layer on both sides of the second insulating layer. Forming an upper electrode on each side, forming a first spacer on both side walls of the upper electrode, and etching a second insulating layer using the upper electrode including the first spacer as a mask to form at least a portion of the lower electrode contact. And exposing the exposed portions of the second insulating layer to form a phase change layer pattern in contact with the lower electrode contact.

The method may further include forming a conductive film for the lower electrode connected to the lower electrode contact on the first insulating layer between the lower electrode contact forming process and the second insulating film forming process.

The method may further include forming a second spacer on side surfaces of the first spacer and the exposed second insulating layer between the etching of the second insulating layer and the forming of the phase change layer pattern.

The first spacer uses a nitride film and the second spacer uses an oxide film.

The phase change layer pattern is in contact with the lower electrode contact by 0.1 m or less by the first spacer.

Forming a third insulating layer on the substrate including the second insulating layer remaining after the etching between the step of etching the second insulating layer and the step of forming the phase change layer pattern, and etching the upper portion by etching the third insulating layer. The side surface of the upper electrode including the first spacer is exposed while exposing the upper surface of the electrode, further exposing the lower electrode contact.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a cross-sectional view illustrating a phase change memory device according to an embodiment of the present invention.

As shown in FIG. 3, the phase change memory device according to an exemplary embodiment of the present invention may be formed on a semiconductor substrate 30 having a predetermined substructure and exposing a portion of the substrate. a first insulating film 32 having a h3), a lower electrode contact 34 filling the first contact hole h3, and a first insulating film including the lower electrode contact 34 and formed at least on the lower electrode contact 34. ), A second insulating film 36 exposing a portion corresponding to the top layer 38, an upper electrode 38a arranged on both sides corresponding to the lower electrode contact 34 on the second insulating film 36, and an upper electrode 38a, respectively. Side surface of the upper electrode 38a including the first spacer 42 formed on the first spacer 42 and the second insulating layer 36 to expose the upper surface of the upper electrode 38a. A third insulating layer 46 surrounding the lower electrode contact 34 is surrounded, and the exposed portions of the third insulating layer 46 and the second insulating layer 36 are buried. Is configured to include the contact on the lower electrode 34. The phase change layer pattern 48 is in contact with.

The phase change film pattern 48 is formed of a GST film. Specifically, for example, the phase change film pattern 48 is formed using one of a GeSb2Te4 film and a Ge2Sb2Te5 film.

4A through 4F are cross-sectional views illustrating processes of manufacturing a phase change memory device according to an exemplary embodiment of the present invention.

In the method of manufacturing the phase change memory device according to the exemplary embodiment having the above structure, as shown in FIG. 4A, the first insulating layer 32 is formed on the semiconductor substrate 30 having a predetermined substructure. After forming, the first insulating layer 32 is etched to form a first contact hole h3 exposing a portion of the substrate.

Subsequently, as shown in FIG. 4B, a lower electrode contact 34 filling the first contact hole h3 is formed. In this case, the lower electrode contact 34 uses a polysilicon-based or metal-based material. Thereafter, the second insulating layer 36 and the upper electrode conductive layer 38 are sequentially formed on the substrate including the lower electrode contact 34. In this case, any one of HDP, USG, SOG, PSG, BPSG, HLD, and TEOS may be used as the second insulating layer 36. In addition, as the upper electrode conductive film 38, a polysilicon series or a metal series, which is the same material as the bottom electrode contact, is used.

Thereafter, as shown in FIG. 4C, a photoresist film is coated on the conductive film, and the photoresist film is exposed and developed to form a photoresist pattern 40 covering the upper electrode region. Then, the conductive film is used as the mask. The upper electrode 38a is formed on both sides of the second insulating layer 36 corresponding to the lower electrode contact 34 by etching. At this time, during the etching process, the second insulating layer 36 serves as an etching barrier.

Subsequently, as illustrated in FIG. 4D, a nitride film (not shown) is deposited on the substrate including the upper electrode 38a, and then the entire surface of the nitride film is etched to form an insulating spacer 42 on the side of the upper electrode 38a. Form. At this time, the interval between the insulating spacers 42 is to be formed to less than 0.1㎛.

Then, as shown in FIG. 4E, after forming a third insulating film (not shown) on the resultant, the third insulating film is etched to expose the top surface of the upper electrode 38a while exposing the insulating spacer 42. It surrounds the side of the upper electrode, including, to expose the portion corresponding to the lower electrode contact 34. Thereafter, the second insulating layer is etched using the third insulating layer, the insulating spacer 42, and the upper electrode 38a as a mask to form a second contact hole h4 exposing a portion of the lower electrode contact.

Subsequently, as shown in FIG. 4F, after the phase change film (not shown) and the hard mask nitride film (not shown) are sequentially formed on the substrate including the second contact hole h4, a photoresist pattern (not shown) is formed. By etching the hard mask nitride film and the phase change film in turn, the second contact hole h4 is buried so as to contact the lower electrode contact 34 with each of the phase change film pattern 48 and the hard mask 50. ). In this case, the phase change layer pattern 48 is in contact with the lower electrode contact 34 by 0.1 μm or less by the insulating spacer 42.                     

In the phase change memory device according to the exemplary embodiment of the present invention manufactured through the above process, the phase change layer pattern is in contact with the lower electrode by 0.1 µm or less by an insulating spacer and is overlaid with the upper electrode. Contact In this case, a portion where the phase change of the phase change layer pattern occurs is in contact with the lower electrode contact.

5 is a cross-sectional view illustrating a phase change memory device according to another exemplary embodiment of the present invention.

The phase change memory device according to another exemplary embodiment of the present invention may include a first contact hole (not shown) formed on a semiconductor substrate 60 having a predetermined substructure and exposing a portion of the substrate. a first insulating layer 62 having a h5, a lower electrode contact 64 filling the first contact hole h5, and a lower electrode contact 64 formed on the first insulating layer 62 and connected to the lower electrode contact 64. A second insulating film 68 formed on the first insulating film including the lower electrode 66 and the lower electrode 66 and exposing at least a portion corresponding to the lower electrode contact 64; An upper electrode 70a arranged at both sides corresponding to the lower electrode contact 64, a first insulating spacer 72 covering both side walls of the upper electrode 70a, a first insulating spacer 72, and an exposure A second insulating spacer 74 formed on the side surface of the second insulating film and a second insulating spacer 74 formed on the resultant. Each of the two contact holes h6 is embedded to include the phase change film pattern 76 and the hard mask 78 which are in contact with the lower electrode contact 64.

Here, the phase change film pattern 76 is made of a GST film, and specifically, any one of a GeSb2Te4 film and a Ge2Sb2Te5 film is used.

6A through 6G are cross-sectional views illustrating processes of manufacturing a phase change memory device according to another exemplary embodiment of the present invention.

In a method of manufacturing a phase change memory device according to another exemplary embodiment having the above structure, as illustrated in FIG. 6A, a first insulating layer 62 is formed on a semiconductor substrate 60 having a predetermined substructure. After forming, the first insulating layer 62 is etched to form a first contact hole h5 exposing a portion of the substrate.

Subsequently, as shown in FIG. 6B, a lower electrode contact 64 is formed to fill the first contact hole h5. In this case, the lower electrode contact 64 uses a polysilicon-based or metal-based material. Thereafter, a lower electrode conductive film 66, a second insulating film 68, and an upper electrode conductive film 70 are sequentially formed on the substrate including the lower electrode contact 64. In this case, as the lower electrode conductive film 66, a material of polycrystalline silicon or metal is used. In addition, the upper electrode conductive film 70 may be made of the same material or a different material as the lower electrode conductive film.

Thereafter, as illustrated in FIG. 6C, the conductive layer for the upper electrode is selectively etched using a photoresist pattern (not shown) or the like to remain on both sides of the lower electrode contact 64 on the second insulating layer 68. The upper electrode 70a is formed.

Next, as shown in FIG. 6D, a nitride film (not shown) is formed on the entire surface of the substrate including the upper electrode 70a, and the entire surface of the nitride film is etched to form a first insulating spacer on the sidewall of the upper electrode 70a. Form 72.                     

Next, as shown in FIG. 6E, the second insulating layer is etched using the upper electrode including the first insulating spacer as a mask to form a second contact hole h6.

Thereafter, as shown in FIG. 6F, after an oxide film (not shown) is formed on the entire surface of the substrate including the second contact hole h6, the oxide film is etched to the entire surface to form the second contact hole h6, that is, the first contact hole. The second insulating spacer 74 is formed on side surfaces of the insulating spacer 72 and the exposed second insulating layer. As a result, the open diameter of the lower electrode 66 is formed to be 100 nm or less by the first and second insulating spacers 72 and 74.

Subsequently, as shown in FIG. 6G, a phase change film (not shown) and a hard mask nitride film (not shown) are sequentially formed on the resultant, and then the nitride film for hard mask is formed using a photoresist pattern (not shown). And the phase change layer is etched to form the phase change layer pattern 76 and the hard mask 78 in contact with the lower electrode 66. At this time, any one of the GeSb2Te4 film and the Ge2Sb2Te5 film is used as the phase change film.

In the phase change memory device according to another embodiment of the present invention manufactured through the above process, the phase change layer pattern is brought into contact with the lower electrode by less than 100 nm by the first and second insulating spacers, and the upper electrode Is in contact with the overlay. At this time, the portion where the phase change of the phase change film pattern occurs is a portion in contact with the lower electrode (see C of FIG. 6G).

As described above, the present invention reduces the contact area between the phase change film pattern and the lower electrode contact or the lower electrode by using a spacer structure, so that the amount of current required for the phase change of the phase change film pattern, that is, the program of the phase change memory device. The amount of current required for operation can be reduced.

Claims (14)

A first insulating layer formed on a semiconductor substrate having a predetermined substructure and having a first contact hole exposing a portion of the substrate; A lower electrode contact filling the first contact hole; A second insulating layer formed on the first insulating layer including the lower electrode contact and exposing at least a portion of the lower electrode contact; An upper electrode arranged at both sides of the second insulating layer corresponding to the lower electrode contact; A first spacer covering both sidewalls of the upper electrode; And a phase change layer pattern contacting the lower electrode contact by filling an exposed portion of the second insulating layer between the upper electrodes including the first spacer. The semiconductor device of claim 1, further comprising a third insulating layer formed on the second insulating layer to surround a top surface of the upper electrode while exposing an upper surface of the upper electrode and exposing the lower electrode contact. A phase change memory device, characterized in that. The phase change memory device of claim 1, further comprising a second spacer on side surfaces of the first spacer and the exposed second insulating layer. The phase change memory device as claimed in claim 1, wherein the first spacer is formed of a nitride film and the second spacer is formed of an oxide film. The phase change memory device of claim 1, wherein a lower electrode connected to the lower electrode contact is interposed between the first insulating layer and the second insulating layer. The phase change memory device as claimed in claim 1, wherein the phase change layer pattern is in contact with the lower electrode contact by 0.1 μm or less by the first spacer. The phase change memory device as claimed in claim 1, wherein the phase change film pattern is formed of a GST film. 8. The phase change memory device as claimed in claim 7, wherein any one of a GeSb2Te4 film and a Ge2Sb2Te5 film is used as the GST film. Forming a first insulating layer on a semiconductor substrate having a predetermined substructure, and then etching the first insulating layer to form a first contact hole exposing a portion of the substrate; Forming a lower electrode contact to fill the first contact hole; Forming a second insulating film on the substrate including the lower electrode; Forming upper electrodes on both side portions of the second insulating layer corresponding to the lower electrode contacts; Forming a first spacer on both side walls of the upper electrode; Etching the second insulating layer using the upper electrode including the first spacer as a mask to form a second contact hole; And filling the second contact hole to form a phase change layer pattern in contact with the lower electrode contact. 10. The method of claim 9, further comprising forming a conductive film for the lower electrode connected to the lower electrode contact between the lower electrode contact forming step and the second insulating film forming step. The method of claim 9, further comprising forming a second spacer on side surfaces of the first spacer and the exposed second insulating layer between the etching of the second insulating layer and the forming of the phase change layer pattern. A method of manufacturing a phase change memory device, characterized in that. 12. The method of claim 11, wherein the first spacer uses a nitride film and the second spacer uses an oxide film. The method of claim 9, wherein the phase change layer pattern is in contact with the lower electrode contact by 0.1 μm or less by the first spacer. 10. The method of claim 9, between etching the second insulating film and forming the phase change film pattern. Forming a third insulating film on the substrate including the second insulating film remaining after the etching; And etching the third insulating layer to expose the upper surface of the upper electrode to surround the side surface of the upper electrode including the first spacer, and to expose the lower electrode contact. Manufacturing method.

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