KR20060002129A - Phase-change random access memory device and method for manufacturing the same - Google Patents

Abstract

The present invention discloses a phase change memory device and a method of manufacturing the same.

The phase change memory device according to the present invention is formed in an active region of a semiconductor substrate, and has a U-shaped gate electrode having a head for applying power to the gate electrode at one end thereof, and an active region formed outside the gate electrode. A source formed in the active region of the drain and gate electrode, a respective bit line contact connected to the drain and the source, a respective bit line connected to the bit line contact, and a lower electrode formed at a bit line portion corresponding to the source. And a lower electrode, a phase change layer pattern, and an upper electrode connected to the lower electrode contact.

Accordingly, the present invention forms the gate electrode in a “U” shape, so that the number of bit line contacts connected to the source formed inside the “U” shaped gate electrode is connected to the drain formed outside the gate electrode. It can be formed relatively less than. In addition, the present invention can also reduce the length of the bit line connected to the source to the length of the gate width to uniform the amount of current for the phase change of the phase change material.

Description

Phase change memory device and its manufacturing method {PHASE-CHANGE RANDOM ACCESS MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME}

1 is a graph for explaining a method of programming and erasing a phase change memory device.

2 is a plan view for explaining a phase change memory device according to the present invention;

3A to 3F are plan views of processes for explaining a method of manufacturing a phase change memory device according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly, to fabricate a gate electrode in a “U” shape, thereby reducing the number of bit line contacts connected to the source compared to the number of bit line contacts connected to the drain. In addition, the present invention relates to a phase change memory device capable of reducing the length of a bit line connected to a source and making the amount of current for phase change of a phase change material uniform, and a manufacturing method thereof.

Semiconductor memory devices, such as DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory (SRAM)), are volatile and fast data input / output (RAM) products that lose data over time. If you input data once, you can maintain the status, but it can be classified into ROM products that have slow input / output data. Such typical memory elements represent logic '0' or logic '1' depending on the stored charge.

Here, the DRAM, which is a volatile memory device, requires high charge storage capability because periodic refresh operation is required, and thus many efforts have been made to increase the surface area of a capacitor electrode. However, increasing the surface area of the capacitor electrode makes it difficult to increase the integration of the DRAM device.

On the other hand, nonvolatile memory devices have almost indefinite storage capacities, and there is an increasing demand for flash memory devices that are electrically input and output such as EEPROM (Elecrtically Erasable and Programmable ROM).

Such flash memory cells generally have a vertically stacked gate structure having a floating gate formed on a silicon substrate. The multilayer gate structure typically includes one or more tunnel oxide or dielectric layers and a control gate formed on or around the floating gate, wherein the principle of writing or erasing data in the flash memory cell is based on the tunnel oxide layer. A method of tunneling charges is used. At this time, a higher operating voltage than the power supply voltage is required. As a result, the flash memory elements require a boosting circuit to form a voltage necessary for writing and erasing operations.                         

Therefore, many efforts have been made to develop a new memory device having a non-volatile characteristic and a random access, and having a simple structure while increasing the degree of integration of the device. As a representative example, phase-change random access memory; PRAM).

The phase change memory device widely uses a chalcogenide film as a phase change film. In this case, the chalcogenide film is a compound film containing germanium (Ge), stevidium (Sb), and tellurium (Te) (hereinafter referred to as a 'GST film'), wherein the GST film is provided with a current, that is, Joule According to Joule Heat, a reversible phase change occurs between the amorphous state and the crystalline state.

1 is a graph for explaining a method of programming and erasing a phase change memory device, in which the horizontal axis represents time and the vertical axis represents temperature applied to the phase change film.

As shown in FIG. 1, when the phase change film is heated at a temperature higher than the melting temperature (Tm) for a short time (first operating period; t ₁ ) and then cooled rapidly (Quenching), the phase change film is amorphous. Change to Amorphous State (see curve 'A'). On the contrary, the phase change film is heated at a temperature lower than the melting temperature Tm and higher than the crystallization temperature Tc for a longer time than the first operating period t ₁ (second operating period t ₂ ). Upon cooling, the phase change film changes to Crystalline State (see curve 'B').

Here, the resistivity of the phase change film having an amorphous state is higher than that of the phase change film having a crystalline state. Accordingly, by detecting the current flowing through the phase change layer in the read mode, it is possible to determine whether the information stored in the phase change memory cell is logic '1' or logic '0'.

As described above, Joule heat is required for the phase change of the phase change film. In a conventional phase change memory device, when a high density current flows through an area in contact with a phase change film, the crystal state of the phase change film contact surface changes, and the smaller the contact surface, the smaller the state of phase change material changes. The current density required to make it smaller. At this time, a current of 1 mA or more is required for the phase change of the phase change film. In the case of a transistor using 0.18 μm CMOS, the gate electrode width must be 1 μm or more, so there is a problem of cell size due to the width of the gate electrode. .

In addition, since the same number of bit line contacts must be formed in the source where the drain and the GST cell are formed, there is a problem in that the substrate is lost, and the length of the bit line for connecting the bit line contacts connected to the source is equal to the width of the gate electrode. There is also a problem that must be formed long.

Accordingly, the present invention has been made to solve the above problems, and by forming the gate electrode in a "U" shape, the number of bit line contacts connected to the source can be reduced compared to the number of bit line contacts connected to the drain. It is also an object of the present invention to provide a phase change memory device capable of reducing the length of a bit line connected to a source to make a current amount uniform for phase change of a phase change material, and a manufacturing method thereof.

The phase change memory device of the present invention for achieving the above object is formed in the active region of the semiconductor substrate, the "U" shaped gate electrode having a head for applying power to the gate electrode at one end, the gate electrode A source formed in the drain and the inner active region of the gate electrode formed at an outer active region of the respective regions; a bit line contact connected to the drain and the source; And a lower electrode contact formed at a line portion, and each lower electrode, a phase change film pattern, and an upper electrode connected to the lower electrode contact.

The active region has a rectangular shape.

The gate electrode uses any one of polycrystalline silicon and metal series.

The number of bit line contacts connected to the drain is equal to or greater than the bit line contacts connected to the source.

The phase change film pattern may use any one of a GeSb2Te4 film and a Ge2Sb2Te5 film.

On the other hand, the method of manufacturing a phase change memory device according to the present invention comprises the steps of forming a "U" shaped gate electrode in the active region of the semiconductor substrate, a drain in the outer active region of the gate electrode, the inside of the gate electrode Forming respective sources in the active region, forming respective bit line contacts to be connected to the drain and the source, forming respective bit lines to be connected to the bit line contacts, and bits corresponding to the source. Forming a lower electrode contact in a line portion, and sequentially forming a lower electrode, a phase change film pattern, and an upper electrode to be connected to the lower electrode contact.

The active region is patterned in a rectangular shape using any one of a locos and a shallow trench process.

The gate electrode uses any one of polycrystalline silicon and metal series.

The gate electrode at one end forms a head for applying power to the gate electrode.

The source and drain are formed by implanting any one of an N type and a P type into the active region using a gate electrode as a mask. Here, one of P and As is used as the N-type ion, and one of B and BF ₂ is used as the P-type ion.

The number of bit line contacts connected to the drain is equal to or larger than the bit line contacts connected to the source.

The bit line contacts are simultaneously formed in the source and the drain.

The bit line contact may use any one of polycrystalline silicon and metal series.

According to the present invention, by forming the gate electrode in a “U” shape, the number of bit line contacts connected to the source can be reduced compared to the number of bit line contacts connected to the drain, and the length of the bit line connected to the source is reduced. Since the length can be reduced to the length of the gate width, the amount of current for the phase change of the phase change material can be made uniform.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a plan view illustrating a phase change memory device according to the present invention.

As shown in FIG. 2, the phase change memory device according to the present invention is formed in the active region 100 of a semiconductor substrate (not shown), and has a head (1) for applying power to the gate electrode at one end thereof. A U-shaped gate electrode 102 provided with C), a drain (not shown) formed in the active region outside the gate electrode 102, and a source (not shown) formed in the internal active region of the gate electrode 102; A drain formed in each bit line contact (not shown) connected to the drain and the source, each bit line 104 and 106 connected to the bit line contact, and a bit line portion 106 corresponding to the source. And an electrode contact (not shown), a lower electrode (not shown) connected to the lower electrode contact, a phase change film pattern (not shown), and an upper electrode 108. In this case, the active region 100 has a rectangular shape.

3A to 3F are plan views for each process for explaining a method of manufacturing a phase change memory device according to the present invention.

According to the method of manufacturing a phase change memory device having the above structure, as shown in FIG. 3A, a process of any one of a LOCOS or a shallow trench is performed on a semiconductor substrate (not shown). It is applied to form a rectangular active region 100.                     

Subsequently, as illustrated in FIG. 3B, a “U” shaped gate electrode 102 is formed by depositing and patterning a polycrystalline silicon or metal film on the active region 100. In this case, a head for applying power to the gate electrode 102 is formed at one end of the gate electrode 102. In addition, one of an N type and a P type ion is implanted into the entire surface of the substrate using the gate electrode 102 as a mask to form a source (not shown) and a drain (not shown). One of P and As is used, and one of B and BF ₂ is used as the P-type ion, and the drain is formed in the outer active region of the gate electrode, and the source is formed inside the gate electrode. It is formed in the active region.

Then, as shown in FIG. 3C, after forming a first conductive film on the entire surface of the substrate including the source and drain, each of the bit line contacts 103 connected to the drain and the source by etching the first conductive film. To form. In this case, the bit line contact 103 is simultaneously formed on the source and the drain. In addition, by manufacturing the gate electrode in a “U” shape, the bit line contacts connected to the drain are made the same or more than the number of bit line contacts connected to the source. In the present invention, an integral insulating film forming step will be omitted.

Thereafter, as shown in FIG. 3D, after forming the second conductive film on the entire surface of the substrate including the bit line contact, the second conductive film is etched to connect the bit lines 104 and 106 to the bit line contacts. Form. In this case, reference numeral 106 denotes a bit line connected to the source and may also be referred to as a bit line buffer layer connecting the sources. In addition, reference numeral 104 denotes a bit line connected to a drain and is connected to a sense amplifier.

Next, as shown in FIG. 3E, after forming a third conductive film on the resultant, the third conductive film is etched to form a lower electrode contact 107 at a bit line portion 106 corresponding to the source.

3F, a GST film (not shown) and a fourth conductive film (not shown) are sequentially formed on the substrate including the lower electrode contact 107, and then the fourth conductive film and the GST are formed. The film is patterned to form a phase change film pattern (not shown) and an upper electrode 108 which are connected to the lower electrode contact 107 in turn. In this case, any one of polysilicon and metal series is used as the first, second, third and fourth conductive films. In addition, any one of the GeSb2Te4 film and the Ge2Sb2Te5 film may be used as the phase change film material.

As described above, the present invention forms a gate electrode in a “U” shape, such that the number of bit line contacts connected to a source formed inside the “U” shaped gate electrode is connected to a drain formed outside the gate electrode. It can be formed relatively less than the number of line contacts. In addition, the present invention can also reduce the length of the bit line connected to the source to the length of the gate width to uniform the amount of current for the phase change of the phase change material.

Claims (15)

A “U” shaped gate electrode formed in the active region of the semiconductor substrate and having a head for applying power to the gate electrode at one end thereof; A drain formed in the outer active region of the gate electrode, a source formed in the inner active region of the gate electrode, Each bit line contact connected to the drain and the source; Each bit line connected to the bit line contact; A lower electrode contact formed at a bit line corresponding to the source; And a lower electrode, a phase change layer pattern, and an upper electrode connected to the lower electrode contacts. The phase change memory device as claimed in claim 1, wherein the active region has a rectangular shape. The phase change memory device as claimed in claim 1, wherein the gate electrode uses any one of polycrystalline silicon and metal series. The phase change memory device of claim 1, wherein the number of bit line contacts connected to the drain is equal to or larger than the bit line contacts connected to the source. The phase change memory device as claimed in claim 1, wherein the phase change film pattern is one of a GeSb2Te4 film and a Ge2Sb2Te5 film. Forming a “U” shaped gate electrode in an active region of the semiconductor substrate, Forming a drain in the outer active region of the gate electrode and a source in the inner active region of the gate electrode; Forming respective bitline contacts to be connected to the drain and the source; Forming each bit line to be connected to the bit line contact; Forming a lower electrode contact at a bit line corresponding to the source; And sequentially forming a lower electrode, a phase change layer pattern, and an upper electrode to be connected to the lower electrode contact. 7. The method of claim 6, wherein the active region is patterned in a rectangular shape using any one of a locos and a shallow trench process. The method of manufacturing a phase change memory device according to claim 6, wherein the gate electrode uses any one of polycrystalline silicon and metal series. 7. The method of claim 6, wherein the gate electrode has a head for applying power to the gate electrode at one end thereof. The method of claim 6, wherein the source and the drain are formed by implanting any one of an N type and a P type into the active region using a gate electrode as a mask. The method of manufacturing a phase change memory device according to claim 10, wherein any one of P and As is used as the N-type ion. The method of manufacturing a phase change memory device according to claim 10, wherein any one of B and BF ₂ is used as said P-type ion. 7. The method of claim 6, wherein the number of bit line contacts connected to the drain is equal to or larger than the bit line contacts connected to the source. The method of claim 6, wherein the bit line contact is simultaneously formed in the source and the drain. 7. The method of claim 6, wherein the bit line contact is made of one of polysilicon and a metal series.

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